TLE94003EP. Features. Potential applications. Product validation. Description

Transcription

1 Feaures Three half bridge power oupus Very low power consumpion in sleep mode 3.3V / 5V compaible inpus wih hyseresis All oupus wih overload and shor circui proecion Direc inerface for conrol and diagnosis Overemperaure proecion Over- and Undervolage lockou Cross-curren proecion Poenial applicaions HVAC Flap DC moors Monosable and bisable relays Side mirror x-y adjusmen Produc validaion Qualified for Auomoive Applicaions. Produc Validaion according o AEC-Q100 Descripion The TLE94003EP is a proeced riple half-bridge driver designed especially for auomoive moion conrol applicaions such as side mirror x-y adjusmen. I is par of a larger family offering half-bridge drivers from hree oupus o welve oupus wih direc inerface or SPI inerface. The half bridge drivers are designed o drive DC moor loads in sequenial or parallel operaion. Operaion modes forward (cw), reverse (ccw), brake and high impedance are conrolled from a direc inerface. I offers diagnosis feaures such as shor circui, power supply failure and overemperaure deecion. In combinaion wih is low quiescen curren, his device is aracive among ohers for auomoive applicaions. The small fine pich exposed pad package, PG-TSDSO-14, provides good hermal performance and reduces PCB-board space and coss. Type Package Marking TLE94003EP PG-TSDSO-14 TLE94003 Daashee

2 Table 1 Produc Summary Operaing Volage V S V Logic Supply Volage V DD V Maximum Supply Volage for Load Dump V S(LD) 40 V Proecion Minimum Overcurren Threshold I SD 0.9 A Maximum On-Sae Pah Resisance a T j = 150 C R DSON(oal)_HSx+LSy Ω Typical Quiescen Curren a T j = 85 C I SQ 0.1 µa Daashee 2 1.0

3 Table of Conens 1 Pin Configuraion Pin Assignmen Pin Definiions and Funcions Block Diagram Volage and curren definiion General Produc Characerisics Absolue Maximum Raings Funcional Range Thermal Resisance Elecrical Characerisics Characerizaion resuls General Descripion Power Supply Operaion modes Normal mode Sleep mode Rese Behaviour Reverse Polariy Proecion Half-Bridge Oupus Oupu Sages Diagnosis Monioring Proecion Shor Circui of Oupu o Supply or Ground Cross-curren proecion Temperaure monioring and shudown VS Undervolage Behaviour VS Overvolage Behaviour V DD Undervolage Applicaion Informaion Applicaion Diagram Thermal applicaion informaion Package Oulines Revision Hisory Daashee 3 1.0

4 Pin Configuraion 1 Pin Configuraion 1.1 Pin Assignmen IN 1 IN 2 IN 3 TEST VS OUT 3 OUT VDD EF EN2 EN1 N.U. OUT 2 GND Figure 1 Pin Configuraion TLE94003EP wih direc inerface 1.2 Pin Definiions and Funcions Pin Symbol Funcion 1 IN1 Direc inpu conrol for power half-bridge 1 2 IN2 Direc inpu conrol for power half-bridge 2 3 IN3 Direc inpu conrol for power half-bridge 3 4 TEST Tes inpu. This pin can be lef open or be erminaed o ground 5 VS Main supply volage for power half bridges. 6 OUT 3 Power half-bridge 3 7 OUT 1 Power half-bridge 1 8 GND Ground 9 OUT 2 Power half-bridge 2 10 N.U. No used. This pin should eiher be lef open or erminaed o ground. 11 EN1 Enable inpu for Half-bridges 1/2 wih inernal pull-down 12 EN2 Enable inpu for Half-bridge 3 wih inernal pull-down 13 EF Error Flag 14 VDD Logic supply volage EDP - Exposed Die Pad; For cooling and EMC purposes only - no usable as elecrical ground. Elecrical ground mus be provided by pins 8. 1) 1) The exposed die pad a he boom of he package allows beer hea dissipaion from he device via he PCB. The exposed pad (EP) mus be eiher lef open or conneced o GND. I is recommended o connec EP o GND for bes EMC and hermal performance. Daashee 4 1.0

5 Pin Configuraion Noe: No used (N.U.) pins and unused oupus are recommended o be lef unconneced (open) on he applicaion board. If N.U. pins or unused oupu pins are roued o an exernal connecor which leaves he PCB, hen hese oupus should have provision for a zero ohm jumper (depopulaed if unused) or ESD proecion. In oher words, hey should be reaed like used pins. Daashee 5 1.0

6 Block Diagram 2 Block Diagram VDD VS Triple Half Bridge Driver Direc Inerface UNDERVOLTAGE & OVERVOLTAGE MONITOR CHARGE PUMP EN1 EN2 IN1 IN2 IN3 EF BIAS & MONITOR LOGIC CONTROL & LATCH DIRECT INTERFACE ERROR DETECTION shor shor o o baery shor o o baery shor o o deecion baery shor o o deecion baery deecion baery deecion shor deecion o ground deecion overemperaure deecion open open load load deecion open deecion open load load deecion open load deecion deecion curren curren conrol curren conrol curren conrol curren conrol curren conrol shor conrol o shor baery shor o o o baery baery o shor o o deecion baery shor deecion o shor o deecion baery deecion deecion baery overemperaure deecion deecion deecion Power driver high-side high-side driver high-side driver driver driver high-side driver emp emp sensor emp sensor emp sensor emp sensor sensor low-side low-side driver low-side driver low-side low-side driver driver driver driver Power sage emp sensor OUT 1 OUT 2 OUT 3 Figure 2 GND Block Diagram TLE94003EP (Direc Inerface) Daashee 6 1.0

7 Block Diagram 2.1 Volage and curren definiion Figure 3 shows erms used in his daashee, wih associaed convenion for posiive values. V S I S V DD I DD I EF VDD EF VS V EFn V INx I IN1, IN2, IN3 I EN1,I EN2 IN1, IN2, IN3 EN1, EN2 Direc Inerface Driver OUT x I OUTx V DSHSx V DSLSx V ENx GND I GND Figure 3 Volage and Curren Definiion Daashee 7 1.0

8 General Produc Characerisics 3 General Produc Characerisics 3.1 Absolue Maximum Raings Table 2 Absolue Maximum Raings 1) T j = -40 C o +150 C Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Volages Supply volage V S V P_4.1.1 Supply Volage Slew Rae dv S /d 10 V/µs V S increasing and P_4.2.2 decreasing 1) Power half-bridge oupu volage V OUT V 0 V < V OUT < V 2) S P_4.1.2 Logic supply volage V DD V 0 V < V S < 40 V P_4.1.3 Logic inpu volages (EN1, EN2, IN1, IN2, IN3) Logic oupu volage (EF) Currens V ENn, V INn -0.3 VDD V 0 V < V S < 40 V 0 V < V DD < 5.5V V EF -0.3 VDD V 0 V < V S < 40 V 0 V < V DD < 5.5V 1) No subjec o producion es, specified by design 2) Also applicable o no used (N.U.) pins 3) ESD suscepibiliy, JEDEC HBM according o ANSI/ ESDA/ JEDEC JS001 (1.5 kω, 100pF) 4) ESD suscepibiliy, Charged Device Model CDM according JEDEC JESD22-C101 P_ P_ Coninuous Supply Curren for V S I S A P_ Curren per GND pin I GND A P_ Oupu Currens I OUT A P_ Temperaures Juncion emperaure T j C P_4.1.8 Sorage emperaure T sg C P_4.1.9 ESD Suscepibiliy ESD suscepibiliy OUTn and VS pins versus GND. All oher pins grounded. V ESD -4 4 kv JEDEC HBM 1)3) P_ ESD suscepibiliy all pins V ESD -2 2 kv JEDEC HBM 1)3) P_ ESD suscepibiliy all pins V ESD V CDM 1)4) P_ ESD suscepibiliy corner pins V ESD V CDM 1)4) P_ Noes 1. Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Daashee 8 1.0

9 General Produc Characerisics 2. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. Daashee 9 1.0

10 General Produc Characerisics 3.2 Funcional Range Table 3 Funcional Range Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Supply volage range for V S(nor) V P_4.2.1 normal operaion Logic supply volage range for V DD V P_4.2.3 normal operaion Logic inpu volages V INn, V ENn V P_4.2.6 (EN1, EN2, IN1, IN2, IN3) Juncion emperaure T j C P_4.2.5 Noe: Wihin he normal funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. Daashee

11 General Produc Characerisics 3.3 Thermal Resisance Table 4 Thermal Resisance TLE94003EP Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Juncion o Case, T A = -40 C R hjc_cold 16 K/W 1) Juncion o Case, T A = 85 C R hjc_ho 19 K/W 1) Juncion o ambien, T A = -40 C (1s0p, minimal fooprin) Juncion o ambien, T A = 85 C (1s0p, minimal fooprin) Juncion o ambien, T A = -40 C (1s0p, 300mm2 Cu) R hja_cold_ min R hja_ho_m in R hja_cold_ K/W 1) 2) 148 K/W 1) 2) 79 K/W 1) 3) Number Juncion o ambien, T A = 85 C R hja_ho_30 95 K/W 1) 3) (1s0p, 300mm2 Cu) 0 Juncion o ambien, T A = -40 C R hja_cold_6 77 K/W 1) 4) (1s0p, 600mm2 Cu) 00 Juncion o ambien, T A = 85 C R hja_ho_60 94 K/W 1) 4) (1s0p, 600mm2 Cu) 0 Juncion o ambien, T A = -40 C R hja_cold_2 63 K/W 1) 5) (2s2p) s2p Juncion o ambien, T A = 85 C R hja_ho_2s 82 K/W 1) 5) (2s2p) 2p 1) No subjec o producion es, specified by design. 2) Specified R hja value is according o JEDEC JESD51-2, -3 a naural convecion on FR4 1s0p board; The produc (chip + package) was simulaed on a 76.2 x x 1.5mm board wih minimal fooprin copper area and 35µm hickness. Ta = -40 C, each channel dissipaes 0.2W. Ta = 85 C, each channel dissipaes 0.135W. 3) Specified R hja value is according o JEDEC JESD51-2, -3 a naural convecion on FR4 1s0p board; The produc (chip + package) was simulaed on a 76.2 x x 1.5mm board wih addiional cooling of 300mm2 copper area and 35µm hickness. Ta = -40 C, each channel dissipaes 0.2W. Ta = 85 C, each channel dissipaes 0.135W. 4) Specified R hja value is according o JEDEC JESD51-2, -3 a naural convecion on FR4 1s0p board; The produc (chip + package) was simulaed on a 76.2 x x 1.5mm board wih addiional cooling of 600mm2 copper area and 35µm hickness. Ta = -40 C, each channel dissipaes 0.2W. Ta = 85 C, each channel dissipaes 0.135W. 5) Specified R hja value is according o JEDEC JESD51-2, -3 a naural convecion on FR4 2s2p board; The produc (chip + package) was simulaed on a 76.2 x x 1.5mm board wih wo inner copper layers ( 4 x 35µm Cu). Ta = -40 C, each channel dissipaes 0.2W. Ta = 85 C, each channel dissipaes 0.135W. Daashee

12 General Produc Characerisics 3.4 Elecrical Characerisics Table 5 Elecrical Characerisics, V S =5.5 V o 20 V, V DD = 3.0V o 5.5V, T j = -40 C o +150 C, EN1= HIGH and EN2= HIGH, I OUTn = 0 A; Typical values refer o V DD = 5.0 V, V S = 13.5 V and T J = 25 C unless oherwise specified; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Curren Consumpion, EN1 = EN2 = GND Supply Quiescen curren I SQ µa -40 C T j 85 C P_4.4.1 Logic supply quiescen curren I DD_Q µa -40 C T j 85 C P_4.4.2 Toal quiescen curren I SQ + I DD_Q µa -40 C T j 85 C P_4.4.3 Curren Consumpion, EN=HIGH Supply curren I S_HSON ma All high-sides ON 1)2) P_ Logic supply curren I DD ma P_4.4.5 Over- and Undervolage Lockou Undervolage Swich ON V UV ON V V S increasing P_4.4.8 volage hreshold Undervolage Swich OFF V UV OFF V V S decreasing P_4.4.9 volage hreshold Undervolage Swich ON/OFF V UV HY 0.40 V V UV ON - V 2) UV OFF P_ hyseresis Overvolage Swich OFF volage V OV OFF V V S increasing P_ hreshold Overvolage Swich ON volage V OV ON V V S decreasing P_ hreshold Overvolage Swich ON/OFF V OV HY 1 V V OV OFF - V 2) OV ON P_ hyseresis V DD Power-On-Rese V DD POR V V DD increasing P_ V DD Power-Off-Rese V DD POffR V V DD decreasing P_ V DD Power ON/OFF hyseresis V DD POR HY 0.06 V V DD POR - V 2) DD POffR P_ Saic Drain-source ON-Resisance (High-Side or Low-Side) High-Side or Low-Side R DSON (all oupus) High-Side or Low-Side R DSON (all oupus) R DSON_HB_25C mω I OUT = ±0.5 A; T j = 25 C R DSON_HB_ mω I OUT = ±0.5 A; T j = 150 C C P_ P_ Oupu Proecion and Diagnosis of high-side (HS) channels of half-bridge oupu HS Overcurren Shudown Threshold I SD_HS A See Figure 7 P_ Difference beween shudown and limi curren I LIM_HS A 2) I LIM_HS I SD_HS I SD_HS See Figure 7 P_ Daashee

13 General Produc Characerisics Table 5 Elecrical Characerisics, V S =5.5 V o 20 V, V DD = 3.0V o 5.5V, T j = -40 C o +150 C, EN1= HIGH and EN2= HIGH, I OUTn = 0 A; Typical values refer o V DD = 5.0 V, V S = 13.5 V and T J = 25 C unless oherwise specified; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) (con d) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Overcurren Shudown filer ime dsd_hs µs 2) P_ Oupu Proecion and Diagnosis of low-side (LS) channels of half-bridge oupu LS Overcurren Shudown Threshold I SD_LS A See Figure 8 P_ Difference beween shudown and limi curren Overcurren Shudown filer ime I LIM_LS A I SD_LS dsd_ls µs 2) I LIM_LS I SD_LS Figure 8 Oupus OUT(1...n) leakage curren HS leakage curren in off sae I QLHn_NOR µa V OUTn = 0V ; OUT1/2: EN1=GND, EN2=High; OUT3: EN1=High,EN2=GN D HS leakage curren in off sae I QLHn_SLE µa V OUTn = 0V; EN1 = EN2 =GND LS Leakage curren in off sae I QLLn_NOR µa V OUTn = V S ; OUT1/2: EN1=GND, EN2=High; OUT3: EN1=High,EN2=GN D LS Leakage curren in off sae I QLLn_SLE µa V OUTn = V S ; EN1 = EN2 =GND Oupu Swiching Times. See Figure 9 and Figure 10. Slew rae of high-side and lowside oupus Oupu delay ime high side driver on Oupu delay ime high side driver off Oupu delay ime low side driver on Oupu delay ime low side driver off Cross curren proecion ime, high o low Cross curren proecion ime, low o high P_ Daashee ) P_ P_ P_ P_ P_ d VOUT / d V/µs Resisive load = 100Ω; V S =13.5V 3) P_ donh µs Resisive load = 100Ω o GND doffh µs Resisive load = 100Ω o GND donl µs Resisive load = 100Ω o VS doffl µs Resisive load = 100Ω o VS DHL µs Resisive load = 100Ω 2) DLH µs Resisive load = 100Ω 2) P_ P_ P_ P_ P_ P_4.4.42

14 General Produc Characerisics Table 5 Elecrical Characerisics, V S =5.5 V o 20 V, V DD = 3.0V o 5.5V, T j = -40 C o +150 C, EN1= HIGH and EN2= HIGH, I OUTn = 0 A; Typical values refer o V DD = 5.0 V, V S = 13.5 V and T J = 25 C unless oherwise specified; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) (con d) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion V DD V P_ V P_ Inpu Inerface: Logic Inpus EN1, EN2 Se up ime afer sleep mode SET_DI 150 µs 2) See Figure 5 P_ High-inpu volage V ENH 0.7 * V DD V P_ V DD Low-inpu volage V ENL * V P_ V DD Hyseresis of inpu volage V ENHY 500 mv 2) P_ Pull down resisor R PD_EN kω V EN = 0.2 x V DD P_ EF rese ime EF_RESET 250 ns 2) Se ENx o Low for EF_RESET o rese EF P_ Inpu Inerface: Logic Inpus IN1, IN2, IN3 High inpu volage hreshold V INnH 0.7 * V DD Low inpu volage hreshold V INnL * V DD Hyseresis of inpu volage V INnHY 500 mv 2) P_ Pull-down resisor R PD kω P_ Oupu Inerface: Logic Oupu EF High oupu volage level V EFH V DD V DD V DD V I EFH = -1.6 ma P_ Low oupu volage level V EFL V I EFL = 1.6 ma P_ Leakage curren I EFLK -1 1 µa 0V < V EF < 5.5V P_ Thermal Shudown Thermal shudown juncion T jsd C See Figure 11 2) P_ emperaure Thermal comparaor hyseresis T jhys 4 C 2) P_ ) I S_HSON does no include he load curren 2) No subjec o producion es, specified by design 3) Measured for 20% - 80% of V S. Daashee

15 Characerizaion resuls 4 Characerizaion resuls Performed on 5 devices, over operaing emperaure and nominal/exended supply range. Typical performance characerisics Supply quiescen curren Supply curren 2.9 P_ P_ ISQ [ua] 1.4 IS[mA] Juncion Temperaure [ C] Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20 VS=22V VS=13.5V VS=18V VS=20V VS=22V Logic supply quiescen curren Logic supply curren 0.7 P_ P_ IDD_Q[uA] IDD[mA] Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20V VS=22V Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20V VS=22V Daashee

16 Characerizaion resuls HS saic Drain-source ON-resisance LS saic Drain-source ON-resisance 1500 P_4.4.16/P_ P_4.4.16/P_ RDSON_HS [mω] RDSON_LS [mω] Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20V VS=22V Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20V VS=22V HS saic drain-source ON-resisance VS = 13.5V and VDD = 5V LS saic drain-source ON-resisance VS = 13.5V and VDD = 5V RDSON_HS [mω] P_4.4.16/P_ RDSON_LS [mω] LS Saic Drain-source ON-Resisance P_4.4.16/P_ Juncion Temperaure [ C] OUT1 OUT2 OUT Juncion Temperaure [ C] OUT1 OUT2 OUT3 Daashee

17 Characerizaion resuls Slew rae ON of high-side oupus Slew rae ON of low-side oupus 0.60 P_ P_ dvout/ d [V/us] dvout/ d [V/us] Juncion Temperaure [ C] Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20V VS=22 VS=5.5V VS=13.5V VS=18V VS=20V VS=22V Slew rae OFF of high-side oupus Slew rae OFF of low-side oupus 0.55 P_ P_ dvout/ d [V/us] dvout/ d [V/us] Juncion Temperaure [ C] VS=5.5V VS=13V5 VS=18V VS=20V VS=22V Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20V VS=22V Daashee

18 Characerizaion resuls HS overcurren shudown hreshold LS overcurren shudown hreshold P_ P_ ISD_HS [ma] ISD_LS [ma] Juncion Temperaure [ C] Juncion Temperaure [ C] VS=5.5V VS=13.5V VS=18V VS=20V VS=22V VS=5.5V VS=13.5 VS=18V VS=20V VS=22V Undervolage swich ON volage hreshold Undervolage swich OFF volage hreshold 5.05 P_ P_ VUV_ON [V] 4.95 VUV_OFF [V] Juncion Temperaure [ C] Juncion Temperaure [ C] VDD=3V VDD=5V VDD=5.5V VDD=3V VDD=5V VDD=5.5V Daashee

19 Characerizaion resuls Overvolage swich ON volage hreshold Overvolage swich OFF volage hreshold 22.8 P_ P_ VOV_ON [V] VOV_OFF [V] Juncion Temperaure [ C] Juncion Temperaure [ C] VDD=3V VDD=5V VDD=5.5V VDD=3V VDD=5V VDD=5.5V VDD Power-on-rese and VDD Power-off-rese 2.68 P_4.4.14/P_ VDD hreshold [V] Juncion Temperaure [ C] VDD POR VDD POffR Daashee

20 General Descripion 5 General Descripion 5.1 Power Supply The TLE94003EP has wo power supply inpus, V S and V DD. The half bridge oupus are supplied by V S, which is conneced o he 12V auomoive supply rail. V DD is used o supply he I/O buffers and inernal volage regulaor of he device. V S and V DD supplies are separaed so ha informaion sored in he logic block remains inac in he even of volage drop ous or disurbances on V S. The sysem can herefore coninue o operae once V S has recovered, wihou having o resend commands o he device. A rising edge on V DD crossing V DD POR riggers an inernal Power-On Rese (POR) o iniialize he IC a power-on. All daa sored inernally is deleed, and he oupus are swiched off (high impedance). An elecrolyic and 100nF ceramic capaciors are recommended o be placed as close as possible o he V S supply pin of he device for improved EMC performance in he high and low frequency band. The elecrolyic capacior mus be dimensioned o preven he VS volage from exceeding he absolue maximum raing. In addiion, decoupling capaciors are recommended on he V DD supply pin. 5.2 Operaion modes Normal mode The TLE94003EP eners normal mode by seing EN1 or EN2 o High. In normal mode, he charge pump is acive and all oupu ransisors can be acivaed or deacivaed according o Chaper Sleep mode The TLE94003EP eners sleep mode by seing he EN1 and EN2 pins o Low. The EN1 and EN2 inpus have an inernal pull-down resisor. In sleep mode, all oupu ransisors are urned off and he logic conen is rese. The curren consumpion is reduced o I SQ + I DD_Q. 5.3 Rese Behaviour The following rese riggers have been implemened in he TLE94003EP: V DD Undervolage Rese: The digial block will be deacivaed, he logic conens cleared and he oupu sages are swiched off if V DD is below he undervolage hreshold, V DD POffR. The digial block is iniialized once V DD volage levels is above he undervolage hreshold, V DD POR. Rese on EN1/2 pins: If he EN1/2 pins are pulled Low, he logic conen is rese and he device eners sleep mode. 5.4 Reverse Polariy Proecion The TLE94003EP requires an exernal reverse polariy proecion. During reverse polariy, he free-wheeling diodes across he half bridge oupu will begin o conduc, causing an undesired curren flow (I RB ) from ground poenial o baery and excessive power dissipaion across he diodes. As such, a reverse polariy proecion diode is recommended (see Figure 4). Daashee

21 General Descripion GND a) b) VBAT DRP CS2 CS HSx HSx OUTx OUTx LSx LSx IRB VBAT GND Figure 4 Reverse Polariy Proecion Daashee

22 Half-Bridge Oupus 6 Half-Bridge Oupus The half-bridge oupus of he TLE94003EP are inended o drive moor loads. They consis of a oal of hree DMOS half-bridges, which can be driven eiher coninuously or in PWM via INx pins. The oupu sages inegraed circuis proec he oupus agains overcurren and overemperaure. 6.1 Oupu Sages EN1 and EN2 inpus conrol he sae of he device according o Table 6. When EN1 = 0 and EN2 = 0, he device eners sleep mode wih low power consumpion and all oupus are OFF (high impedance). When EN1=1, HB1 and HB2 are enabled When EN2=1, HB3 is enabled Table 6 Device saes EN1 EN2 HB1/2 HB 3 Device sae 0 0 OFF OFF Sleep mode, all oupus are OFF 0 1 OFF Enabled Device is in normal mode 1 0 Enabled OFF Device is in normal mode 1 1 Enabled Enabled Device is in normal mode Noe: Afer he ransiion from sleep mode o normal mode, he oupus are OFF for a duraion SET_DI.See Figure 5 V ENx H L OUT x Acive High-Z EN1 = EN2 = Low Sleep mode EN1 and/or EN2 = High Normal mode SE T _DI Time Time OUTx is acive if he corresponding ENx = High Figure 5 Oupu seup ime afer a ransiion from sandby o normal mode The conrol inpus consis of CMOS-compaible schmi-riggers wih hyseresis. There are alogeher hree conrol inpus, i.e. IN1, IN2 and IN3 wih inernal pull-down resisors. If EN1 = 0, HB1 and HB2 are OFF. If EN1 = 1, HB1 and HB2 are conrolled according otable 7 Table 7 Funcional Truh Table for HB1 and HB2 EN1 IN1 IN2 HB1 HB2 Mode 0 X X OFF OFF HB1 and HB2 are OFF L L Brake Low Daashee

23 Half-Bridge Oupus Table 7 Funcional Truh Table for HB1 and HB2 EN1 IN1 IN2 HB1 HB2 Mode L H Moor couner-clockwise H L Moor clockwise H H Brake High If EN2 = 0, HB3 is high impedance. If EN2 = 1, he saes of HB3 is conrolled according otable 8 Table 8 Funcional Truh able for HB3 EN2 IN3 HB3 0 X OFF 1 0 L 1 1 H If wo moors are conneced in cascaded configuraion (see Figure 6), he moors and he half-bridges behave according o Table 9. VDD EN1 EN2 EF IN1 IN2 VS TLE94003EL OUT1 OUT2 M1 M2 IN3 OUT3 GND Figure 6 TLE94003EP wih wo moors in cascaded configuraion Table 9 Funcional Truh Table for HB1, HB2 and HB3 conrolling wo cascaded moors EN1 EN2 IN1 IN2 IN3 HB1 HB2 HB3 Moor1 Moor X X X OFF OFF OFF OFF OFF X L L OFF Brake Low OFF X L H OFF Couner-clockwise OFF X H L OFF Clockwise OFF X H H OFF Brake High OFF L L L Brake Low Brake Low L L H Brake Low Couner-clockwise L H L Couner-clockwise Clockwise L H H Couner-clockwise Brake High H L L Clockwise Brake Low Daashee

24 Half-Bridge Oupus Table 9 Funcional Truh Table for HB1, HB2 and HB3 conrolling wo cascaded moors EN1 EN2 IN1 IN2 IN3 HB1 HB2 HB3 Moor1 Moor H L H Clockwise Couner-clockwise H H L Brake High Clockwise H H H Brake High Brake High Daashee

25 Half-Bridge Oupus 6.2 Diagnosis Monioring The EF pin (push-pull oupu) repors he following error condiions: Overcurren (OC) Overemperaure (OT) VS overvolage and VS undervolage EF repors an overcurren even on HB1/2 only if EN1 = 1. Likewise, EF repors an overcurren on HB3 only if EN2 = 1. Afer an overcurren even is deeced on HB1/2, EF is lached o 1, unil EN1 = 0.Likewise, afer an overcurren even deeced on HB3, EF is lached o 1 unil EN2 = 0. EF repors overemperaure or VS overvolage/undervolage evens if he device is in normal mode (EN1 = 1 or EN2 = 1). The error flag is lached o 1 for hese faul condiions unil EN1 = 0 and EN2 = 0 Table 10 Error reporing by EF pin EN1 EN2 Error repored by EF pin 0 0 No applicable, he device is in sleep mode 1 0 OC on HB1/2, OT, VS under/overvolage 0 1 OC on HB3, OT, VS under/overvolage 1 1 OC on HB1/2, OC on HB3, OT, VS under/overvolage The able below depics he EF behaviour: Table 11 Error flag behaviour and rese condiions Faul condiion EF Rese condiions No faul 0 Overcurren on HB1 or HB2 1 (lached) Se EN1 pin o 0 for EF_RESET Overcurren on HB3 1 (lached) Se EN2 pin o 0 for EF_RESET VS overvolage 1 (lached) V S < V OV ON, EN1 = 0 and EN2 = 0 for EF_RESET VS undervolage 1 (lached) V S > V UV ON, EN1 = 0 and EN2 = 0 for EF_RESET Overemperaure 1 (lached) EN1 = 0 and EN2 = 0 for EF_RESET 6.3 Proecion This device has embedded proecive funcions which are designed o preven he desrucion of he device under faul condiions described in his secion. Faul condiions are reaed as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion Shor Circui of Oupu o Supply or Ground The high-side swiches are proeced agains shor circuis o ground whereas he low-side swiches are proeced agains shor circuis o supply. The high-side and low-side swiches will ener ino an over-curren condiion if he curren wihin he swich exceeds he overcurren shudown deecion hreshold, I SD. Upon deecion of he I SD hreshold, an Daashee

26 Half-Bridge Oupus overcurren shudown filer, dsd is begun. As he curren rises beyond he hreshold I SD, i will be limied by he curren limi hreshold, I LIM. Upon expiry of he overcurren shudown filer ime, he affeced power swich is lached off (see Figure 7 and Figure 8) and he EF is se o 1 and lached. The fauly power swich remains deacivaed and EF is lached as long as he corresponding ENx =1. To resume normal funcionaliy of he power swich (in he even he overcurren condiion disappears or o verify if he failure sill exiss) he microconroller shall: 1. clear he error flag by seing he corresponding ENx o 0 (see Table 11) 2. se he corresponding ENx o 1 in order o re-enable he corresponding half-bridges VS I HS ON OUTn I I LIM_HS I I I SD_HS I I I LIM_HS - I SD_HS I Shor o GND dsd_ HS Shor condiion on High-Side Swich Figure 7 High-Side Swich - Shor Circui and Overcurren Proecion VS VS I LS OUTn Shor o Supply I LIM_LS I SD_LS I LIM_LS -I SD_LS ON Figure 8 Low-Side Swich - Shor Circui and Overcurren Proecion dsd_ls Shor condiion on Low-Side Swich Cross-curren proecion In bridge configuraions he high-side and low-side power ransisors are ensured never o be simulaneously ON o avoid cross currens. This is achieved by inegraing delays in he driver sage of he power oupus o creae a dead-ime beween swiching off of one power ransisor and swiching on of he adjacen power ransisor wihin he half-bridge. The dead imes, DHL and DLH, as shown in Figure 9 case 3 and Figure 10 case 3, have been specified o ensure ha he swiching slopes do no overlap wih each oher. This prevens a cross conducion even. Daashee

27 Half-Bridge Oupus Case 1: Delay Time High Side Driver OFF INx If x = 1 or 2, hen y = 1 and z =2 Oherwise y = 2 and z =1 Previous Sae New Sae HS ON HS OFF ENy LS OFF LS OFF ENz VOUT_HSx [V] VS 80% 1) doffh GND 1) Delay ime HS OFF 20% Case 2: Delay Time Low Side Driver ON INx Previous Sae New Sae HS OFF HS OFF LS OFF LS ON ENy ENz VOUT_LSx [V] VS 80% donl 2) 20% GND 2) Delay ime LS ON wihou dead ime ; HS previously OFF Case 3: Delay Time Low Side Driver ON wih DHL dead ime INx Previous Sae New Sae HS ON HS OFF ENy LS OFF LS ON VOUT_LSx [V] VS Low-Side ON delay ime donl + DHL 3) 80% 20% GND 3) Delay ime LS ON wih dead ime ; HS previously ON Figure 9 Half bridge oupus swiching imes - high-side o low-side ransiion Daashee

28 Half-Bridge Oupus Case 1: Delay Time High Side Driver OFF INx If x = 1 or 2, hen y = 1 and z =2 Oherwise y = 2 and z =1 Previous Sae New Sae HS OFF HS OFF LS ON LS OFF ENy ENz VOUT_LSx [V] VS 80% doffl 1) GND 1) Delay ime LS OFF 20% Case 2: Delay Time High Side Driver ON INx Previous Sae New Sae HS OFF HS ON LS OFF LS OFF ENy ENz VOUT_HSx [V] VS 80% GND donh 2) 20% 2) Delay ime HS ON wihou dead ime ; LS previously OFF Case 3: Delay Time High Side Driver ON wih DLH dead ime Previous Sae New Sae HS OFF HS ON INx ENy LS ON LS OFF VOUT_HSx [V] VS GND High-Side ON delay ime donh + DLH 3) 20% 80% 3) HS ON delay ime wih dead ime ; LS previously ON Figure 10 Half bridge oupus swiching imes- low-side o high-side ransiion Temperaure monioring and shudown Temperaure sensors are inegraed in he power sages. The emperaure monioring circui compares he measured emperaure o he shudown hreshold. Daashee

29 Half-Bridge Oupus If one or more emperaure sensors reach he shu-down emperaure hreshold, all oupus are lached off. All oupus remain deacivaed as long as EN1 = 1 or EN2 = 1. To resume normal funcionaliy of he power swich (in he even he overemperaure condiion disappears or o verify if he failure sill exiss) he microconroller shall: 1. clear he error flag by seing EN1 and EN2 o 0 (see Table 11) 2. se EN1 or EN2 o 1 in order o send he device from sleep mode back o normal mode T j T jsd V OUTx ON High Z V EF no error Overemperaure error Error Flag H L Figure 11 Overemperaure Behaviour Daashee

30 Half-Bridge Oupus VS Undervolage Behaviour If he supply volage decreases o he undervolage swich-off hreshold, V UV OFF, hen all oupu swiches are swiched off, and he error flag EF is se o High (error deecion). If V S rises again and reaches he undervolage swich-on hreshold, V UV ON, he power-sages are auomaically reacivaed according o ENx and INx. Refer o Figure 12 V S V UV HY V UV OFF V UV ON V OUTx EN1 = EN2 = 0 Sleep mode EN1=1 and/or EN2=1 Time ON OFF (High-Z) Error Flag VS undervolage SE T _DI Time V EF H Figure 12 L Undervolage behaviour Hi-Z Time EF acively se of Low Daashee

31 Half-Bridge Oupus VS Overvolage Behaviour If he supply volage increases beyond he overvolage swich hreshold, V OV OFF, hen all oupu swiches are swiched off and EF is se High, indicaing an overvolage condiion. If V S decreases again and reaches he overvolage swich-on hreshold, V OV ON, hen he power-sages are auomaically reacivaed according o ENx and INx. Refer o Figure 13. V S V OV OFF V OV HY VOV ON V OUTx EN1 = EN2 = 0 Sleep mode EN1=1 and/or EN2=1 Time ON OFF (High-Z) Error Flag VS overvolage SE T_ DI Time V EF H L Hi-Z Time EF acively se of Low Figure 13 Overvolage behaviour V DD Undervolage In he even he V DD logic supply decreases below he undervolage hreshold, V DD_POFFR, he TLE94003EP will ener rese. EF is se o high impedance during a V DD undervolage even. The digial block will be iniialized and he oupu sages are swiched off o High impedance. The undervolage rese is released once V DD volage levels are above he undervolage hreshold, V DD POR. Daashee

32 Applicaion Informaion 7 Applicaion Informaion Noe: The following simplified applicaion examples are given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. The funcion of he described circuis mus be verified in he real applicaion. 7.1 Applicaion Diagram Wachdog In Wachdog Ou Rese Ou Q CD 100nF CQ 22μF 6 D GND 3-5, VReg TLE4678 G Rese Adjus 13 2 RWA 100 kω Wachdog Adjus Inpu CI 100 nf VBAT DRP WDO WDI R VCC Series resisors are recommended if he VS of he TLE94003 EP is proeced by an acive reverse polariy proecion µc 100nF VDD EN1 EN2 EF IN1 IN2 VS TLE94003EP OUT1 OUT2 M1 M2 Landing pads for ceramic capaciors a OUTx GND IN3 GND OUT3 Figure 14 Applicaion example wih DC moors Daashee

33 Applicaion Informaion Wachdog In Wachdog Ou Rese Ou Q CD 100nF CQ 22μF 6 D GND 3-5, VReg TLE4678 G Rese Adjus 13 2 RWA 100 kω Wachdog Adjus Inpu CI 100 nf VBAT DRP WDO WDI R VCC Series resisors are recommended if he VS of he TLE94003 EP is proeced by an acive reverse polariy proecion µc 100nF VDD EN1 EN2 EF IN1 IN2 VS TLE94003EP OUT1 OUT2 M1 M2 Landing pads for ceramic capaciors a OUTx IN3 GND OUT3 GND VDD VS VDD EN1 EN2 EF IN1 IN2 VS TLE94003EP OUT1 OUT2 M1 M2 IN3 OUT3 GND Figure 15 Applicaion Example wih wo TLE94003EP Noes on he applicaion example 1. Series resisors beween he microconroller and he signal pins of he TLE94003EP are recommended if an acive reverse polariy proecion (MOSFET) is used o proec he VS pin. These resisors limi he curren beween he microconroller and he device during negaive ransiens on VBAT (e.g. ISO/TR 7637 pulse 1) Daashee

34 Applicaion Informaion 2. Landing pads for ceramic capaciors a he oupus of he TLE94003EP as close as possible o he connecors are recommended (he ceramic capaciors are no populaed if unused). These ceramic capaciors can be mouned if a higher performance in erm of ESD capabiliy is required. 3. The elecrolyic capacior a he VS pin should be dimensioned in order o preven he VS volage from exceeding he absolue maximum raing. PWM operaion wih a oo low capaciance can lead o a VS volage overshoo, which resuls in a VS overvolage deecion. 4. No used (NU) pins and unused oupus are recommended o be lef unconneced (open) in he applicaion. If NU pins or unused oupu pins are roued o an exernal connecor which leaves he PCB, hen hese oupus should have provision for a zero ohm jumper (depopulaed if unused) or ESD proecion. In oher words, NU and unused pins should be reaed like used pins. 5. Place bypass ceramic capaciors as close as possible o he VS pins, wih shores connecions he GND pins and GND layer, for bes EMC performance Daashee

35 Applicaion Informaion 7.2 Thermal applicaion informaion Ta = -40 C, Ch1 o Ch3 are dissipaing a oal of 0.6W (0.2W each). Ta = 85 C, Ch1 o Ch3 are dissipaing a oal of 0.405W (0.135W each). Zh-ja [K/W] s0p / 600mm² / -40 C 1s0p / 600mm² / +85C 1s0p / 300mm² / -40 C 1s0p / 300mm² / +85C 1s0p / fooprin / -40 C 1s0p / fooprin / +85 C 2s2p / -40 C 2s2p / +85 C Zh-ja for TLE94003EP ime [sec] Figure 16 ZhJA Curve for differen PCB seups 20 Zh-jc for TLE94003EP 15 Zh-jc [K/W] 10 Tamb = -40 C 5 Tamb = +85C ime [sec] Figure 17 ZhJC Curve Daashee

36 Package Oulines 8 Package Oulines Figure 18 PG-TSDSO-14 (Plasic Green - Dual Small Ouline Package) Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e lead-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp:// Dimensions in mm Daashee

37 Revision Hisory 9 Revision Hisory Revision Dae Changes 1.0 Iniial release Daashee

38 Trademarks All referenced produc or service names and rademarks are he propery of heir respecive owners. Ediion Published by Infineon Technologies AG Munich, Germany 2017 Infineon Technologies AG. All Righs Reserved. Do you have a quesion abou any aspec of his documen? erraum@infineon.com Documen reference Doc_Number IMPORTANT NOTICE The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics ("Beschaffenheisgaranie"). Wih respec o any examples, hins or any ypical values saed herein and/or any informaion regarding he applicaion of he produc, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion warranies of non-infringemen of inellecual propery righs of any hird pary. In addiion, any informaion given in his documen is subjec o cusomer's compliance wih is obligaions saed in his documen and any applicable legal requiremens, norms and sandards concerning cusomer's producs and any use of he produc of Infineon Technologies in cusomer's applicaions. The daa conained in his documen is exclusively inended for echnically rained saff. I is he responsibiliy of cusomer's echnical deparmens o evaluae he suiabiliy of he produc for he inended applicaion and he compleeness of he produc informaion given in his documen wih respec o such applicaion. For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( WARNINGS Due o echnical requiremens producs may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies office. Excep as oherwise explicily approved by Infineon Technologies in a wrien documen signed by auhorized represenaives of Infineon Technologies, Infineon Technologies producs may no be used in any applicaions where a failure of he produc or any consequences of he use hereof can reasonably be expeced o resul in personal injury.