BTS7200-2EPC. 1 Overview. Smart High-Side Power Switch. Package PG-TSDSO-14 Marking C

Transcription

1 Smar High-Side Power Swich 2x 200 mω Package PG-TSDSO-14 Marking C 1 Overview Poenial Applicaions Suiable for resisive, inducive and capaciive loads Replaces elecromechanical relays, fuses and discree circuis Driving capabiliy suiable for 1.2 A loads (including relays) and high inrush curren loads such as R5W lamps or LED equivalen Exreme Cranking capabiliy down o 2.7 V VBAT R/L cable T1 CVS DZ2 VDD VDD GPIO RIN IN0 VS T ROL GPIO RIN IN1 R/L cable GPIO RDEN DEN OUT0 COU T0 GPIO RDSEL DSEL Conrol RPD Microconroller Proecion T Diagnosis R/L cable A/D IN RAD RIS_PROT IS GND OUT1 CSENSE VSS DZ1 RSENSE RGND RPD COUT1 App_2CH_LI_INTDIO_Cover.emf Figure 1 Applicaion Diagram. Furher informaion in Chaper 10 Daa Shee Rev

2 Overview Basic Feaures High-Side Swich wih Diagnosis and Embedded Proecion Par of Family Swich ON capabiliy while Inverse Curren condiion (InverseON) Green Produc (RoHS complian) Qualified in accordance wih AEC Q100 grade 1 Proecion Feaures Absolue and dynamic emperaure limiaion wih conrolled resar Overcurren proecion (ripping) wih Inelligen Resar Conrol Undervolage shudown Overvolage proecion wih exernal componens Diagnosic Feaures Proporional load curren sense Open Load in ON and OFF sae Shor circui o ground and baery Descripion The is a Smar High-Side Power Swich, providing proecion funcions and diagnosis. The device is inegraed in SMART7 echnology. Table 1 Produc Summary Parameer Symbol Values Minimum Operaing volage (a swich ON) V S(OP) 4.1 V Minimum Operaing volage (cranking) V S(UV) 2.7 V Maximum Operaing volage V S 28 V Minimum Overvolage proecion (T J 25 C) V DS(CLAMP)_25 35 V Maximum curren in Sleep mode (T J 85 C) I VS(SLEEP)_ µa Maximum operaive curren I GND(ACTIVE) 4 ma Maximum ON-sae resisance (T J = 150 C) R DS(ON)_ mω Nominal load curren (T A = 85 C) I L(NOM) 1.2 A Typical curren sense raio a I L = I L(NOM) k ILIS 670 Daa Shee 2 Rev. 1.00

3 Block Diagram and Terms 2 Block Diagram and Terms 2.1 Block Diagram VS Supply Volage Monioring Overvolage Proecion Inernal Power Supply IS IN0 IN1 DEN Inelligen Resar Conrol SENSE Oupu ESD Proecion + Inpu Logic Channel 1 Channel 0 driver logic Driver Logic Volage Sensor Volage Overempera Sensor ure Overemperaure Gae Conrol + Gae Chargepump Conrol + Chargepump Overvolage Clamping Overvolage Clamping Overcurren Proecion Overcurren Proecion T T OUT1 DSEL Inernal Reverse Polariy Proecion InverseON Load Curren Sense Load Curren Sense Oupu Volage Limiaion OUT0 GND Circuiry Oupu Volage Limiaion Figure 2 GND Block Diagram of Block_PROFET2ch_IN VON_IN TDIO.emf Daa Shee 3 Rev. 1.00

4 Block Diagram and Terms 2.2 Terms Figure 3 shows all erms used in his daa shee, wih associaed convenion for posiive values. I VS I INn V SIS INn VS V DSn V S I DEN I DSEL DEN DSEL OUTn I Ln V INn V DEN V DSEL I IS IS GND V OUTn V IS I GND Terms_PROFET.emf Figure 3 Volage and Curren Convenion Daa Shee 4 Rev. 1.00

5 Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen GND IN0 DEN IS DSEL IN1 n.c VS expos ed pad (bo om) OUT0 OUT0 OUT0 n.c. OUT1 OUT1 OUT1 PinOu_PROFET2ch.emf Figure 4 Pin Configuraion Daa Shee 5 Rev. 1.00

6 Pin Configuraion 3.2 Pin Definiions and Funcions Table 2 Pin Definiion Pin Symbol Funcion EP VS (exposed pad) Supply Volage Baery volage 1 GND Ground Signal ground 2, 6 INn Inpu Channel n Digial signal o swich ON channel n ( high acive) If no used: connec wih a 10 kω resisor eiher o GND pin or o module ground 3 DEN Diagnosic Enable Digial signal o enable device diagnosis ( high acive) and o clear he proecion couner of channel seleced wih DSEL pin If no used: connec wih a 10 kω resisor eiher o GND pin or o module ground 4 IS SENSE curren oupu Analog/digial signal for diagnosis If no used: lef open 5 DSEL Diagnosis Selecion Digial signal o selec one channel o perform ON and OFF sae diagnosis ( high acive) If no used: connec wih a 10 kω resisor eiher o GND pin or o module ground 7, 11 n.c. No conneced, inernally no bonded 8-10, OUTn Oupu n Proeced high-side power oupu channel n All oupu pins of he channel mus be conneced ogeher on he PCB. All pins of he oupu are inernally conneced ogeher. PCB races have o be designed o wihsand he maximum curren which can flow. Daa Shee 6 Rev. 1.00

7 General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings - General Table 3 Absolue Maximum Raings T J = -40 C o +150 C; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Supply pins Power Supply Volage V S V P_ Load Dump Volage V BAT(LD) 35 V suppressed Load Dump acc. o ISO (2010). R i = 2 Ω P_ Supply Volage for Shor Circui Proecion V BAT(SC) 0 24 V Seup acc. o AEC-Q Reverse Polariy Volage -V BAT(REV) 16 V 2 min T A = +25 C Seup as described in Chaper 10 P_ P_ Curren hrough GND Pin I GND ma P_ Logic & conrol pins (Digial Inpu = DI) DI = INn, DEN, DSEL 2) Curren hrough DI Pin I DI -1 2 ma P_ Curren hrough DI Pin I DI(REV) ma 2) P_ Reverse Baery Condiion 2 min IS pin Volage a IS Pin V IS -1.5 V S V I IS = 10 μa P_ Curren hrough IS Pin I IS -25 I IS(SAT),M ma P_ Temperaures Juncion Temperaure T J C P_ Sorage Temperaure T STG C P_ ESD Suscepibiliy ESD Suscepibiliy all Pins (HBM) V ESD(HBM) -2 2 kv HBM 3) P_ AX Daa Shee 7 Rev. 1.00

8 General Produc Characerisics Table 3 Absolue Maximum Raings (coninued) T J = -40 C o +150 C; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion ESD Suscepibiliy OUTn vs GND V ESD(HBM)_OU -4 4 kv HBM 3) P_ and VS conneced (HBM) T ESD Suscepibiliy all Pins V ESD(CDM) V CDM 4) P_ (CDM) ESD Suscepibiliy Corner Pins (CDM) (pins 1, 7, 8, 14) V ESD(CDM)_CR N V CDM 4) P_ No subjec o producion es - specified by design. 2) Maximum V DI o be considered for Lach-Up ess: 5.5 V. 3) ESD suscepibiliy, Human Body Model HBM, according o AEC Q ) ESD suscepibiliy, Charged Device Model CDM, according o AEC Q Noes 1. Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. 2. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 4.2 Absolue Maximum Raings - Power Sages Number Power Sage mω Table 4 Absolue Maximum Raings T J = -40 C o +150 C; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Maximum Energy Dissipaion Single Pulse Maximum Energy Dissipaion Repeiive Pulse E AS 13.5 mj I L = 2*I L(NOM) T J(0) = 150 C V S = 28 V E AR 4 mj I L = I L(NOM) T J(0) = 85 C V S = 13.5 V 1M cycles Number P_ P_ Daa Shee 8 Rev. 1.00

9 General Produc Characerisics Table 4 Absolue Maximum Raings (coninued) T J = -40 C o +150 C; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Maximum Energy Dissipaion Repeiive Pulse - Relay E AR(RELAY) 10 mj I L = 220 ma T J(0) = 85 C V S = 13.5 V 2M cycles P_ A P_ Load Curren I L I L(OVL),M Number No subjec o producion es - specified by design. AX 4.3 Funcional Range Table 5 Funcional Range - Supply Volage and Temperaure Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Supply Volage Range for Normal Operaion V S(NOR) V P_ Lower Exended Supply Volage Range for Operaion Upper Exended Supply Volage Range for Operaion V S(EXT,LOW) V V S(EXT,UP) V 3) No subjec o producion es - specified by design. 2) In case of V S volage decreasing: V S(EXT,LOW),MIN =2.7V. In case of V S volage increasing: V S(EXT,LOW),MIN =4.1V. 3) Proecion funcions sill operaive. 2)3) (parameer deviaions possible) (parameer deviaions possible) P_ P_ Juncion Temperaure T J C P_ Noe: Wihin he funcional or operaing range, he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he Elecrical Characerisics ables. Daa Shee 9 Rev. 1.00

10 General Produc Characerisics 4.4 Thermal Resisance Noe: This hermal daa was generaed in accordance wih JEDEC JESD51 sandards. For more informaion, go o Table 6 Thermal Resisance Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Thermal Characerizaion Ψ JTOP K/W 2) Parameer Juncion-Top Thermal Resisance Juncion-o-Case Thermal Resisance Juncion-o-Ambien No subjec o producion es - specified by design. 2) According o Jedec JESD51-2,-5,-7 a naural convecion on FR4 2s2p board; he Produc (Chip + Package) was simulaed on a mm board wih 2 inner copper layers (2 70 µm Cu, 2 35 µm Cu). Where applicable a hermal via array under he exposed pad conaced he firs inner copper layer. Simulaion done a T A = 105 C, P DISSIPATION = 1 W PCB Seup R hjc K/W 2) simulaed a exposed pad Number P_ P_ R hja 34.6 K/W 2) P_ µm modeled (races, cooling area) 1,5 mm 70 µm, 5% mealizaion* *: means percenual Cu mealizaion on each layer PCB_Zh_1s0p.emf Figure 5 1s0p PCB Cross Secion 1,5 mm 70 µm modeled (races) 35 µm, 90% mealizaion* 35 µm, 90% mealizaion* 70 µm, 5% mealizaion* *: means percenual Cu mealizaion on each layer PCB_Zh_2s2p.emf Figure 6 2s2p PCB Cross Secion Daa Shee 10 Rev. 1.00

11 General Produc Characerisics PCB 1s0p mm² cooling PCB 2s2p / 1s0p fooprin PCB_sim _seup_tsdso14.emf Figure 7 PCB seup for hermal simulaions PCB_ 2s2p_vias_TSDSO14.emf Figure 8 Thermal vias on PCB for 2s2p PCB seup Thermal Impedance Daa Shee 11 Rev. 1.00

12 General Produc Characerisics BTS7200-2EPx Z hja (K/W) T A = 105 C Time (s) Figure 9 Typical Thermal Impedance. PCB seup according Chaper s2p 1s0p mm 1s0p mm 1s0p - fooprin 130 BTS7 00- EPx 120 1s0p - Ta = 105 C R hja (K/W) Figure Cooling area (mm2) Thermal Resisance on 1s0p PCB wih various cooling surfaces Daa Shee 12 Rev. 1.00

13 Logic Pins 5 Logic Pins The device has 4 digial pins for direc conrol. 5.1 Inpu Pins (INn) The inpu pins IN0, IN1 acivae he corresponding oupu channel. The inpu circuiry is compaible wih 3.3V and 5V microconroller. The elecrical equivalen of he inpu circuiry is shown in Figure 11. In case he pin is no used, i mus be conneced wih a 10 kω resisor eiher o GND pin or o module ground. VS IN I DI V S(CLAMP) ESD I DI V DI(CLAMP) V DI GND I GND RGND Inpu_IN_INTDIO.emf Figure 11 Inpu circuiry The logic hresholds for low and high saes are defined by parameers V DI(TH) and V DI(HYS). The relaionship beween hese wo values is shown in Figure 12. The volage V IN needed o ensure a high sae is always higher han he volage needed o ensure a low sae. V DI V DI(TH ),MAX V DI(TH) V DI(HYS) V DI(TH ),MIN Inernal channel acivaion signal 0 x 1 x 0 Inpu_VDITH_2.emf Figure 12 Inpu Threshold volages and hyseresis Daa Shee 13 Rev. 1.00

14 Logic Pins 5.2 Diagnosis Pin The Diagnosis Enable (DEN) pin conrols he diagnosis circuiry and he proecion circuiry. When DEN pin is se o high, he diagnosis is enabled (see Chaper 9.2 for more deails). When i is se o low, he diagnosis is disabled (IS pin is se o high impedance). The Diagnosis Selecion (DSEL) pin selecs he channel where diagnosis is performed (see Chaper The ransiion from high o low of DEN pin clears he proecion lach of he channel seleced wih DSEL pin depending on he logic sae of IN pin and DEN pulse lengh (see Chaper 8.3 for more deails). The inernal srucure of diagnosis pins is he same as he one of inpu pins. See Figure 11 for more deails. 5.3 Elecrical Characerisics Logic Pins V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Digial Inpu (DI) pins = IN, DEN, DSEL Table 7 Elecrical Characerisics: Logic Pins - General Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Digial Inpu Volage Threshold Digial Inpu Clamping Volage Digial Inpu Clamping Volage V DI(TH) V See Figure 11 and Figure 12 V DI(CLAMP 7 V I DI = 1 ma See Figure 11 and Figure 12 V DI(CLAMP2) V I DI = 2 ma See Figure 11 and Figure 12 Digial Inpu Hyseresis V DI(HYS) 0.25 V Digial Inpu Curren ( high ) Digial Inpu Curren ( low ) I DI(L) µa V DI = 0.8 V See Figure 11 and Figure 12 No subjec o producion es - specified by design. See Figure 11 and Figure 12 I DI(H) µa V DI = 2 V See Figure 11 and Figure 12 Number P_ P_ P_ P_ P_ P_ Daa Shee 14 Rev. 1.00

15 Power Supply 6 Power Supply The is supplied by V S, which is used for he inernal logic as well as supply for he power oupu sages. V S has an undervolage deecion circui, which prevens he acivaion of he power oupu sages and diagnosis in case he applied volage is below he undervolage hreshold. 6.1 Operaion Modes has he following operaion modes: Sleep mode Acive mode Sand-by mode The ransiion beween operaion modes is deermined according o hese variables: Logic level a INn pins Logic level a DEN pin The sae diagram including he possible ransiions is shown in Figure 13. The behavior of as well as some parameers may change in dependence from he operaion mode of he device. Furhermore, due o he undervolage deecion circuiry which moniors V S supply volage, some changes wihin he same operaion mode can be seen accordingly. There are hree parameers describing each operaion mode of : Saus of he oupu channels Saus of he diagnosis Curren consumpion a VS pin (measured by I VS in Sleep mode, I GND in all oher operaive modes) Table 8 shows he correlaion beween operaion modes, V S supply volage, and he sae of he mos imporan funcions (channel saus, diagnosis). Unsupplied Power-up IN = high IN = low & DEN = low Sleep V S > V S(OP) IN = low & DEN = low IN = low & DEN = high DEN = high Acive IN = high IN = low & DEN = high Sand-by DEN = low PowerSupply_OpMode_PROFET.emf Figure 13 Operaion Mode Sae Diagram Daa Shee 15 Rev. 1.00

16 Power Supply Table 8 Device funcion in relaion o operaion modes and V S volage Operaive Mode Funcion V S in undervolage V S no in undervolage Sleep Channels OFF OFF Diagnosis OFF OFF Acive Channels OFF available Diagnosis OFF available in OFF and ON saes Sand-by Channels OFF OFF Diagnosis OFF available in OFF sae Unsupplied In his sae, he device is eiher unsupplied (no volage applied o VS pin) or he supply volage is below he undervolage hreshold Power-up The Power-up condiion is enered when he supply volage (V S ) is applied o he device. The supply is rising unil i is above he undervolage hreshold V S(OP) herefore he inernal Power-On signals are se Sleep mode The device is in Sleep mode when all Digial Inpu pins (INn, DEN, DSEL) are se o low. When is in Sleep mode, all oupus are OFF. The curren consumpion is minimum (see parameer I VS(SLEEP) ). No Overemperaure or Overload proecion mechanism is acive when he device is in Sleep mode. The device can go in Sleep mode only if he proecion is no acive (couner = 0, see Chaper for furher deails) Sand-by mode The device is in Sand-by mode as long as DEN pin is se o high while inpu pins are se o low. All channels are OFF herefore only Open Load in OFF diagnosis is possible. Depending on he load condiion, eiher a faul curren I IS(FAULT) or an Open Load in OFF curren I IS(OLOFF) may be presen a IS pin. In such siuaion, he curren consumpion of he device is increased Acive mode Acive mode is he normal operaion mode of. The device eners Acive mode as soon as one IN pin is se o high. Device curren consumpion is specified wih I GND(ACTIVE) (measured a GND pin because he curren a VS pin includes he load curren). Overload, Overemperaure and Overvolage proecions are acive. Diagnosis is available. 6.2 Undervolage on V S Beween V S(OP) and V S(UV) he undervolage mechanism is riggered. If he device is operaive (in Acive mode) and he supply volage drops below he undervolage hreshold V S(UV), he inernal logic swiches OFF he oupu channels. As soon as he supply volage V S is above he operaive hreshold V S(OP), he channels having he corresponding inpu pin se o high are swiched ON again. The resar is delayed wih a ime DELAY(UV) which proecs he device in case he undervolage condiion is caused by a shor circui even (according o AEC-Q ), as shown in Figure 14. Daa Shee 16 Rev. 1.00

17 Power Supply If he device is in Sleep mode and one inpu is se o high, he corresponding channel is swiched ON if V S > V S(OP) wihou waiing for DELAY(UV). V S V S(OP) V S(UV) V S(HYS) Channel acivaion signal V OUT DELAY(UV) PowerSupply_UVRVS.emf Figure 14 V S undervolage behavior Daa Shee 17 Rev. 1.00

18 Power Supply 6.3 Elecrical Characerisics Power Supply V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Typical resisive loads conneced o he oupus for esing (unless oherwise specified): R L = 7.8 Ω Table 9 Elecrical Characerisics: Power Supply - General Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion VS pin Power Supply Undervolage Shudown Power Supply Minimum Operaing Volage Power Supply Undervolage Shudown Hyseresis Power Supply Undervolage Recovery Time Breakdown Volage beween GND and VS Pins in Reverse Baery No subjec o producion es - specified by design. V S(UV) V V S decreasing IN = high From V DS 0.5 V o V DS = V S See Figure 14 V S(OP) V V S increasing IN = high From V DS = V S o V DS 0.5 V See Figure 14 V S(HYS) 0.7 V V S(OP) - V S(UV) See Figure 14 DELAY(UV) ms dv S /d 0.5 V/µs V S -1 V See Figure 14 -V S(REV) V I GND(REV) = 7 ma T J = 150 C Number P_ P_ P_ P_ P_ Daa Shee 18 Rev. 1.00

19 Power Supply 6.4 Elecrical Characerisics Power Supply - Produc Specific V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Typical resisive loads conneced o he oupus for esing (unless oherwise specified): R L = 7.8 Ω Table 10 Elecrical Characerisics: Power Supply Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Power Supply Curren Consumpion in Sleep Mode wih Loads a T J 85 C Power Supply Curren Consumpion in Sleep Mode wih Loads a T J = 150 C Operaing Curren in Acive Mode (all Channels ON) Operaing Curren in Sandby Mode No subjec o producion es - specified by design. I VS(SLEEP)_ µa V S = 18 V V OUT = 0 V IN = DEN = low T J 85 C I VS(SLEEP)_ µa V S = 18 V V OUT = 0 V IN = DEN = low T J = 150 C I GND(ACTIVE) 2 4 ma V S = 18 V IN = DEN = high I GND(STBY) ma V S = 18 V IN = low DEN = high Number P_ P_ P_ P_ Daa Shee 19 Rev. 1.00

20 Power Sages 7 Power Sages The high-side power sages are buil using a N-channel verical Power MOSFET wih charge pump. 7.1 Oupu ON-Sae Resisance The ON-sae resisance R DS(ON) depends mainly on juncion emperaure T J. Figure 15 shows he variaion of R DS(ON) across he whole T J range. The value 2 on he y-axis corresponds o he maximum R DS(ON) measured a T J = 150 C R DS(ON) variaion over T J 2.00 Reference value: "2" = R 150 C R DS(ON) variaion facor Typical Juncion Temperaure ( C) Figure 15 R DS(ON) variaion facor The behavior in Reverse Polariy is described in Chaper Swiching loads Swiching Resisive Loads When swiching resisive loads, he swiching imes and slew raes shown in Figure 16 can be considered. The swich energy values E ON and E OFF are proporional o load resisance and imes ON and OFF. Daa Shee 20 Rev. 1.00

21 Power Sages V IN(TH) IN V OUT V IN(HYS) 90% of V S ON OFF(DELAY) 70% of V S 70% of V S (dv/d) ON -(dv/d) OFF 30% of V S 30% of V S 10% of V S ON(DELAY) OFF P DMOS E ON E OFF Power S age_swichres.emf Figure 16 Swiching a Resisive Load Swiching Inducive Loads When swiching OFF inducive loads wih high-side swiches, he volage V OUT drops below ground poenial, because he inducance inends o coninue driving he curren. To preven he desrucion of he device due o overvolage, a volage clamp mechanism is implemened. The clamping srucure limis he negaive oupu volage so ha V DS = V DS(CLAMP). Figure 17 shows a concep drawing of he implemenaion. The clamping srucure proecs he device in all operaion modes lised in Chaper 6.1. V S High-side Channel VS V DS V SIS(CLAMP) V DS(CLAMP) IS I L V S(CLAMP) OUTn V OU Tn RSENSE GND I L L, R L RGND PowerSage_Clamp_INTDIO.emf Figure 17 Oupu Clamp concep Daa Shee 21 Rev. 1.00

22 Power Sages During demagneizaion of inducive loads, energy has o be dissipaed in. The energy can be calculaed wih Equaion (7.: E = V S V DS( CLAMP) 1 R L I L ( ) ln I L V DS CLAMP R L V S V DS( CLAMP) L R L (7. The maximum energy, herefore he maximum inducance for a given curren, is limied by he hermal design of he componen Oupu Volage Limiaion To increase he curren sense accuracy, V DS volage is moniored. When he oupu curren I L decreases while he channel is diagnosed (DEN pin se o high, channel seleced wih DSEL pins - see Figure 18) bringing V DS equal or lower han V DS(SLC), he oupu DMOS gae is parially discharged. This increases he oupu resisance so ha V DS = V DS(SLC) even for very small oupu currens. The V DS increase allows he curren sensing circuiry o work more efficienly, providing beer k ILIS accuracy for oupu curren in he low range. IN DEN I L sis(on) sis(off) V DS V S V DS(SLC) PowerSage_GBR_diag.emf Figure 18 Oupu Volage Limiaion acivaion during diagnosis 7.3 Advanced Swiching Characerisics Inverse Curren behavior When V OUT > V S, a curren I INV flows ino he power oupu ransisor (see Figure 19). This condiion is known as Inverse Curren. If he channel is in OFF sae, he curren flows hrough he inrinsic body diode generaing high power losses herefore an increase of overall device emperaure. This may lead o a swich OFF of unaffeced channels due o Overemperaure. If he channel is in ON sae, R DS(INV) can be expeced and power dissipaion in he oupu sage is comparable o normal operaion in R DS(ON). During Inverse Curren condiion, he channel remains in ON or OFF sae as long as I INV < I L(INV). If one channel has inverse curren applied, he neighbor channel is no influenced, meaning ha swiching ON and OFF imings, proecion (Overcurren, Overemperaure) and curren sensing (k ILIS ) are sill wihin specified limis. Daa Shee 22 Rev. 1.00

23 Power Sages Wih InverseON, i is possible o swich ON he channel during Inverse Curren condiion as long as I INV < I L(INV) (see Figure 20). V BAT V S Gae Driver Device Logic INV Comp. OUT I INV V INV = V OU T > V S GND RGND PowerSage_InvCurr_INTDIO.emf Figure 19 Inverse Curren Circuiry IN CASE 1 : Swich is ON IN CASE 2 : Swich is OFF I L ON I L OFF NORMAL INVERSE NORMAL NORMAL INVERSE NORMAL DMOS sae DMOS sae ON OFF CASE 3 : Swich ON ino Inverse Curren CASE 4 : Swich OFF ino Inverse Curren IN IN I L OFF ON I L ON OFF NORMAL INVERSE NORMAL NORMAL INVERSE NORMAL DMOS sae DMOS sae OFF ON ON OFF PowerSage_InvCurr_INVON.emf Figure 20 InverseON - Channel behavior in case of applied Inverse Curren Daa Shee 23 Rev. 1.00

24 Power Sages Noe: No proecion mechanism like Overemperaure or Overload proecion is acive during applied Inverse Currens Swiching Channels in Parallel In case of appearance of a shor circui wih conneced in parallel o drive a single load, i may happen ha he wo channels swich OFF asynchronously, herefore bringing an addiional hermal sress o he channel ha swiches OFF las. For his reason i is no recommended o use he device wih channels in parallel Cross Curren robusness wih H-Bridge configuraion When is used as high-side swich e.g. in a bridge configuraion (herefore paired wih a low-side swich as shown in Figure 2, he maximum slew rae applied o he oupu by he low-side swich mus be lower han dv OUT / d. V BAT R/L cable VS T T ON (DC) IN0 IN1 OFF OUT0 OUT1 dv OUT / d Curren hrough Moor M Cross Curren OFF ON (PWM) PowerSage_PassiveSl ew_profet.emf Figure 21 High-Side swich used in Bridge configuraion Daa Shee 24 Rev. 1.00

25 Power Sages 7.4 Elecrical Characerisics Power Sages V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Typical resisive loads conneced o he oupus for esing (unless oherwise specified): R L = 7.8 Ω Table 11 Elecrical Characerisics: Power Sages - General Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Volages Drain o Source Clamping Volage a T J = -40 C Drain o Source Clamping Volage a T J 25 C Tesed a T J = 150 C. V DS(CLAMP)_ V I L = 5 ma T J = -40 C See Figure 17 V DS(CLAMP)_ V I L = 5 ma T J 25 C See Figure 17 Number P_ P_ Elecrical Characerisics Power Sages - PROFET Table 12 Elecrical Characerisics: Power Sages - PROFET Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Timings Swich-ON Delay ON(DELAY) μs V S = 13.5 V V OUT = 10% V S See Figure 16 Swich-OFF Delay OFF(DELAY) μs V S = 13.5 V V OUT = 90% V S See Figure 16 Swich-ON Time ON μs V S = 13.5 V V OUT = 90% V S See Figure 16 Number P_ P_ P_ Swich-OFF Time OFF μs V S = 13.5 V P_ V OUT = 10% V S See Figure 16 Swich-ON/OFF Maching ON - OFF Δ SW μs V S = 13.5 V P_ Daa Shee 25 Rev. 1.00

26 Power Sages Table 12 Elecrical Characerisics: Power Sages - PROFET (coninued) Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Volage Slope Swich-ON Slew Rae (dv/d) ON V/μs V S = 13.5 V V OUT = 30% o 70% of V S See Figure 16 Swich-OFF Slew Rae -(dv/d) OFF V/μs V S = 13.5 V V OUT = 70% o 30% of V S See Figure Elecrical Characerisics - Power Oupu Sages V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Typical resisive loads conneced o he oupus for esing (unless oherwise specified): R L = 7.8 Ω P_ P_ Slew Rae Maching Δ(dV/d) SW V/μs V S = 13.5 V P_ (dv/d) ON - (dv/d) OFF Volages Oupu Volage Drop Limiaion a Small Load Currens No subjec o producion es - specified by design. V DS(SLC) mv DEN = high channel seleced wih DSEL pin I L = I L(OL) = 20 ma See Figure 18 Number P_ Power Oupu Sage mω Table 13 Elecrical Characerisics: Power Sages mω Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Oupu characerisics ON-Sae Resisance a R DS(ON)_ mω T J =25 C T J = 25 C ON-Sae Resisance a T J = 150 C ON-Sae Resisance in Cranking R DS(ON)_ mω T J = 150 C I L = 1 A R DS(ON)_CRAN 150 mω T J = 150 C K V S = 3.1 V I L = 0.4 A Number P_ P_ P_ Daa Shee 26 Rev. 1.00

27 Power Sages Table 13 Elecrical Characerisics: Power Sages mω (coninued) Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion ON-Sae Resisance in Inverse Curren a T J = 25 C ON-Sae Resisance in Inverse Curren a T J = 150 C Nominal Load Curren per Channel (all Channels Acive) Oupu Leakage Curren a T J 85 C Oupu Leakage Curren a T J = 150 C R DS(INV)_ mω T J = 25 C V S = 13.5 V I L = -1 A R DS(INV)_ mω T J = 150 C V S = 13.5 V I L = -1 A I L(NOM) 1.2 A I L(OFF)_ μa T A = 85 C T J 150 C V OUT = 0 V V IN = low T A 85 C I L(OFF)_ μa V OUT = 0 V V IN = low T A = 150 C Inverse Curren Capabiliy I L(INV) 1.2 A V S < V OUT IN = high Volage Slope Passive Slew Rae (e.g. for Half Bridge Configuraion) dv OUT / d 10 V/μs V S = 13.5 V Volages Drain Source Diode Volage V DS(DIODE) mv I L = -190 ma T J = 150 C Swiching Energy Swich-ON Energy E ON 0.17 mj V S = 18 V See Figure 16 Swich-OFF Energy E OFF 0.19 mj No subjec o producion es - specified by design V S = 18 V See Figure 16 Number P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ Daa Shee 27 Rev. 1.00

28 Proecion 8 Proecion The is proeced agains Overemperaure, Overload, Reverse Baery and Overvolage. Overemperaure and Overload proecions are working when he device is no in Sleep mode. Overvolage proecion works in all operaion modes. Reverse Baery proecion works when he GND and VS pins are reverse supplied. 8.1 Overemperaure Proecion The device incorporaes boh an absolue (T J(ABS) ) and a dynamic (T J(DYN) ) emperaure proecion circuiry for each channel. An increase of juncion emperaure T J above eiher one of he wo hresholds (T J(ABS) or T J(DYN) ) swiches OFF he overheaed channel o preven desrucion. The channel remains swiched OFF unil juncion emperaure has reached he Resar condiion described in Table 14. The behavior is shown in Figure 22 (absolue Overemperaure Proecion) and Figure 23 (dynamic Overemperaure Proecion). T J(REF) is he reference emperaure used for dynamic emperaure proecion. IN DEN I L I L(OVL) T J T J(ABS) THYS(ABS) I IS I IS(SAT) I IS(FAUL T) IS(FAUL T)_D I L / k ILIS In er nal coun er 0 1 Proecion_PROFET_OT_IRC.emf Figure 22 Overemperaure Proecion (Absolue) Daa Shee 28 Rev. 1.00

29 Proecion IN DEN I L I L(OVL) T J T J(ABS) TJ(DYN) T J(REF) I IS IS(FAUL T)_D I IS(FAUL T) I L / k ILIS In er nal coun er Proecion_PROFET_dT_IRC.emf Figure 23 Overemperaure Proecion (Dynamic) When he Overemperaure proecion circuiry allows he channel o be swiched ON again, he rery sraegy described in Chaper 8.3 is followed. 8.2 Overload Proecion The is proeced in case of Overload or shor circui o ground. Two Overload hresholds are defined (see Figure 24) and seleced auomaically depending on he volage V DS across he power DMOS: I L(OVL0) when V DS < 13 V I L(OVL when V DS > 22 V Daa Shee 29 Rev. 1.00

30 Proecion Overload hreshold variaion ("1" = I L(OVL) V DS = 5 V) I L(OVL0) I L(OVL Drain Source Volage (V) Figure 24 Overload Curren Thresholds variaion wih V DS In order o allow a higher load inrush a low ambien emperaure, Overload hreshold is maximum a low emperaure and decreases when T J increases (see Figure 25). I L(OVL0) ypical value remains consan up o a juncion emperaure of +75 C. Daa Shee 30 Rev. 1.00

31 Proecion 1.3 I L(OVL0) variaion over T J I L(OVL0) variaion facor reference value "1" = I L(OVL0) -40 C Typ Juncion Temperaure ( C) Figure 25 Overload Curren Thresholds variaion wih T J Power supply volage V S can increase above 18 V for shor ime, for insance in Load Dump or in Jump Sar condiion. Whenever V S V S(JS), he overload deecion curren is se o I L(OVL_JS) as shown in Figure 26. I L(OVL ) I L(OVL_ JS) V S(JS) V S Proecion_JS.emf Figure 26 Overload Deecion Curren variaion wih V S volage When I L I L(OVL) (eiher I L(OVL0) or I L(OVL ), he channel is swiched OFF. The channel is allowed o resar according o he rery sraegy described in Chaper 8.3. Daa Shee 31 Rev. 1.00

32 Proecion 8.3 Proecion and Diagnosis in case of Faul Any even ha riggers a proecion mechanism (eiher Overemperaure or Overload) has 2 consequences: The affeced channel swiches OFF and he inernal couner is incremened If he diagnosis is acive for he affeced channel, a curren I IS(FAULT) is provided by IS pin (see Chaper for furher deails) The channel can be swiched ON again if all he proecion mechanisms fulfill he resar condiions described in Table 14. Furhermore, he device has an inernal rery couner (one for each channel) o maximize he robusness in case of faul. Table 14 Proecion Resar Condiion Faul condiion Swich OFF even Resar Condiion Overemperaure T J T J(ABS) or (T J - T J(REF) ) T J(DYN) T J < T J(ABS) and (T J - T J(REF) ) < T J(DYN) (including hyseresis) Overload I L I L(OVL) I L < 50 ma T J wihin T J(ABS) and T J(DYN) ranges (including hyseresis) Rery Sraegy When IN is se o high, he channel is swiched ON. In case of faul condiion he oupu sage is swiched OFF. The channel can be allowed o resar only if he resar condiions for he proecion mechanisms are fulfilled (see Table 14). The channel is allowed o swich ON for n RETRY(CR) imes before swiching OFF. Afer a ime RETRY, if he inpu pin is se o high, he channel swiches ON again for n RETRY(NT) imes before swiching OFF again ( rery cycle). Afer n RETRY(CYC) consecuive rery cycles, he channel laches OFF. I is necessary o se he inpu pin o low for a ime longer han DELAY(CR) o de-lach he channel ( couner rese delay ime) and o rese he inernal couner o he defaul value. During he couner rese delay ime, if he inpu is se o high he channel remains swiched OFF and he imer couning DELAY(CR) is rese, saring o coun again as soon as he inpu pin is se o low again. If he inpu pin remains low for a ime longer han DELAY(CR) he inernal rery couner is rese o he defaul value, allowing n RETRY(CR) reries a he nex channel acivaion. The rery sraegy is shown in Figure 29 (flowchar), Figure 27 (iming diagram - inpu pin always high ) and Figure 28 (iming diagram - channel conrolled in PWM). Daa Shee 32 Rev. 1.00

33 Proecion IN Shor circu i o ground n RETRY(CYC) "rery" cycle n RETRY(CR) n RETRY(NT) n RETRY(NT) I L RETRY RETRY DELAY(CR) In er nal coun er 0 1 n RETRY(CR) n RETRY(CR) + n RETRY(NT) n RETRY(CR) + (n RETRY(CYC) * n RETRY(NT)) 0 DEN I IS(FAUL T) I IS I L / k ILIS I L / k ILIS Proecion_PROFET_ime_noPWM.emf Figure 27 Rery Sraegy Timing Diagram IN Shor circu i o ground nretry(cyc) "rery" cycle nretry(cr) nretry(nt) nretry(nt) IL RETRY RETRY DELAY(CR) In er nal coun er 0 1 nretry(cr) nretry(cr) + nretry(nt) nretry(cr) + (nretry(cyc) * nretry(nt)) 0 Proecion_PROFET_Timings.emf Figure 28 Rery Sraegy Timing Diagram - Channel operaed in PWM Daa Shee 33 Rev. 1.00

34 Proecion START Channel remains OFF IN is "high" no yes "Rery" cycles = nretry(cyc) yes no ALL "Resar" condiions fulfilled no Swich channel OFF no yes Swich channel ON IN is "high" yes Channel remains ON no Faul (Overemperaure or Overload) yes Swich channel OFF Couner++ "Rery" cycles++ yes Couner < nretry(cr) Wai for RETRY no "Rery" cycles = no nretry(cyc) yes Wai unil IN is "low" hen sar couning for DELAY(CR) IN is "low" no yes Coninue couning for DELAY(CR) no DELAY(CR) elapsed yes Couner = 0 "Rery" cycles = 0 Proecion_PRO FET _Flow.emf Figure 29 Rery Sraegy Flowchar Daa Shee 34 Rev. 1.00

35 Proecion I is possible o force a rese of he inernal couner wihou waiing for DELAY(CR) by applying a pulse (rising edge followed by a falling edge) o he DEN pin while IN pin is low. The pulse applied o DEN pin mus have a duraion longer han DEN(CR) o ensure a rese of he inernal couner. The DSEL pin mus selec he channel ha has o be de-lached and keep he same logic value while DEN pin oggles wice (rising edge followed by a falling edge). The imings are shown in Figure 30. IN Shor circu i o ground I L n RETRY(CR) n RETRY(CR) In er nal coun er 0 1 n RETRY(CR) 0 1 n RETRY(CR) 0 DEN DEN(CR) DEN(CR) DEN(CR) Proecion_PROFET_DENforce_ime2.emf Figure 30 Rery Sraegy Timing Diagram wih Forced Rese 8.4 Addiional proecions Reverse Polariy Proecion In Reverse Polariy condiion (also known as Reverse Baery), power dissipaion is caused by he inrinsic body diode of he DMOS channel. Each ESD diode of he logic conribues o oal power dissipaion. The reverse curren hrough he oupu sages mus be limied by he conneced loads. The curren hrough digial inpu pins has o be limied as well by an exernal resisor (please refer o he Absolue Maximum Raings lised in Chaper 4.1 and o Applicaion Informaion in Chaper 10) Overvolage Proecion In he case of supply volages beween V S(EXT,UP) and V BAT(LD), he oupu ransisors are sill operaional and follow he inpu pin. In addiion o he oupu clamp for inducive loads as described in Chaper 7.2.2, here is a clamp mechanism available for Overvolage proecion for he logic and he oupu channels, monioring he volage beween VS and GND pins (V S(CLAMP) ). Daa Shee 35 Rev. 1.00

36 Proecion 8.5 Proecion agains loss of connecion Loss of Baery and Loss of Load The loss of connecion o baery or o he load has no influence on device robusness when load and wire harness are purely resisive. In case of driving an inducive load, he energy sored in he inducance mus be handled. devices can handle he induciviy of he wire harness up o 10 µh wih I L(NOM). In case of applicaions where currens and/or he aforemenioned induciviy are exceeded, an exernal suppressor diode (like diode D Z2 shown in Chaper 10) is recommended o handle he energy and o provide a welldefined pah o he load curren Loss of Ground In case of loss of device ground, i is recommended o have a resisor conneced beween any Digial Inpu pin and he microconroller o ensure a channel swich OFF (as described in Chaper 10). Noe: In case any Digial Inpu pin is pulled o ground (eiher by a resisor or acive) a parasiic ground pah is available, which could keep he device operaional during loss of device ground. Daa Shee 36 Rev. 1.00

37 Proecion 8.6 Elecrical Characerisics Proecion V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Typical resisive loads conneced o he oupus for esing (unless oherwise specified): R L = 7.8 Ω Table 15 Elecrical Characerisics: Proecion - General Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Thermal Shudown T J(ABS) C 2) Temperaure (Absolue) See Figure 22 Thermal Shudown T HYS(ABS) 30 K 3) Hyseresis (Absolue) See Figure 22 Thermal Shudown T J(DYN) 80 K 3) Temperaure (Dynamic) See Figure 23 Power Supply Clamping Volage a T J = -40 C Power Supply Clamping Volage a T J 25 C Power Supply Volage Threshold for Overcurren Threshold Reducion in case of Shor Circui Funcional es only. 2) Tesed a T J = 150 C only. 3) No subjec o producion es - specified by design. V S(CLAMP)_ V I VS = 5 ma T J = -40 C See Figure 17 V S(CLAMP)_ V 2) V S(JS) V I VS = 5 ma T J 25 C See Figure 17 3) Seup acc. o AEC- Q Number P_ P_ P_ P_ P_ P_ Daa Shee 37 Rev. 1.00

38 Proecion Elecrical Characerisics Proecion - PROFET Table 16 Elecrical Characerisics: Proecion - PROFET Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Auomaic Reries in Case of Faul afer a Couner Rese Auomaic Reries in Case of Faul afer he Firs RETRY Acivaion Maximum Rery Cycles allowed before Channel Lach OFF Auo Rery Time afer Faul Condiion Couner Rese Delay Time afer Faul Condiion n RETRY(CR) 5 n RETRY(NT) 1 n RETRY(CYC) 2 RETRY ms DELAY(CR) ms See Figure 27 and Figure 28 See Figure 27 and Figure 28 See Figure 27 and Figure 28 Minimum DEN Pulse DEN(CR) µs 2) Duraion for Couner Rese See Figure 30 Funcional es only. 2) No subjec o producion es - specified by design. See Figure 27 and Figure 28 See Figure 27 and Figure 28 Number P_ P_ P_ P_ P_ P_ Daa Shee 38 Rev. 1.00

39 Proecion 8.7 Elecrical Characerisics Proecion - Power Oupu Sages V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Typical resisive loads conneced o he oupus for esing (unless oherwise specified): R L = 7.8 Ω Proecion Power Oupu Sage mω Table 17 Elecrical Characerisics: Proecion mω Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Overload Deecion Curren a T J = -40 C Overload Deecion Curren a T J = 25 C Overload Deecion Curren a T J = 150 C Funcional es only. 2) No subjec o producion es - specified by design. I L(OVL0)_ A I L(OVL0)_ A 2) I L(OVL0)_ A T J = -40 C di/d = 0.05 A/µs see Figure 24 T J = 25 C di/d = 0.05 A/µs see Figure 24 2) T J = 150 C di/d = 0.05 A/µs see Figure 24 Overload Deecion Curren I L(OVL 4 A 2) a High V DS di/d = 0.05 A/µs see Figure 24 Overload Deecion Curren Jump Sar Condiion I L(OVL_JS) 4 A 2) V S > V S(JS) di/d = 0.05 A/µs Number P_ P_ P_ P_ P_ Daa Shee 39 Rev. 1.00

40 Diagnosis 9 Diagnosis For diagnosis purpose, he provides a combinaion of digial and analog signals a pin IS. These signals are generically named SENSE and wrien I IS. In case of disabled diagnosic (DEN pin se o low ), IS pin becomes high impedance. A sense resisor R SENSE mus be conneced beween IS pin and module ground if he curren sense diagnosis is used. R SENSE value has o be higher han 820 Ω (or 400 Ω when a cenral Reverse Baery proecion is presen on he baery feed) o limi he power losses in he sense circuiry. A ypical value is R SENSE = 1.2 kω. Due o he inernal connecion beween IS pin and V S supply volage, i is no recommended o connec he IS pin o he sense curren oupu of oher devices, if hey are supplied by a differen baery feed. See Figure 31 for deails as an overview. VS Channel 1 Channel 0 T Overemperaure Inernal Couners INn DEN DSEL IS Pin Conrol Logic I L / k ILIS OUT1 OUT0 I IS(FAULT) + V DS(OLOFF) MUX MUX I IS(OLOFF) MUX IS R SENSE Diagnosis_PROFET_2CH.emf Figure 31 Diagnosis Block Diagram 9.1 Overview Table 18 gives a quick reference o he sae of he IS pin during operaion. Daa Shee 40 Rev. 1.00

41 Diagnosis Table 18 SENSE Signal, Funcion of Applicaion Condiion Applicaion Condiion Inpu level DEN level V OUT Diagnosic Oupu Normal operaion low high ~ GND Z I IS(FAULT) if couner > 0 Shor circui o GND ~ GND Z I IS(FAULT) if couner > 0 Overemperaure Z I IS(FAULT) Shor circui o V S V S I IS(OLOFF) (I IS(FAULT) if couner > 0) Open Load Wih addiional pull-up resisor. 2) The oupu curren has o be smaller han I L(OL). 3) The oupu curren has o be higher han I L(OL). < V S - V DS(OLOFF) > V S - V DS(OLOFF) Z I IS(OLOFF) (in boh cases I IS(FAULT) if couner > 0) Inverse curren ~ V INV = V OUT > V S I IS(OLOFF) (I IS(FAULT) if couner > 0) Normal operaion high ~ V S I IS = I L / k ILIS Overcurren < V S I IS(FAULT) Shor circui o GND ~ GND I IS(FAULT) Overemperaure Z I IS(FAULT) Shor circui o V S V S I IS < I L / k ILIS Open Load 2) ~ V S I IS = I IS(EN) Under load (e.g. Oupu Volage 3) ~ V S I IS(EN) < I IS < I L(NOM) / k ILIS Limiaion condiion) Inverse curren ~ V INV = V OUT > V S I IS = I IS(EN) All condiions n.a. low n.a. Z SENSE signal ruh able In case DEN is se o high, he SENSE for he seleced channel is enabled or disabled using DSEL pin. Table 19 gives he ruh able. Table 19 Diagnosic Truh Table DEN DSEL IS low no relevan Z high low SENSE oupu 0 high high SENSE oupu Diagnosis in ON sae A curren proporional o he load curren (raio k ILIS = I L / I IS ) is provided a pin IS when he following condiions are fulfilled: Daa Shee 41 Rev. 1.00

42 Diagnosis The power oupu sage is swiched ON wih V DS < 2 V The diagnosis is enabled for ha channel No faul (as described in Chaper 8.3) is presen or was presen and no cleared ye (see Chaper for furher deails) If a hard failure mode is presen or was presen and no cleared ye a curren I IS(FAULT) is provided a IS pin Curren Sense (k ILIS ) The accuracy of he sense curren depends on emperaure and load curren. I IS increases linearly wih I L oupu curren unil i reaches he sauraion curren I IS(SAT). In case of Open Load a he oupu sage (I L close o 0 A), he maximum sense curren I IS(EN) (no load, diagnosis enabled) is specified. This condiion is shown in Figure 33. The blue line represens he ideal k ILIS line, while he red lines show he behavior of a ypical produc. An exernal RC filer beween IS pin and microconroller ADC inpu pin is recommended o reduce signal ripple and oscillaions (a minimum ime consan of 1 µs for he RC filer is recommended). The k ILIS facor is specified wih limis ha ake ino accoun effecs due o emperaure, supply volage and manufacuring process. Tigher limis are possible (wihin a defined curren window) wih calibraion: A well-defined and precise curren (I L(CAL) ) is applied a he oupu during End of Line es a cusomer side The corresponding curren a IS pin is measured and he k ILIS is calculaed (k I L(CAL) ) Wihin he curren range going from I L(CAL)_L o I L(CAL)_H he k ILIS is equal o k I L(CAL) wih limis defined by Δk ILIS The deraing of k ILIS afer calibraion is calculaed using he formulas in Figure 32 and i is specified by Δk ILIS Diagnosis_dKILIS.emf Figure 32 Δk ILIS calculaion formulas The calibraion is inended o be performed a T A(CAL) = 25 C. The parameer Δk ILIS includes he drif overemperaure as well as he drif over he curren range from I L(CAL)_L o I L(CAL)_H. I IS I IS(OL) I IS(EN) I L(OL) I L Diagnosis_ OLON _adv.emf Figure 33 Curren Sense Raio in Open Load a ON condiion Daa Shee 42 Rev. 1.00

43 Diagnosis Faul Curren (I IS(FAULT) ) As soon a proecion even occurs, changing he value of he inernal rery couner (see Chaper 8.3 for more deails) from is rese sae, a curren I IS(FAULT) is provided by pin IS when DEN is se o high and he affeced channel is seleced. The following 3 siuaions may occur: If he channel is ON and he number of reries is lower han n RETRY(CR) + n RETRY(CYC) * n RETRY(NT), he curren I IS(FAULT) is provided for a ime IS(FAULT)_D afer he channel is allowed o resar, afer which I IS = I L / k ILIS (as shown in Figure 34). During a rery cycle (while imer RETRY is running) he curren I IS(FAULT) is provided each ime he channel diagnosis is checked If he channel is ON and he number of reries is equal han n RETRY(CR) + n RETRY(CYC) * n RETRY(NT), he curren I IS(FAULT) is provided unil he inernal couner is rese (eiher by expiring of DELAY(CR) ime or by DEN pin pulse, as described in Chaper 8.3. If he channel is OFF and he inernal couner is no in he rese sae, he curren I IS(FAULT) is provided each ime he channel diagnosis is checked IN I L I L(OVL) In er nal coun er DEN IS(FAUL T)_D I IS(FAUL T) I IS I IS(FAUL T) I L / k ILIS Diagnosis_PROFET_IISFAULT_load.emf Figure 34 I IS(FAULT) a Load Swiching Figure 35 adds he behavior of SENSE signal o he iming diagram seen in Figure 28, while Figure 36 shows he relaion beween I IS = I L / k ILIS, I IS(SAT) and I IS(FAULT). Daa Shee 43 Rev. 1.00

44 Diagnosis IN Shor circu i o ground n RETRY(CYC) "rery" cycle n RETRY(CR) n RETRY(NT) n RETRY(NT) I L RETRY RETRY DELAY(CR) In er nal coun er 0 1 n RETRY(CR) n RETRY(CR) + n RETRY(NT) n RETRY(CR) + (n RETRY(CYC) * n RETRY(NT)) 0 DEN I IS(FAUL T) I IS(FAUL T) I IS(FAUL T) IL / kilis I IS Diagnosis_PROFET_IISFAULT.emf Figure 35 SENSE behavior in Faul condiion I IS I IS(SA T),max I IS(SAT) I IS(FAUL T),max I IS(FAUL T) I IS(SA T),min = I IS(FAUL T),min I L / k ILIS I L(OVL) I L Diagnosis_PROFET_IISFAULT_IISSAT.emf Figure 36 SENSE behavior - overview 9.3 Diagnosis in OFF sae When a power oupu sage is in OFF sae, he can measure he oupu volage and compare i wih a hreshold volage. In his way, using some addiional exernal componens (a pull-down resisor and a swichable pull-up curren source), i is possible o deec if he load is missing or if here is a shor circui o baery. If a Faul condiion was deeced by he device (he inernal couner has a value differen from he rese value, as described in Chaper 9.2.2) a curren I IS(FAULT) is provided by IS pin each ime he channel diagnosis is checked also in OFF sae. Daa Shee 44 Rev. 1.00

45 Diagnosis Open Load curren (I IS(OLOFF) ) In OFF sae, when DEN pin is se o high and a channel is seleced using DSEL pin, he V DS volage is compared wih a hreshold volage V DS(OLOFF). If he load is properly conneced and here is no shor circui o baery, V DS ~ V S herefore V DS > V DS(OLOFF). When he diagnosis is acive and V DS V DS(OLOFF), a curren I IS(OLOFF) is provided by IS pin. Figure 37 shows he relaionship beween I IS(OLOFF) and I IS(FAULT) as funcions of V DS. The wo currens do no overlap making always possible o differeniae beween Open Load in OFF and Faul condiion. I IS I IS(FAULT) I IS(OLOFF) V DS(OLOFF) V DS Diagnosis_PROFET_IISOL OFF.emf Figure 37 I IS in OFF Sae I is necessary o wai a ime IS(OLOFF)_D beween he falling edge of he inpu pin and he sensing a pin IS for Open Load in OFF diagnosis o allow he inernal comparaor o sele. In Figure 38 he imings for an Open Load deecion are shown - he load is always disconneced. IN DEN V OUT ~ V S IS(OLOFF)_D V DS(OLOFF) Load conn eced I IS I IS(OLOFF) I IS(OL) Diagnosis_PROFET_OLOFF_ime.emf Figure 38 Open Load in OFF Timings - load disconneced Daa Shee 45 Rev. 1.00

46 Diagnosis 9.4 SENSE Timings Figure 39 and Figure 41 show he iming during seling sis(on) and disabling sis(off) of he SENSE (including he case of load change). As a proper signal canno be esablished before he load curren is sable (herefore before ON ), sis(diag) = sis(on) + ON. IN OFF ON OFF DEN OFF I L I IS sis(lc) sis(o FF) sis(on) sis(o FF) sis(di AG) Diagnose_PROFET_SENSE_imings.emf Figure 39 SENSE Seling / Disabling Timing IN OFF ON OFF DEN I L sis(on)_slc sis(on) sis(lc)_slc I IS Diagnose_PROFET_SENSE_imings_SLC.emf Figure 40 SENSE Timing wih Small Load Curren Daa Shee 46 Rev. 1.00

47 Diagnosis DEN DSEL I L0 I L(CAL) I L1 I L(CAL)_L I L(CAL)_O L si S(CC) sis(o FF) sis(on) si S(CC)_SLC I IS Figure 41 SENSE Seling Timing - Channel Change Diagnose_PROFET_SENSE_imings_CC.emf Daa Shee 47 Rev. 1.00

48 Diagnosis 9.5 Elecrical Characerisics Diagnosis V S = 6 V o 18 V, T J = -40 C o +150 C Typical values: V S = 13.5 V, T J = 25 C Typical resisive loads conneced o he oupus for esing (unless oherwise specified): R L = 7.8 Ω Table 20 Elecrical Characerisics: Diagnosis - General Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion SENSE Sauraion Curren I IS(SAT) ma V S = 8 V o 18 V R SENSE = 1.2 kω See Figure 36 SENSE Sauraion Curren I IS(SAT) ma SENSE Leakage Curren when Disabled SENSE Leakage Curren when Enabled a T J 85 C SENSE Leakage Curren when Enabled a T J = 150 C SENSE Operaive Range for k ILIS Operaion (V S - V IS ) SENSE Operaive Range for Open Load a OFF Diagnosis (V S - V IS ) SENSE Operaive Range for Faul Diagnosis (V S - V IS ) V S = 6 V o 18 V R SENSE = 1.2 kω See Figure 36 I IS(OFF) µa DEN = low I L I L(NOM) V IS = 0 V I IS(EN)_ µa T J 85 C DEN = high I L = 0 A See Figure 33 I IS(EN)_ µa T J = 150 C DEN = high I L = 0 A See Figure 33 V SIS_k V V SIS_OL V V SIS_F V V S = 6 V IN = DEN = high I L 1.2 * I L(NOM) V S = 6 V IN = low DEN = high V S = 6 V IN = low DEN = high couner > 0-40 C < T J 150 C Number P_ P_ P_ P_ P_ P_ P_ P_ Daa Shee 48 Rev. 1.00