Conduction in Semiconductors Review


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1 Conduction in Semiconductors Review Intrinsic (undoped) Semiconductors intrinsic carrier concentration n i =.45x0 0 cm 3, at room temp. n = p = n i, in intrinsic (undoped) material n number of electrons, p number of holes massaction law, np = n i =(.45E0), applies to undoped and doped material Extrinsic (doped) Semiconductors dopants added to modify material/electrical properties Chap. 3 ntype onor P group V element P ion B B free carrier electron ptype cceptor group III element ion free carrier hole ntype (n), add elements with an extra electron N d conc. of donor atoms [cm 3 ] n n = N d, n n conc. of electrons in ntype material p n = n i /N d, using massaction law, p n conc. of holes in ntype material always a lot more n than p in ntype material ptype = p, add elements with an extra hole N a concentration of acceptor atoms [cm 3 ] p p = N a, p p conc. of holes in ptype material n p = ni /N a, using massaction law, n p conc. of electrons in ptype material always a lot more p than n in ptype material Lecture Notes 6.
2 Conduction in Semiconductors doping provides free charge carriers, alters conductivity conductivity,σ, in semic. w/ carrier densities n and p σ = q(µ n n µ p p), q electron charge, q =.6x0 9 [Coulombs] µ mobility [cm /Vsec], µ n 360, µ p 480 (typical values) in ntype region, n n >> p n σ qµ n n n in ptype region, p p >> n p σ qµ p n p resistivity, ρ = /σ resistance of an n or p region R = ρ l, = wt mobility = average velocity per unit electric field µ n > µ p electrons more mobile than holes conductivity of n > p drift current (flow of charge carriers in presence of an electric field, E x ) n/p drift current density: Jxn = σ n E x = qµ n n n E x, Jxp = σ p E x = qµ p p p E x total drift current density in x direction Jx = q(µ n n µ p p) E x = σ E x w l t Lecture Notes 6.
3 What is a pn Junction? interface of ptype and ntype semiconductor pn Junctions: Intro junction of two materials forms a diode In the Beginning ionization of dopants at material interface iffusion movement of charge to regions of lower concentration free carriers diffuse out leave behind immobile ions region become depleted of free carriers ions establish an electric field acts against diffusion ptype N acceptors/cm ptype 3 hole diffusion hole current electron diffusion electron current ptype depletion region 3 N acceptors/cm depletion region boundaries pn diode junction immobile acceptor ions (negativecharge) x p electric field W contact to pside ptype Si wafer ntype x n ntype N donors/cm 3 donor ion and electron free carrier acceptor ion and hole free carrier E contact to nside p n n well ntype 3 N donors/cm immobile donor ions (positivecharge) dielectric insulator (oxide) Lecture Notes 6.3
4 pn Junctions: Equilibrium Conditions epletion Region area at pn interface void of free charges charge neutrality must have equal charge on both sides q x p N = q x n N, =junction area; x p, x n depth into p/n side x p N = x n N depletion region will extend further into the more lightly doped side of the junction Builtin Potential ptype depletion region 3 N acceptors/cm immobile acceptor ions (negativecharge) diffusion of carriers leaves behind immobile charged ions ions create an electric field which generates a builtin potential N 0 = VT ln N Ψ ni N where V T = kt/q = 6mV at room temperature x p electric field W x n E N ntype 3 N donors/cm immobile donor ions (positivecharge) Lecture Notes 6.4
5 pn Junctions: epletion Width epletion Width use Poisson s equation & charge neutrality W = x p x n x p = ε ( Ψ ) 0 VR N ε( Ψ0 VR) N xn = ( N N ) qn ( N N ) qn W where V R is applied reverse bias = Onesided Step Junction if N >>N (pn diode) most of junction on nside ( Ψ V ) N N ε 0 R q N N W x n ptype depletion region N 3 N acceptors/cm immobile acceptor ions (negativecharge) ε is the permittivity of Si ε =.04x0 F/cm x p electric field W x n E N ntype 3 N donors/cm immobile donor ions (positivecharge) N N 0 = VT ln ni Ψ ε = K S ε 0, where ε 0 = 8.85x0 4 F/cm and K S =.8 is the relative permittivity of silicon = ( Ψ V ) ε 0 qn R if N >>N (np diode) most of junction on pside W x p = ( Ψ V ) ε 0 qn R Lecture Notes 6.5
6 Lecture Notes 6.6 pn Junctions epletion Capacitance Free carriers are separated by the depletion layer Separation of charge creates junction capacitance Cj = ε/d (d = depletion width, W) is complex to calculate in semiconductor diodes consists of both bottom of the well and sidewall areas Cj is a strong function of biasing must be recalculated if bias conditions change CMOS doping is not linear/constant graded junction approximation Junction Breakdown if reverse bias is too high (typically > 30V) can get strong reverse current flow ( ) Ψ = R j V N N N N q C 0 ε ε is the permittivity of Si ε =.8ε 0 =.04x0 F/cm V R = applied reverse bias Ψ = 0 R jo j V C C ( ) 0 Ψ = jo N N N N q C ε Ψ = 3 0 R jo j V C C
7 V p n iode Biasing and Current Flow V I V f V I I Forward Bias; V > Ψ 0 acts against builtin potential I depletion width reduced diffusion currents increase with V minority carrier diffusion ( V V ) e T = I S Reverse Bias; V R = V > 0 acts to support builtin potential depletion width increased electric field increased small drift current flows considered leakage I S N small until V R is too high and breakdown occurs N Lecture Notes 6.7
8 MOSFET Capacitor MOSFETs move charge from drain to source underneath the gate, if a conductive channel exists under the gate Understanding how and why the conductive channel is produced is important MOSFET capacitor models the gate/oxide/substrate region source and drain are ignored substrate changes with applied gate voltage Consider an nmos device ccumulation, V G < 0, ()ve charge on gate induces ()ve charge in substrate ()ve charge accumulate from substrate p Weak Inversion epletion, V G > 0 but small creates depletion region in subst. () charge but no free carriers Inversion, V G > 0 but larger further depletion requires high energy () charge pulled from Ground e free carriers in channel S G gate gate oxide channel = Si substrate = bulk V < 0 V > 0 G G ptype Si substrate B depletion layer ptype Si substrate G B V >> 0 G depletion layer ptype Si substrate B B B ccumulation epletion Inversion Lecture Notes 6.8
9 Capacitance in MOSFET Capacitor In ccumulation Gate capacitance = Oxide capacitance Cox = ε ox /t ox [F/cm ] In epletion Gate capacitance has components ) oxide capacitance ) depletion capacitance of the substrate depletion region Cdep = ε si /x d, x d = depth of depletion region into substrate Cgate = Cox Cdep = Cox Cdep / (CoxCdep) < Cox Cox Cdep In Inversion free carries at the surface Cgate = Cox Cox Cgate accumulation depletion inversion V G Lecture Notes 6.9
10 Inversion Operation MOSFET off unless in inversion look more deeply at inversion operation efine some stuff Qs = total charge in substrate V G = applied gate voltage Vox = voltage drop across oxide φ s = potential at silicon/oxide interface (relative to substrateground) Qs = Cox V G V G = Vox φ s uring Inversion (for nmos) V G > 0 applied to gate Vox drops across oxide (assume linear) φ s drops across the silicon substrate, most near the surface Lecture Notes 6.0
11 Surface Charge Q B = bulk charge, ion charge in depletion region under the gate recall from pn junction, Q B = q N x d, x d = depletion depth when N Q B = (q ε Si N φ s ) / >>N ε Ψ0 V W xn = = f(v G ) qn charge per unit area Qe = charge due to free electrons at substrate surface Qs = Q B Qe < 0 (negative charge for nmos) ( ) R depletion region Q B, bulk charge electron layer, Qe Lecture Notes 6.
12 Surface Charge vs. Gate Voltage Surface Charge vs. Gate Voltage V G < Vtn, substrate charge is all bulk charge, Qs = Q B V G = Vtn, depletion region stops growing x d at max., further increase of V G will NOT increase x d Q B at max. V G > Vtn, substrate charge has both components, Qs = Q B Qe since Q B is maxed, further increases in V G must increase Qe increasing Qe give more free carriers thus less resistance Threshold Voltage Vtn defined as gate voltage where Qe starts to form Qe = Cox (V G Vtn) Vtn is gate voltage required to overcome material difference between silicon and oxide establish depletion region in channel to max value/size Lecture Notes 6.
13 Gate current Overview of MOSFET Current gate is essentially a capacitor no current through gate gate is a control node V G < Vtn, device is off V G > Vtn, device is on and performance is a function of V GS and V S rain Current (current from drain to source), I Source = source/supply of electrons (nmos) or holes (pmos) rain = drain/sink of electrons (nmos) or holes (pmos) V S establishes an Efield across the channel (horizontally) free charge in an Efield will create a drainsource current is I drift or diffusion current? MOSFET IV Characteristics V S = V GS Vtn nmos V GS ground Charge Flow Current Flow ()ve potential Electron Flow Current Flow Lecture Notes 6.3
14 Cutoff Region V GS < Vtn nmos Current vs.voltage I = 0 (Not quietthere is leakage subthreshold current ) Linear Region V GS > Vth, V S > 0 but very small Qe = Cox (V GS Vtn) I = µ n Qe (W/L) V S I = µ n Cox (W/L) (V GS Vtn) V S Triode Region V GS > Vth, 0 < V S < V GS Vth surface potential, φ s, at drain now f(v GS V S =V G ) less charge near drain assume channel charge varies linearly from drain to source I at source: Qe = Cox (V GS Vtn), at drain: Qe = 0 nc = µ OX W L [ ] ( V V ) V V GS t S S General Integral for expressing I channel charge = f(y) channel voltage = f(y) y is direction from drain to source I = α V 0 Q I V S = V GS Vtn ( y) δv ( y) V GS Lecture Notes 6.4
15 nmos Current vs.voltage Saturation Region (ctive Region) V GS > Vtn, V S > V GS Vtn surface potential at drain, φ sd = V GS VtnV S when V S = V GS Vtn, φ sd = 0 channel not inverted at the drain channel is said to be pinched off square law equation during pinch off, further increase in V S will not increase I define saturation voltage, Vsat, when V S = V GS Vtn current is saturated, no longer increases substitute Vsat=V GS Vtn for V S into triode equation I nc = µ OX W L ( V GS V t ) I nc = µ OX W L [ ( V V ) V V ] GS t S S Lecture Notes 6.5
16 Transconductance Other Stuff process transconductance, k = µ n Cox constant for a given fabrication process device transconductance, β n = k W/L Surface Mobility mobility at the surface is lower than mobility deep inside silicon for current, I, calculation, typical µ n = cm /Vsec Effective Channel Length effective channel length reduced by lateral diffusion under the gate depletion spreading from drainsubstrate junction Leff = L( drawn) L X d X d = εs ( V ( V V )) qn G t S L (drawn) x d G Leff ~x d L Lecture Notes 6.6
17 Second Order Effects Channel Length Modulation Square Law Equation predicts I is constant with V S However, I actually increases slightly with V S due to effective channel getting shorter as V S increases effect called channel length modulation Channel Length Modulation factor, λ models change in channel length with V S Corrected I equation I µ ncox W = ( VGS Vt ) λ L ( ( V V )) Veff = V GS Vtn Body Effect so far we have assumed that substrate and source are grounded if source not at ground, sourcetobulk voltage exists, V SB > 0 V SB > 0 will increase the threshold voltage, Vtn = f(v SB ) called Body Effect, or BodyBias Effect S eff Lecture Notes 6.7
18 pmos Equations analysis of nmos applies to pmos with following modifications physical change all ntype regions to ptype change all ptype regions to ntype substrate is ntype (pwell) channel charge is positive (holes) and ()ve charged ions equations change V GS to V SG (V SG typically = V V G ) change V S to V S (V S typically = V V ) change Vtn to Vtp pmos threshold is negative, nearly same magnitude as nmos other factors lower surface mobility, typical value, µ p = 0 cm /Vsec body effect, change V SB to V BS Lecture Notes 6.8
19 MOSFET RC Model Modeling MOSFET resistance and capacitance is very important for transient characteristics of the device RC Model rainsource (channel) Resistance, Rn Rn = V S / I function of bias voltages point (a), linear region Rn = /[β n (V GS Vtn)] point (b), triode region Rn = /{β n [(V GS Vtn)V S ]} point (c), saturation region Rn = V S / [β n (V GS Vtn) ] general model equation Rn = /[β n (V Vtn)] Lecture Notes 6.9
20 MOSFET Capacitances Preview Need to find C S and C MOSFET Small Signal model Model Capacitances Cgs Cgd Cgb Cdb Csb no Csd! v g Gate C gs C gd vgs C gb r o g m v gs g v i s v s mb Source sb C sb rain Body (Bulk) i d C db v d MOSFET Physical Capacitances layer overlap pn junction Lecture Notes 6.0
21 MOSFET conductances Preview# How do you determine g m and r o? v g Gate C gs C gd vgs r o g m v gs g v i s v s mb sb rain i d C db v d Source C sb This is a smallsignal MOSFETmodel or C model. I.e., it is a linearized version of the Ids equations about an operating C point. One has ncox W In the triode region: I ( V V ) V V, or In the statuation region (assumed): C gb [ ] Then (where * means the C operating point) g m IS : = Vgs IS r = / g = / o o Vds * Body (Bulk) = µ GS t S S L C W * I n = µ OX L ( V GS V t ) Lecture Notes 6.
22 Why do we care? RC Model Capacitances capacitances determine switching speed Important Notes models developed for saturation (active) region models presented are simplified (not detailed) RC Model Capacitances Source Capacitance models capacitance at the Source node C S = C GS C SB rain Capacitance models capacitance at the rain node C = C G C B What are C GS, C G, C SB, and C B? Lecture Notes 6.
23 MOSFET Parasitic Capacitances Gate Capacitance models capacitance due to overlap of Gate and Channel C G = Cox W L estimate that C G is split 50/50 between Source and rain C GS = ½ C G C G = ½ C G assume GateBulk capacitance is negligible models overlap of gate with substrate outside the active tx area C GB = 0 Bulk Capacitance C SB (SourceBulk) and C B (rainbulk) C j pn junction capacitances = C V qεn R N C = Ψ jo 0 Ψ0 What are V R, Ψ 0, N, and N? jo ( N N ) N N Lecture Notes 6.3
24 MOSFET Junction Capacitances Capacitance/area for pn Junction C j = C jo V Ψ m j = grading coefficient (typically /3) R 0 S/ Junction Capacitance zerobias capacitance m j C jo qεn Ψ = highest value when V R = 0, assume this for worstcase estimate 0 N 0 = VT ln assuming N (n S/) >> N (p subst.) N Ψ ni C j = C jo C S/j = C jo S/, S/ = area of Source/rain what is S/? complex 3dimensional geometry bottom region and sidewall regions C S/j = Cbot Csw bottom and side wall capacitances Lecture Notes 6.4
25 Bottom Capacitance Junction Capacitance C bot = Cj bot bot = X W Sidewall Capacitance x j C sw = C jsw P sw C jsw = Cj x j [F/cm] x j = junction depth P sw = sidewall perimeter P sw = (W X) ccounting for Gate Undercut junction actually under gate also due to lateral diffusion X X L (replace X with X L ) Total Junction Cap C S/j = C bot C sw = C j bot C jsw P sw = C S/j Lecture Notes 6.5
26 MOSFET Bulk Capacitances General Junction Capacitance C S/j = Cbot Csw C SB (SourceBulk) C SB = C j Sbot C jsw P Ssw C B (rainbulk) C B = C j bot C jsw P sw RC Model Capacitances Source Capacitance C S = C GS C SB rain Capacitance C = C G C B v g Gate C gs C gd vgs C gb r o g m v gs g v i s v s mb Source sb C sb rain Body (Bulk) i d C db v d Lecture Notes 6.6
27 Junction reas:examples Note: calculations assume following design rules poly size, L = λ poly space to contact, λ contact size, λ active overlap of contact, λ W = 4λ X = 5λ, X= λ, X3 = 6λ Nonshared Junction with Contact rea: X W = (5)(4) = 0λ Perimeter: (X W) = 8λ Shared Junction without Contact rea: X W = ()(4)λ = 8λ Perimeter: (X W) = λ much smaller! Shared Junction with Contact rea: X3 W = (6)(4)λ = 4λ Perimeter: (X3 W) = 0λ largest area! X X X3 Lecture Notes 6.7
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