Exam 2-Solutions ECE 410

Transcription

1 NME: Exam -Solutions ECE 40 uring this exam you are allowed to use a calculator and the equations sheet provided. You are not allowed to speak to or exchange books, papers, calculators, etc. with other students. Total Points: 00 Time: 60 minutes (:30pm :30pm rite your name at the top of the exam and your initials at the top of each sheet. Note the point value of each question and try to at least attempt each problem. Partial credit will be given for all problems involving calculations. Show all of your work. Try to use only the pages provided (write on back if necessary Give units in your answers. Sign the honor pledge at the bottom of this page. Unsigned exams will not be graded. True or False: For each of the following statements, circle T if it is true and F if it is false. pts. each. T F. To set the switching threshold (midpoint voltage, Vm, to V/ in a CMOS inverter, the pmos transistor must be wider than the nmos. T F. The most significant parameter in CMOS power consumption is the supply voltage, V. T F 3. ncreasing power supply voltage, V, will decrease the speed performance of CMOS gates. T F 4. The best way to improve the speed performance of a CMOS circuit is to decrease the channel width. T F 5. For adding large words (e.g., 3-bit, a ripple carry adder will be much faster than a carry lookahead adder. T F 6. The -flip flop provides synchronous data storage and is used to create registers, counters and other useful digital functions. T F 7. For the best speed performance in a 6T SRM cell, the access transistor must have a larger width (. T F 8. FET-programmable ROM uses a contact layer mask to set data values in the memory array. T F 9. n the field of semiconductors, MEMS stands for Micro Environmental Motor Sensors. T F 0. The added cost and complexity of BiCMOS process is only justified if large output currents are needed. Honor Pledge By signing below, pledge that have neither given nor received aid on this exam, nor have witnessed any other student giving or receiving aid.

2 ECE 40, Exam Multiple Choice: n the box beside each question, write the letter for the ONE answer that best fits the question/statement. 3 pts. each. B C B. hich of the following is a factor in CMOS total power consumption? average switching frequency B threshold voltage C transistor resistance number of substrate contacts. hich of the following circuits should have the slowest average rise time? NV B NOR C NN NN3 4. dding buffers to a CMOS circuit will do which of the following? reduce power consumption B minimize chip size C improve signal rise/fall times add a large capacitive load 3. hich of the following functions are not commonly included in an LU? addition B count up/down C increment logic N 6. hich of the following is an advantage of BiCMOS over static CMOS? power consumption B cost per chip C functions per chip area switching speed 5. hich type of memory is non-volatile with bit data that can be re-written? EPROM B SRM C ROM none of the above 7. CMOS Logic Functions: 7 points raw the CMOS schematic for the function: F = xy + z X Y Z Vout Z X Y

3 ECE 40, Exam Calculation: Solve the following problems in the space provided and on the backs of these pages if necessary. You must show LL major steps on these test pages. Unless otherwise noted, for all problems assume minimum feature size = λ = 0.6μm, and V = 3V. 8. CMOS C Timing Characteristics: 8 points nswer the following questions based on the circuit shown to the right. a f Vx = 0V, what logic function is implemented? NSER: NV. b hat is V OL if Vx = 0V? V OL = Vtp NSER: V OL = 0.5 V c s V OH = V if Vx=0V? Briefly explain your answer. NSER: YES / NO EXPLN: Vin Vx V=3V Vtp =0.5V M, β M, β Vout M is always on and will pull the output low when M is on VOH always less than V. d f Vx = 0V, write an expression for the gate switching threshold, Vm i hat is the region of operation of M? ii hat is the region of operation of M? REGON: Saturation. REGON: Saturation since VSG=VS. iii rite an expression that could be solved to find Vm (do not evaluate the expression, just write it. Your expression should be ONLY in terms of Vm, V, Vtp, β, and β. Note, β = μ Cox /L β Vm V β = β ( Vm V = ( VSG Vtp = ( VSG Vtp β ( V tp tp e How can this circuit be modified to maximize the output voltage swing (i.e., get V OH close to V and V OL close to ground? Explain briefly i in terms of size parameter (, L for transistors M and/or M? V OL = Vtp, can not be changed V OH can be raised by decreasing the /L ratio of M or increasing /L of M ii re there any other circuit parameters that can be modified to improve output voltage swing? ncreasing Vx (> 0V will make current in M weaker and allow V OH to go higher. 3

4 ECE 40, Exam 9. CMOS Transient Timing Characteristics: 8 points This problem refers to the schematic of a digital circuit shown to the right. lthough a pmos load has been used to simplify the circuit, you can assume that the nmos network functions like a typical static CMOS gate. a rite an expression for the output capacitance in terms of parasitics components Cgs, Cgd, Csb, and Cdb and output load capacitance C L. Specify the transistor for each component using the notation Cgs, CsbB, etc. M C MP MC V=3V Vtn= Vtp =0.5V MB M Vout B x EXPRESSON: C out = C L +Cgd+CgdB+CgdP+Cdb+CdbB+CdbP b n the table below, identify the logic value combination(s for inputs, B, C, and that would produce the worst case fall time. ssume all transistors are the same size. B C worst case fall time 0 0 worst case fall time (if more than one 0 0 c n the table below, identify the logic value combination(s for inputs, B, C, and that would produce the best case fall time. ssume all transistors are the same size. B C best case fall time best case fall time (if more than one d f all transistors are the same size with Rn=500Ω, what is the fall time (t f =.τn if Cout=50fF and Cx=0fF for the transition BC=000 to BC=0? τ n = Cout(Rn+Rn/+Cx(Rn/ = 50(.5(500+0(500/ = 40,000x0-5 t f =.(40x0- = 88 psec t f = 88 [psec] e rite a simplified expression for the falling-time time constant, τ n, in terms of Cout, Cx, and Rn for the transition BC=000 to BC=0 if R =4Rn, R B =3Rn and R C =R =Rn. τ n = Cout(4Rn (3Rn+Rn+Cx(Rn = CoutRn + CxRn EXPRESSON: τ n = CoutRn + CxRn 4

5 ECE 40, Exam 0. CMOS rithmetic and Logic Gates: 9 points a Complete the truth table for a /4 activelow decoder. c Complete the truth table for a -bit binary full-adder with inputs x, y and Cin. S S0 d3 d d d b 4-bit shift/rotate register has outputs F3-F0. hat are the outputs in terms of inputs 3-0 after performing the SHFT_RGHT function two times? x y Cin Sum Cout F3 F F F CMOS Memory: 0 points CMOS memory cell uses one nmos access transistor and a storage capacitor to save data. a hat type of memory is this? NSER: RM b f the nmos access transistor has Vtn=0.6V and μ n = 500cm /V, what is the maximum voltage that can be stored with V=3V? V max =.4 [V] c x0-3 coulombs of charge are stored on this cell at a max storage voltage =.5V. f the minimum cell readout voltage is 0.5V, what is the maximum allowable leakage current for a hold time of μsec? Cs=Qmax/Vmax = 0-3 /.5 = 4x0-4 =40fF L = Cs(dV/t h = 40f (.5-.5 / μ = 80n L (max = 80 [n] d f the minimum voltage after charge leakage on the cells is V, what is the final bit line voltage if Cs = 30fF and Cbit = 0.7pF? Vf = Vmin(Cs/(Cs+Cbit = (30f/(30+70f = 0.V V f = 0. [V] 5

6 ECE 40, Exam Equations Sheet V = R n p = n i R = L/σ Q = C V = Q / t σ = q(μ n n + μ p p Jx = σ Ex Cox = ε ox /t ox Q c = -C G (V G -V tn β n = μ n Cox (/L V ( V e N N 0 = V T ln ni T = S, Ψ C j = R n = / β n [(V-Vtn] ( Ψ + V N N ε 0 R + = q N N ε Ψ + V qε N N ( ( 0 R x p = N + N Ψ0 + VR qn C SB = C j Sbot + C jsw P Ssw C B = C j bot + C jsw P sw t f =. τ n, t r =. τ p t p = 0.35(τ n + τ p C GS = ½ C G C G = ½ C G, x RM: t h = (Cs / L (ΔVsf refresh = / t h region nmos equations pmos equations Cutoff = 0 = 0 Triode Saturation (ctive k' n ( Ψ V ε 0 + = qn ncox = μ pcox [ ( VGS Vtn VS VS ] = μ [ ( V V V V ] SG tp L L ncox = μ pcox ( VGS Vtn = μ ( VSG Vtp L L = μ β = μc OX L p C OX S R S Constants kt = 0.06 ev, at room temperature k = 8.6x0-5 ev/k, Boltzman s constant V T = 0.06 V, thermal voltage q=.6x0-9 C (coulombs n i =.45x0 0 cm -3, Si at room temperature ε 0 = 8.85x0-4 F/cm ε OX = ( x0-4 F/cm ε si = ( x0-4 F/cm Quadratic Equation: ax + bx + c = 0 b± b 4ac x = a emorgan s Rules (a * b = a + b (a + b = a * b Useful Logic Properties + x = 0 + x = x * x = x 0 * x = 0 x + x = x * x = 0 a * a = a a + a = a ab + ac = a (b+c properties which can be proven (a+b(a+c = a+bc a + a'b = a + b a + ab +ac = a 6