Student Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS


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1 Name: CARLETON UNIVERSITY SELECTE FINAL EXAMINATION QUESTIONS URATION: 6 HOURS epartment Name & Course Number: ELEC 3908 Course Instructors: S. P. McGarry Authorized Memoranda: Nonprogrammable calculators NO BOOKS OR NOTES Students MUST count the number of pages in this examination question paper before beginning to write, and report any discrepancy immediately to a proctor. This question paper has twenty (0) pages. This examination question paper may not be taken from the examination room. ANSWER ALL QUESTIONS ALL ANSWERS MUST BE WRITTEN ON THE EXAM PAPER (If necessary, continue answers on the back of pages) SEE EN OF EXAM FOR FORMULA & ATA SHEETS WRITE YOUR NAME AN STUENT NUMBER ON EACH PAGE
2 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 1. Consider a structure fabricated in silicon with the crosssection shown below. A B C p + p + n + n + n p n S S a) The starting substrate has a doping of n s = x10 14 cm 3, the implant to form the pregion is N A = 8x10 14 cm 3, for the nregion it is N = 5x10 15 cm 3, the n + region is N + =10 18 cm 3 and the p + region is N A + =5x10 17 cm 3. Calculate the carrier densities p, n, p + and n +. b) Assuming all the PN junctions act as isolated diodes and ignoring parasitic resistances, draw the equivalent circuit for this structure in terms of the contacts A, B, C, and the substrate S. (i.e. draw how the diodes are connected to each other and A, B, C, and S.) c) Would it be possible to use this structure as a bipolar junction transistor (BJT)? If so, what type of transistor and which contacts would you choose to be the collector, base and emitter and why?
3 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 3. Consider a structure fabricated in silicon with the crosssection shown below. A B C a) What type of device does this structure define? S b) What is the purpose of the niso regions in this structure? c) How many mask levels (i.e. patterning steps) are required to form this structure and what regions do they define? d) The starting substrate has a doping of n sub = x10 14 cm 3, the buried layer doping is p bur + = 5x10 18 cm 3 and the epitaxial layer is grown with p epi = 5x10 16 cm 3. The implant used for the n iso region it is N = x10 17 cm 3, the n +  region is N + = x10 18 cm 3 and the p + region is N A + = 5x10 17 cm 3. Calculate the carrier densities n iso, n + and p +. e) Assuming all the PN junctions act as isolated diodes and ignoring parasitic resistances, draw the equivalent circuit for this structure in terms of the contacts A, B, C, and the substrate S. (i.e. draw how the diodes are connected to each other and A, B, C, and S.)
4 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 4 3. The ShockleyReadHall model uses the equation below to calculate the net recombination rate in a semiconductor. U = τ 0 n( x) p( x) ni ( n( x) + p( x) + n ) a) What is meant by lowlevel injection? i b) Under the conditions of lowlevel injection in a ptype material the above expression can be solved to give t τ 0 t τ 0 n np0 = ( n0 np0 ) e = Δn0e. If a ptype material is initially raised by Δn 0 under lowinjection conditions how long will it take the excess carrier concentration to fall to Δn 0 /3 if the minority carrier lifetime is τ 0 = x106 sec? How far, on average, will the carriers diffuse in this time? c) What do the following imply with regards to the generation or recombination of carriers: U = 0? U > 0? U < 0?
5 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 5 p = x10 17 cm A deepdiffused junction substrate diode is formed as shown below with the starting substrate doping sub and an implant of N = 5x10 17 cm 3 to form the n region. The n region extends for 100 µm into the page (to give an n region area of 50 µm x 100 µm). 50 µm 0 µm 30 µm a) Assuming that the uniform doping approximation can be used and there is no current spreading, calculate the total series resistance, R s, of the diode shown above. b) If the process being used allows a maximum current density of J max = 10 3 A/cm what is the maximum current, I max, that this diode can carry? c) Using the results from (a) and (b), calculate the forward voltage, V x, of this diode structure at the maximum current, I max. (Assume L p >> 0µm and L n >> 30µm.)
6 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 6 5. A epitaxial diode ln(i ) vs V x characteristic is measured at T = 300 K and plotted as shown below. The slope in the linear portion of the curve at V x > 3kT/q is found to be Δln( I ) 1 ΔV = 3.0 V measured at high current and found to be I = 75 ma at V x = 1.0 V. ln(i ) x with an intercept of I S = 101 A. A point is I = 75 ma I S = 101 A V x = 0.0 V V x = 1.0 V V x 40 µm a) Extract the values of the series resistance, R s, and ideality factor, n, for this diode from the ln(i ) vs V x characteristic. b) The n+ buried layer is µm thick, the contacts are 40 µm apart and 00 µm wide (into the page). Assume that the buried layer dominates the series resistance and that its n + doping is N = x10 18 cm 3. Using these values calculate the approximate value of R s. (1 µm = 104 cm)
7 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 7 6. The structure of a bipolar junction transistor (BJT) is illustrated below. a) What are the four regions of operation for a bipolar junction transistor (BJT)? b) What is "transistor action" in a BJT? c) Why the forward current gain, β F, is larger than the reverse current gain, β R, in a welldesigned BJT. d) What is the main physical cause of the Early effect in a BJT? e) Why do we call a BJT a "minority carrier" device?
8 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 8 7. A bipolar junction transistor (BJT) has the parameters and biases shown in the diagram below. (T = 300 K) N C =10 16 /cm 3 N AB =10 17 /cm 3 N E =10 19 /cm 3 4 V a) The neutral region widths are W C = µm, W B = 1µm and W E = 0.5µm. If the emitter area of the BJT above is µm by 10µm, what are the values of the base and collector currents? (You may use whatever approximations that are appropriate.) b) What is the maximum field, ε deplmax, in the basecollector junction of the BJT above?
9 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 9 8. A bipolar junction transistor (BJT) has the parameters and currents shown in the diagram below. (T = 300 K) N C =10 16 /cm 3 N AB =10 17 /cm 3 N E =10 19 /cm 3 I BE = 1 ma V CE = 3 V I CE = 100 ma a) If the neutral region width of the emitter is W E = 0.5µm, what is the neutral region width of the base, W B? (You must use the appropriate approximations.) b) What is the collectorbase breakdown voltage with the emitter open, BV CBO, for the BJT shown above if it has a critical field of ε crit = 3x10 5 V/cm?
10 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The smallsignal hybridpi model for the bipolar transistor is shown below. a) In what transistor operating range is this model normally used and what restrictions apply to the use of this model? b) If the transistor collector current, I C is 0 ma, what is the value of the transconductance, g m, for this model? (V BE >> 3kT, T = 300 K) c) If the transistor collector current, I C is 0 ma, what is the value of the output impedance, r 0, for this model (ignoring the Early effect)? (V BE >> 3kT, T = 300 K) d) If the transistor collector current I C = 0 ma and the forward beta β F = 100, what is the value of r π for this model? (V BE >> 3kT, T = 300 K)
11 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The maximum lowfrequency voltage gain achievable using a FET is given by G max = g m /g o. a) Show that, in saturated mode, G max is only dependent on the channelshortening parameter, λ, and the biasing conditions (V GS V T and V S ) of the device. b) What is G max for V GS V T = 1V and V S = V if λ = 0.05 V 1? c) Find an expression for G max if the FET is biased in triode mode. d) What is G max for V GS V T = V and V S = 1V if λ = 0.05 V 1?
12 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The cross section of a simple substrate nchannel MOSFET biased above threshold is illustrated below. a) What is meant by "pinchoff" in a MOSFET and what happens to the channel when pinchoff occurs? b) How do we add the effect of channel shortening to the MOSFET square law model when V S > V Ssat? c) A gate bias of V GS =.5 V is applied to a MOSFET with a threshold voltage of V T = 0.4 V and substrate doping of N A = 5 x cm 3. The gate oxide thickness is t ox = 0 nm and the device has an effective channel length of µm and width of 10 µm. If channel shortening can be ignored, what is the channel current, I, for V S = 1.5V?
13 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The cross section of a simple substrate MOSFET structure is illustrated below. a) How many patterning steps are required to make the structure above and what features does each step define? (In the order in which they are processed.) b) Why do we say that the source and drain implants are "selfaligned" to the gate in a MOSFET process? c) We use the structure above to fabricate a MOSFET with a substrate doping of N A = cm 3 and a heavily doped p +  polysilicon gate. Calculate the threshold voltage, V T, if t ox = 5 nm and V SB = 0V. (T = 300K)
14 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The cross section of a simple substrate MOSFET structure is illustrated below. a) Explain briefly the difference between "drawn channel length" and "effective channel length". b) What is the "short channel effect" on threshold voltage? What are the two main techniques used to mitigate this effect? c) What is drift conduction in a semiconductor? How does drift conduction in a semiconductor change at high electric fields?
15 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page There are three voltage components in the equation used to calculate the basic threshold voltage, V T0, for a MOSFET. V Qˆ dep T 0 = VFB + φ B = VFB + φ B + Cox qε SiN C ox A ( φ ) B a) A simple nmosfet process starts with a substrate doping of p sub = 5x10 16 cm 3 uses a gate oxide (SiO ) with a thickness of 30 nm and a heavily doped p + polysilicon gate. Calculate the basic threshold voltage, V T0, for an nchannel MOSFET in this process. (T = 300K) b) Briefly describe how the threshold voltage is changed if a voltage is applied between the source of the MOSFET and the substrate (bulk).
16 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page A MOSFET has a layout as illustrated in the diagram below. There is 0.5 µm of lateral diffusion under the gate from the source and drain implants and the oxide thickness is t ox = 0 nm. The source and drain are implanted at N = cm 3 into the substrate having an initial doping of N A = 5x10 16 cm µm/division (a) Calculate the intrinsic gatesource capacitance, mode. C int GS, for this MOSFET structure assuming it is operating in saturated (b) Calculate the depletion sourcebulk capacitance, C dep SB, for this device assuming that the bottom depletion capacitance dominants (i.e. all other nonintrinsic capacitances can be neglected) and V SB = 0V, z SB = ½. g m! tot (c) The transit frequency for a FET is given by f!! "C GS g m int "C GS ignore, what is the transit frequency for this device? (Using the result from (a).). If V GS V T = 1V and channel shortening can be
17 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page A MOSFET has a layout as illustrated in the diagram below. There is 0.5 µm of lateral diffusion under the gate from the source and drain implants. 1 µm/division (a) The source and drain are implanted at N = cm 3 into the substrate having an initial doping of N A = 5x10 16 cm 3. Assuming that the sidewall capacitances can be ignored relative to the bottoms, calculate the depletion capacitance of the source and drain if V S = 5V, V SB = 0V, z SB = z B = 1/? (b) Under the same doping and biasing conditions as in (a), how far under the gate will the sidewall depletion regions of the source and drain extend?
18 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 18 Equations Ideal iode qv kt I = IS ( e 1) with depletion region GR: ( qv nkt = 1 ) I IS e with series resistance & GR: ( V I R ) nkt I ( q IS e ) x s = 1 where Vx = V + IRs ShockleyReedHall: n( x) p( x) ni U = τ ( n( x) + p( x) + n ) Einstein Relations: iffusion Length: Saturation Current ensity: 0 kt kt n µ n, p µ p q q L n τ, L τ n 0 J S = J Sh + J Se = q p p n0 w n p i p 0 + q n n p0, for thin n and thin p w p Gaussian Integral: Resistivity: J S = J Sh + J Se = q p p n0 L p 0 e x σ = π σ + q nn p0, for thick n and thick p L n = ( σ n + σ p ) = ( qnµ n + qpµ p ) n ρ p ρ ρ d ψ x de x ρ x = = dx dx ε Si ρ x = q p x n x + N N A kt N AN V = ln bi q ni Poisson's Equation: ( ) ( ) ( ) Excess Charge ensity in a iode: ( ) [ ( ) ( ) ] BuiltIn Voltage: epletion Width: Maximum Electric Field: Avalanche Multiplication Factor: Impact Ionization Probability: iode Junction Conductance: iode Junction Capacitance (per area): W = Charge Control Equation: ( ) Charge Storage Time: Heat Flow: BJT Injection Model Currents: ε Si q N A N q N AN E depl max = ε Si N A + N 1 M = 1 p ii ν, ρ l R = A A ( V ) = = + bi V, xn W, xp W N A N N A + N ( V V ) E depl max p ii =, 3 < ν < 6 E crit di q qv nkt q g = = I Se I dv nkt nkt dqˆ depl dqˆ depl dw N AN Cˆ depl ( V ) = = = q dv dw dv N A + N dqp t Qp( t) = i( t) dt τ 0 I V τ 0 τ V V V dt Φ = κ, Trise = P RTH dx I = I + I, I = I + I, I = I + I F F t s = ln 1 F R >> I 0 ln 1 R V for, R C pc nb B pc I C = qa E pc p C0 W C e qv BC kt 1 I B = qa E pc p C0 W C e qv BC kt 1 bi pe E nb N ε Si N A + N Wq N AN ( ) + qa E nb n B0 ( ) pe W B e qv BE kt e qv BC kt ( ) + qa E pe p E 0 ( ) W E e qv BE kt 1 ( ) + qa E pe p E 0 ( ) I E = qa E nb n B0 W B e qv BE kt e qv BC kt W E e qv BE kt 1 N ε Si = W V ( )
19 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 19 BJT EbbersMoll Model: I ES qa E nb n B0 W B + qa E pe p E 0 W E I CS qa E nb n B0 W B + qa E pc p C0 W C BJT Base iffusion Capacitance: BJT Transit Frequency: MOSFET Gate Capacitance: (per unit area) rift Conduction: Carrier ensity Relative to E F qa α F E nb n B0 W B qa α R E nb n B0 W B qa E nb n B0 W B + qa E pe p E 0 W E qa E nb n B0 W B + qa E pc p C0 W C ( ) α R I CS e qv BC ( kt 1) ( ) + ( 1 α R )I CS e qv BC ( kt 1) ( ) I CS e qv BC ( kt 1) I E = I ES e qv BE kt 1 I B = ( 1 α F )I ES e qv BE kt 1 I C = α F I ES e qv BE kt 1 B W Cπ = τ Bgm, τ B = nb 1 f τ = π " C depbc + C depbe Ĉ ox = ε ox t ox! ( ) g m +τ B J = qnv n + qpv p = qnµ n + qpµ p # $ ( )ε = σε n = N C e ( E C E F ) kt, p = N V e ( E F E V ) kt Flat Band Voltage: V FB = Φ MS q = Φ M Φ S Bulk Potential (ptype): φ B = kt q ln! N $ A # & " % MOSFET Threshold Voltage (V SB =0): MOSFET Threshold Modulation: MOSFET Square Law Model: Channel shortening depletion charge: n i ( ) q ( ) V T 0 = V FB + ϕ B ˆQ dep = V FB + ϕ B + qε SiN A ϕ B C ox V T = V T 0 +γ ( φ B +V SB φ B ), γ = qε SiN A Ĉ ox W " I = µ n Ĉ ox ( L V GS V T )V S V % S $ '( 1+ λv S ), V GS V T,V S V S,sat # & W "( V = µ n Ĉ GS V T ) % ox L $ # '( 1+ λv S ), V GS V T,V S V S,sat & Qdep ˆ! = ˆQ ) dep 1 x # J 1+ W S + 1+ W &, + L % $ x J x (. * + J '. C ox MOSFET Transconductance: MOSFET Output Conductance: W S ε Si ( φ B +V SB ), W ε Si φ B +V B qn A qn A g m = di dv GS VS g o = di W = µ n Ĉ ox dv S VGS L ( ) W = µ n Ĉ ox ( L V V GS T )( 1+ λv S ), V GS V T,V S V S,sat ( V GS V T ) λ, V GS V T,V S V S,sat MOSFET epletion Capacitances: MOSFET Overlap Capacitances: MOSFET Intrinsic Capacitances: MOSFET Velocity Saturation Model: MOSFET Current with Vel. Sat. : C! C SB = depsw P S 1+V SB V bisb ( ) z SB C GS,ovl = C G,ovl = ε ox x ovl W t ox C GS = ( 3 C " * V ox 1 GS V T * $ # V GS V ) T µ v = 0 ε 1+ε ε crit W I = µ n Ĉ ox L 1+V S Ĉ + depbot A S 1+V SB V bisb ( ) z SB ( ) V S ( ) V S Lε crit ( ( )) C!, C B = depsw P 1+V B V bib ( ) z B % +  ' & , C G = ( 3 C " * V ox 1 GS V T * $ V, # GS V ) T ( ) ( ) V S Ĉ + depbot A 1+V B V bib ( ) z B % +  ' &  for V S V S,sat, "( V GS V T ) % $ # '( 1+ λv S ), V GS V T,V S V S,sat &
20 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 0 Physical Constants and Material Properties Quantity Symbol Value Micron µm 104 cm = 106 m Angstrom Unit Å 108 cm = m Boltzmann s Constant k 8.6x105 ev/k 1.381x103 J/K Electronic Charge q 1.60x1019 C Electron Volt ev 1.60x1019 J Electron Rest Mass m o 9.11x1031 kg Free Space Permittivity ε o 8.854x1014 F/cm Plank s Constant h 6.66x Js 4.14x1015 evs Thermal Voltage at 300K 1kT/q V Properties of Silicon at 300K Quantity Symbol Value Intrinsic Carrier Concentration n i 1.45x10 10 cm 3 Effective ensities of States N v 1.08x10 19 cm 3 N c.8x10 19 cm 3 Electron Affinity χ Si 4.05 ev Energy Gap E g 1.08 ev Bulk Electron Mobility µ n 1350 cm /Vs Bulk Hole Mobility µ p 470 cm /Vs Surface Electron Mobility µ n 50 cm /Vs Permittivity ε Si 11.7ε o Properties of Silicon ioxide Quantity Symbol Value Permittivity ε ox 3.9ε o
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