An Analysis on a Pseudo- Differential Dynamic Comparator with Load Capacitance Calibration

Transcription

1 An Analysis on a Pseudo- Differential Dynamic omparator with Load apacitance alibration Daehwa Paik, Masaya Miyahara, and Akira Tokyo Institute of Technology, Japan 011/10/7

2 ontents 1 Topology of Dynamic omparator Analysis onditions General Analysis Gain of Dynamic Amplifier Load apacitance alibration What Decides ompensated oltage Influence of PT ariation onclusion 011/10/7

3 An Analyzed omparator oltage [] Fig. Transient waveform of a comparator [6], [7]. 011/10/7 LK Latch becomes high 1. Electric charge on the node Out int flows into gnd. urrent difference is determined by input signals The difference is integrated on Out int and becomes larger as time passes 3. The second stage regenerates the voltage difference [6] M. Miyahara, et al., ASS, 008 [7] D. Paik, et al., IEIE Trans. on Fundamentals, 010

4 Analysis onditions of a Pre-amplifier 3 Process is 90-nm MOS The size of all transistors is µm/100 nm To simplify the analysis The rising time of LK Latch to 1 ps M 3 and M 4 are in the deep triode when LK Latch is high out_int can be approximated as the drain voltage of M 1 (or M gnd In p Out p_int I DSp LK Latch M 5 M 6 M 3 M 4 M 1 M gnd gnd Out n_int I DSn gnd In n Simplify Fig. Simplified schematic of a dynamic amplifier when the LK Latch is high. gnd In p Out p_int I DSp out_int = LK Latch I M 1 M gnd gnd DS t Out n_int I DSn gnd In n 011/10/7

5 Mismatch ontribution 4 011/10/7 Fig. Mismatch contribution (Remains are.4 %. []. Giannini, et al., ISS, 008 [3] G. an der Plas, et al., ISS, 008 Mismatch is dominated by a pair of input transistors Mismatch of the second stage is suppressed by the gain of the pre-amplifier I DS is mainly decided by input transistors Mismatch changes I DS and the slew rate of Out int is also varied out_int = I DS t d out_int dt = Load capacitance calibration [], [3] is commonly used to compensate mismatch To figure out the calibration ect, the gain is required I DS

6 hannel-length Modulation 5 I DS is affected by the channel-length modulation λ is the channel-length coicient out_int = I DS t I DS = 1 µ OX W L ( 1+ λ( DS DS_sat IDS [A] Actual model (I DS w/ Ideal model (I DS w/o GS th DS_sat = the saturation condition of drain-source voltage (= DS [] Fig. Influence of the channel-length modulation. 011/10/7

7 Gain of A Dynamic Amplifier 6 G amp_trans is satisfied only when out_int If out_int falls to, G amp_trans reaches its maximum 011/10/7 G amp_trans v = v out in idst 1 = v a. = 0.15 b. = 0.0 c. = 0.5 d. = 0.30 e. = Simulation results a 5 Estimation b 4 c 3 e d DS [] in = ( 1+ λ( Gain [times] DS λ 1+ ( + (a various (b various channel length when is 0. Fig. Gain of a pre-amplifier. DS DS DS [] a. (W/L input = 6 m/300 nm b. (W/L input =.4 m/10 nm c. (W/L input = m/100 nm Simulation results Estimation Estimation ( = 0 a b c

8 Load apacitance alibration 7 Using binary-weighted PMOS varactors By turning on or off PMOS, capacitance is varied Reduce offset voltage LK Latch M 5 M 6 Out p_int M 3 M 4 Out n_int out_int outp_int outn_int out_int DB[0:N al 1] In p M 1 M In n Error is decreased gnd gnd Error apacitors for calibration (A number of unit cap. at each code = D[i] LK Latch Time LK Latch cal. Time Before calibration After calibration D[0] D[1] D[] D[N al 1] Fig. Load capacitance calibration. Fig. Error reduction by calibration ( inp = inn. 011/10/7

9 Input-Referred ompensated oltage 8 Assumption Input signal of the second stage is decided when gain reaches its maximum v in_diff_cal dout_int = d = 1+ input-referred λ Ncal 1 ( ( N ( cal ode on off (N ode Ncal 1 : N ode from the mile of calibration code N ode : calibration code N al : calibration resolution ( on off : capacitance difference of a unit PMOS varactor on : on capacitance of a unit PMOS varactor off : off capacitance of a unit PMOS varactor 011/10/7

10 Simulation Results 9 Simulation condition 1 LSB = 1.5 m = 1.0 and in_com = 0.5 Size of a unit varactor is W/L = 600 nm/100 nm Estimation : 1+ λ Ncal 1 ( ( N ( ode on off Input-referred compensated voltage [m] Fig. Input-referred compensated voltage by the capacitance calibration. 011/10/7

11 PT ariation 10 If surrounding condition is varied after compensation, calibration accuracy is degraded Process is fixed in the factory oltage and Temperature should be considered Assumption An error due to PT variation, σ _PT, is uncorrelated with offset after calibration, σ _offset0 σ _offset = σ _offset0 + σ _PT (σ _offset0 is extracted from simulation data 011/10/7

12 Input ommon-mode oltage 11 Input common-mode voltage is fluctuated Standard deviation of calibration code is σ ode σ _ PT _ OM Error due to Error due to λ = Error due to = = v = in_diff_cal in _ com 1+ λ in _ com ( ( on off σ ode λ ( ( on off σ ode λ ( = ( on off σ ode 1+ λ ( λ + λ ( + + ( λ λ( ( on off σ ode 011/10/7

13 Simulation Results 1 alibration is conducted when is 1.0, in_com is 0.5, and Temp is 7 _offset [m] SNDR decrease [db] SNDR decrease = SNDR SQNR 1 = 10log 1+ σ q Fig. Influence of input common-mode voltage on the capacitance calibration (1 LSB = 4.5 m and a number of the Monte arlo simulation is /10/7

14 Influence of Supply oltage 13 alibration is conducted when is 1.0, in_com is 0.5, and Temp is 7 Simulation results Estimation SNDR decrease σ _ PT _ = 1+ λ λ ( + λ( ( on off σ ode Supply voltage after calibration [] Fig. Influence of supply voltage on the capacitance calibration (1 LSB = 4.5 m and a number of the Monte arlo simulation is /10/7

15 Influence of Temperature 14 alibration is conducted when is 1.0, in_com is 0.5, and Temp is 7 _offset [m] σ SNDR decrease [db] _ PT _ T = + 1+ th λ ( λ + + λ ( λ + λ( ( on off σ ode ( th 1 Fig. Influence of temperature on the capacitance calibration (1 LSB = 4.5 m and a number of the Monte arlo simulation is /10/7

16 onclusions 15 A pseudo-differential dynamic comparator with load capacitance calibration is analyzed The gain of a dynamic amplifier Expressed by a ratio of to and λ of an input transistor Gain is inversely proportional to Thermal noise, input-referred compensate voltage, and influence of PT variation are analyzed A dynamic comparator is sensitive to PT variation Mainly decided by 011/10/7

17 Acknowledgements 16 This work was partially supported by MI, REST in JST, NEDO, Berkeley Design Automation for the use of the Analog FastSPIE(AFS Platform, and DE in collaboration with adence Design Systems, Inc. 011/10/7

18 References 17 [1] Tsuguo Kobayashi, et al., in IEEE Journal of Solid-State ircuits, vol. 8, no. 4, pp , Apr., [] ito Giannini, et al., in IEEE International Solid-State ircuits onference Digest of Technical Papers, pp , Feb., 008. [3] Geert an der Plas, et al., in IEEE International Solid-State ircuits onference Digest of Technical Papers, pp. 4-43, Feb., 008. [4] Michiel van Elzakker, et al., in IEEE Journal of Solid-State ircuits, vol. 45, no. 5, pp , May, 010. [5] Daniël Schinkel, et al., in IEEE International Solid-State ircuits onference Digest of Technical Papers, pp , Feb., 007. [6] Masaya Miyahara, et al., in IEEE Proceedings of Asian Solid-State ircuits onference, pp. 69-7, Nov., 008. [7] Daehwa Paik, et al., in IEIE Transactions on Fundamentals of Electronics, ommunications and omputer Sciences, vol. E93-A, no., pp , Feb., 010. [8] Asad A. Abidi, in IEEE Journal of Solid-State ircuits, vol. 41, no. 8, pp , Aug., 006. [9] John K. Fiorenza, et al., in IEEE Journal of Solid-State ircuits, vol. 41, no. 1, pp , Dec., 006. [10] Pierluigi Nuzzo, et al., in IEEE Transactions on ircuits and System I: Regular Papers, vol. 55, no. 6, pp , Jul., 008. [11] To Sepke, et al., in IEEE Transactions on ircuits and System I: Regular Papers, vol. 56, no. 3, pp , Mar., 009. [1] Akira, in IEEE Proceedings of International onference on ASI, pp. 18-1, Oct., 009. [13] Jun He, et al., in IEEE Transactions on ircuits and System I: Regular Papers, vol. 56, no. 5, pp , May, /10/7