A 74.9 db SNDR 1 MHz Bandwidth 0.9 mw Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Transcription

1 A 74.9 db SNDR 1 MHz Bandwidth 0.9 mw Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan

2 Outline 2 Introduction Circuit design Charge-pump Time-domain feedback SAR ADC as quantizer Performance summary Conclusion

3 Emitter Absorber Time to Digital Converter 3 Measuring time difference between electrical events Particle detector in High Energy Physics Positron Emission Tomography γ-detector T 1 + T 2 TDC γ TDC Laser range finder All Digital PLL T 1 Laser TDC Object F ref Phase Detector TDC Digital Filter DCO Fout T 2 Detector Counter

4 TDC Prior Arts 4 Flash / delay-line Simple Technology-limited resolution Pipeline High resolution Require a linear time amplifier CK 1 t d t d t d Inter-stage mismatch Coarse Fine CK 2 CK 1 CK 2 Delay line TA Delay line D out Thermal to binary encoder D out Logic [R. Staszewski, RFIC 04] [M. Lee, VLSIC 07]

5 ΔΣ TDC Prior Arts 5 Gated Ring Oscillator Breaking the technologylimited resolution Dead-zone issue Switched Ring Oscillator No dead-zone issue Always running VCO high power V H V L T in GRO T in SRO Clr Clr Differentiator Differentiator Out Out [M.Z. Straayer, JSSC 09] [A. Elshazly, JSSC 14]

6 Voltage-domain TDC 6 Time-to-voltage followed by analog-to-digital conversion More relaxed technology-constrained resolution High resolution ADC is required CK 1 CK 2 PFD UP DN CLR C ADC D out Typical implementation o Charge-pump + SAR ADC [Z. Xu, CICC 13] o Charge-pump + ΔΣ ADC [M.B. Dayanik, ESSCIRC 15]

7 Mixed-domain ΔΣ TDC Gm-cell as integrator + time-domain feedback Simplified ADC design Power-starving integrator Only for positive input T in T dtc Gm Σ C T dtc Counter ADC 7 D out Ф fast DTC [M. Gande, VLSIC 12]

8 Proposed Mixed-domain ΔΣ TDC 8 Integrator implementation by charge preservation Compact design Low power Differential input CK 1 CK 2 Δ Time sub TVC and Σ PFD UP DN C Lowresolution ADC ADC D out DTC

9 Charge-pump as Integrator 9 Bottom-plate sampling Reduces charge injection Prevents charge-pump s current mismatch CK 1 CK 1 D Q D R CK R 1 CK 1 Td CK 2 CK R 2 R I CP I CP UP UP Q Td D Q D Q DN DN ΔV o = I CP. T in / I CP I CP S 1 S V 1 o CK 2 UP DN V o CK 2 UP DN S 2 S 2 S 1 S 1 T in T in V o V o ΔV o ΔV o T d T d S 2 S 2 sampling sampling sampling sampling conversion conversion

10 Charge-sharing Phenomenon 10 Op-amp can reduce chargesharing before and after sampling 1. Before sampling 2. Sampling 3. Sampling finish I CP C PP spilled charge C PP I CP V O V DD /2 V O V O -ΔV O V DD /2 V DD /2 spilled charge C PN C PN CK 1 CK 2 UP I CP equal charge I CP I CP DN V O + - V M C PP V O + - V M C PP V O + - V M V O I CP I CP I CP equal charge C PN C PN

11 Pseudo Diff. Charge-pump 11 Op-amps provide an isolated CMFB voltage from the actual sampled voltage CMFB V BP C CM2 V CM Ф 2 Ф 1 C CM1 V BP,CMFB V CP Ф 1 Ф 2 UP V CUP UP DN V CUN DN V OP + - V MP R M V M R M C CM1 V MN + - V ON V OP DN + - V CD V MP R M R M V M DN UP V MN + - V CD V ON UP P N V CN V BN

12 Time-domain Feedback 12 Using delay-line Digital-to-Time Converter (DTC) Input is delayed based on TDC s output T IN D IN Positive input Negative input CK 1 CK 2 T OUT T IN T IN -T OUT>0 OUT>0 delay CK 1 T IN -T OUT<0 OUT<0 delay CK 2 DTC Time subtraction method

13 SAR Logic Proposed ΔΣ TDC Architecture 13 Δ D out > 0 TVC and Σ 4-bit SAR ADC CK 1 0 I CP CDAC DTC CK 2 1 D out < 0 0 PFD UP DN DN UP V dacp V inp V inn D out DTC 1 I CP V dacn CDAC z -1

14 Noise power (db) SNDR (db) TDC Noise Analysis 14 Thermal noise and quantization noise are the dominant noise sources = 0.5 pf Thermal noise Quantization noise dominates Thermal noise dominates Total noise Quantization noise Quantizer size (bit) without thermal noise = 2 pf 1 pf 0.5 pf 0.25 pf with thermal noise Quantizer size (bit)

15 SAR Logic SAR ADC Quantizer 15 SAR ADC: low power, low complexity, moderate speed Separated CDAC and charge-pump capacitor Reduce disturbance to sampled charge Smaller CDAC cap for faster conversion V outn + - D out V outp 2 N-1 C u C u C u V in V dac + - CK CK V dacn V inp V dacp V inn V refn V refp CDAC CK [M. Miyahara, A-SSCC 08]

16 Normalized PSD (db) SNDR (db) Performance Summary khz 2.4ns pp input at 1 MHz bandwidth, 200 MHz sampling freq SNDR = 74.9 db ENOB = 12.1 bit F BW db/dec Frequency (MHz) Input amplitude (dbfs)

17 121 μm Core Layout Implementation 17 Core area: mm μm

18 Performance Comparison 18 JSSC 09 JSSC 14 CICC 13 ESSCIRC 15 VLSIC 12 This* ΔΣ TDC Type GRO SRO GSRO CP+ ΔΣ ADC CP+ Gm-C CP+ SAR Filter order 1 st 1 st 2 nd 3 rd 3 rd 1 st CMOS (nm) Sampling (MHz) Bandwidth (MHz) SNDR (db) N/A Integ. noise (fs rms ) Resolution (ps)** Power (mw) FoM (fj/conv)*** N/A Area (mm 2 ) *Transistor-level simulation **Resolution = 12 integrated noise ***FoM = Power/(2 bandwidth 2 (SNDR-1.76)/6.02 )

19 Conclusion 19 A mixed time and voltage domain TDC is proposed Charge-pump is used both as VTC and integrator to achieve low power performance The ΔΣ implementation allows a good TDC resolution while only using a low bit SAR ADC as quantizer

20 Acknowledgement 20 This work was partially supported by MIC, STARC, HUAWEI, Mentor Graphics for the use of the AFS Platform, and VDEC in collaboration with Cadence Design Systems, Inc.

21 A 74.9 db SNDR 1 MHz Bandwidth 0.9 mw Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa firdaus@ssc.pe.titech.ac.jp