Lecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1

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1 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 LECTURE 34 CHARACTERZATON OF DACS AND CURRENT SCALNG DACS LECTURE ORGANZATON Outline ntroduction Static characterization of DACs Dynamic characterization of DACs Testing of DACs Current scaling DACs Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 342 NTRODUCTON mportance of Data Converters in Signal Processing ANALOG SGNAL (Speech, sensors, radar, etc.) PREPROCESSNG (Filtering and analog to digital conversion) DGTAL PROCESSOR (Microprocessor) POSTPROCESSNG (Digital to analog conversion and filtering) ANALOG OUTPUT SGNAL CONTROL ANALOG A/D DGTAL D/A ANALOG

2 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 343 DigitalAnalog Converters Digital Signal Processing System Microprocessors Compact disks Read only memory Random access memory Digital transmission Disk outputs Digital sensors DGTAL ANALOG CONVERTER Filter Amplifier Analog Output Reference Fig.. s: Can be asynchronous or synchronous Primary active element is the op amp Conversion time can vary from fast (one clock period, T) to slow (2 No. of bits *T) Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 344 AnalogDigital Converters Analog nput Sample and Hold ANALOG DGTAL CONVERTER Digital Signal Processing System Microprocessors Compact disks Read only memory Random access memory Digital transmission Disk outputs Digital sensors 6922 Reference s: Can only be synchronous (the analog signal must be sampled and held during conversion) Primary active element is the comparator Conversion time can vary from fast (one clock period, T) to slow (2 No. of bits *T)

3 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 345 STATC CHARACTERSTCS OF DGTALANALOG CONVERTERS Block Diagram of a DigitalAnalog Converter Voltage Reference V REF Scaling DVREF Output vout = Network Amplifier KDV REF Binary Switches b b b 2 b N Figure.3 b is the most significant bit (MSB) The MSB is the bit that has the most (largest) influence on the analog output b N is the least significant bit (LSB) The LSB is the bit that has the least (smallest) influence on the analog output Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 346 nputoutput s deal inputoutput characteristics of a 3bit DAC. Analog Output Value Normalized to VREF LSB nfinite Resolution Vertical Shifted. Digital nput Code Fig..4

4 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 347 Definitions Resolution of the DAC is equal to the number of bits in the applied digital input word. The full scale (FS): FS = Analog output when all bits are Analog output all bits are FS = (V REF V REF ) = V REF Full scale range (FSR) is defined as FSR = lim N (FS) = V REF Quantization Noise is the inherent uncertainty in digitizing an analog value with a finite resolution converter. Quantization Noise LSB.5LSB LSB.5LSB Digital nput Code Fig..5 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 More Definitions Dynamic Range (DR) of a DAC is the ratio of the FSR to the smallest difference that can be resolved (i.e. an LSB) FSR DR = LSBchange = FSR (FSR/) = 2 N or in terms of decibels DR(dB) = 6. (db) Signaltonoise ratio (SNR) for the DAC is the ratio of the full scale value to the rms value of the quantization noise. rms(quantization noise) = T T t LSB 2 T.5 2 dt = LSB 2 = FSR 2 N 2 (rms) SNR = (FSR/ 22 N ) Maximum SNR (SNR max ) for a sinusoid is defined as max (rms) SNR max = (FSR/ 22 N ) = FSR/(2 2) FSR/( 22 N ) = 62 N 2 or in terms of decibels SNR max (db) = 2log 62 N 2 = log (6)2 log (2 N )2 log (2) = db

5 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 349 Even More Definitions Effective number of bits (ENOB) can be defined from the above as ENOB = SNR Actual where SNR Actual is the actual SNR of the converter. Comment: The DR is the amplitude range necessary to resolve N bits regardless of the amplitude of the output voltage. However, when referenced to a given output analog signal amplitude, the DR required must include.76 db more to account for the presence of quantization noise. Thus, for a bit DAC, the DR is 6.2 db and for a fullscale, rms output voltage, the signal must be approximately 62 db above whatever noise floor is present in the output of the DAC. Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 Accuracy Requirements of the ith Bit The output of the ith bit of the converter is expressed as: The output of the ith bit = V REF 2 i 2 n 2 n = 2 ni LSBs The uncertainty of each bit must be less than ±.5 LSB (assuming all other bits are ideal. Must use ±.25 LSB if each bit has a worst case error.) The accuracy of the ith bit is equal to the uncertainty divided by the output giving: Accuracyoftheithbit= ±.5LSB 2 ni LSB = 2 ni = 2 ni % Result: The highest accuracy requirement is always the MSB (i = ). The LSB bit only needs ±5% accuracy. Example: What is the accuracy requirement for each of the bits of a bit converter? Assuming all other bits are ideal, the accuracy requirement per bit is given below. Bit Number Accuracy % (f all other bits are worst case, the numbers above must be divided by 2.)

6 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 Offset and Gain Errors An offset error is a constant difference between the actual finite resolution characteristic and the ideal finite resolution characteristic measured at any vertical jump. A gain error is the difference between the slope of the actual finite resolution and the ideal finite resolution characteristic measured at the rightmost vertical jump. Analog Output Value Normalized to VREF 7/ 6/ Actual Analog Output Value Normalized to VREF 5/ Offset 4/ Error nfinite 3/ Resolution 2/ deal 3bit / Resolution Digital nput Code Offset Error in a 3bit DAC 7/ 6/ 5/ Gain Error Actual 4/ nfinite 3/ Resolution 2/ deal 3bit / Resolution Digital nput Code Gain Error in a 3bit DAC Fig..6 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 342 ntegral and Differential Nonlinearity ntegral Nonlinearity (NL) is the maximum difference between the actual finite resolution characteristic and the ideal finite resolution characteristic measured vertically (% or LSB). Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels measured at each vertical jump (% or LSB). DNL = V cx V s = V cx V s V s V s = V cx V s LSBs where V cx is the actual voltage change on a bittobit basis and V s is the ideal LSB change of (V FSR /2 N ) nfinite Resolution 7 Example of a 3bit DAC: Analog Output Voltage.5 LSB DNL 6 5 Nonmonotonicity LSB NL 4.5 LSB NL A 3.5 LSB DNL 2 deal 3bit Actual 3bit Digital nput Code Fig..7

7 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 343 Example of NL and DNL of a Nonideal 4Bit Dac Find the ±NL and ±DNL for the 4bit DAC shown. Analog Output (Normalized to Full Scale) 5/6 4/ /6 /6 /6 9/6 /6 7/6 6/6 5/6 4/6 3/6 2/6 /6 /6 b b b 2 b 3.5 LSB NL 2 LSB DNL deal 4bit DAC Digital nput Code.5 LSB NL.5 LSB DNL 2 LSB DNL Actual 4bit DAC Fig.. Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 344 DYNAMC CHARACTERSTCS OF DGTALANALOG CONVERTERS Dynamic characteristics include the influence of time. Definitions Conversion speed is the time it takes for the DAC to provide an analog output when the digital input word is changed. Factor that influence the conversion speed: Parasitic capacitors (would like all nodes to be low impedance) Op amp gainbandwidth Op amp slew rate Gain error of an op amp is the difference between the desired and actual output voltage of the op amp (can have both a static and dynamic influence) Actual Gain = deal Gain x LoopGain LoopGain Gain error = dealgainactualgain dealgain = LoopGain

8 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 345 Example of nfluence of Op Amp Gain Error on DAC Performance Assume that a DAC using an op amp in the inverting configuration with C = C 2 and A vd () =. Find the largest resolution of the DAC if V REF is V and assuming worst case conditions. Solution C 2 The loop gain of the inverting configuration is LG = C C2 A vd() =.5 = 5. The gain error is therefore /5.2. The gain error should be less than the quantization noise of ±.5LSB which is expressed as Gain error = 5.2 V REF 2 N Therefore the largest value of N that satisfies this equation is N = 7. Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 346 nfluence of the Op Amp Gainbandwidth Singlepole response: v out (t) = A CL [ e H t]v in (t) where A CL = closedloop gain H = GB R R R 2 or GB C 2 C C 2 To avoid errors in DACs (and ADCs), v out (t) must be within ±.5LSB of the final value by the end of the conversion time. Multiplepole response: Typically the response is underdamped like the following (see Appendix C of text). v N (t) Final Value ε Final Value Final Value ε ε ε Upper Tolerance Lower Tolerance Settling Time t T s Fig. 6.7

9 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 347 Example of the nfluence of GB and Settling Time on DAC Performance Assume that a DAC uses a switched capacitor noninverting amplifier with C = C 2 using an op amp with a dominant pole and GB = MHz. Find the conversion time of an bit DAC if V REF is V. Solution From the results in Sections 9.2 and 9.3 of the text, we know that H = C 2 C C 2 GB = (2)(.5)( 6 ) = 3.4x 6 and A CL =. Assume that the ideal output is equal to V REF. Therefore the value of the output voltage which is.5lsb of V REF is 2 N = e H T or 2 N = e H T Solving for T gives T = N H ln(2) =.693 N H = =.96μs Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 nputoutput Test Test setup: Digital Word nput (N2 bits) Nbit DAC under test TESTNG OF DACs V out ADC with more resolution than DAC (N2 bits) ADC Output Digital Subtractor (N2 bits) Digital Error Output (N2 bits) Fig..9 Comments: Sweep the digital input word from... to... The ADC should have more resolution by at least 2 bits and be more accurate than the errors of the DAC NL will show up in the output as the presence of s in any bit. f there is a in the Nth bit, the NL is greater than ±.5LSB DNL will show up as a change between each successive digital error output. The bits which are greater than N in the digital error output can be used to resolve the errors to less than ±.5LSB

10 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 349 Spectral Test Test setup: Comments: Digital input pattern is selected to have a fundamental frequency which has a magnitude of at least 6N db above its harmonics. Length of the digital sequence determines the spectral purity of the fundamental frequency. Digital Pattern Generator (N bits) Clock Nbit DAC under test All nonlinearities of the DAC (i.e. NL and DNL) will cause harmonics of the fundamental frequency The THD can be used to determine the SNR db range between the magnitude of the fundamental and the THD. This SNR should be at least 6N db to have an NL of less than ±.5LSB for an ENOB of Nbits. Note that the noise contribution of V REF must be less than the noise floor due to nonlinearities. f the period of the digital pattern is increased, the frequency dependence of NL can be measured. V REF V out V out t Distortion Analyzer Vout(jω) fsig Noise floor due to nonlinearities Spectral Output ω Fig.. Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 342 CURRENT SCALNG DGTALANALOG CONVERTERS Classification of DigitalAnalog Converters DigitalAnalog Converters Serial Parallel Charge Current Voltage Charge Voltage and Charge Slow Fast Fig..2

11 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 342 General Current Scaling DACs Digital nput Word V REF Current Scaling Network 2 N R F Fig..22 The output voltage can be expressed as V OUT = RF( 2 N ) where the currents,, 2,... are binary weighted currents. Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 3422 BinaryWeighted Resistor DAC Circuit: V REF RF = K(R/2) S S S 2 2 S N N R 2R 4R R O RMSB R LSB Fig..23 Comments:.) R F can be used to scale the gain of the DAC. f R F = KR/2, then =R F O = KR b 2 R b 2R b 2 4R b N 2 N R V REF =K b 2 b 4 b 2 b N 2 N V REF where b i is if switch S i is connected tov REF or if switch S i is connected to ground. 2.) Component spread value = R MSB R R LSB = 2 N R = 2 N 3.) Attributes: nsensitive to parasitics fast Large component spread value Trimming required for large values of N Nonmonotonic

12 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 3423 R2R Ladder mplementation of the Binary Weighted Resistor DAC Use of the R2R concept to R R 2R avoid large element spreads: 2R 2R 2R 2 2R N RF = KR V REF S S S 2 S N O Fig..24 How does the R2R ladder work? 4 2 The resistance seen to the right of any V REF of the vertical 2R resistors is 2R. R R 2R Attributes: 4 2 2R 2R 2R Not sensitive to parasitics Fig..24(2RR) (currents through the resistors never change as S i is varied) Small element spread. Resistors made from same unit (2R consist of two in series or R consists of two in parallel) Not monotonic Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 3424 Current Scaling Using Binary Weighted MOSFET Current Sinks Circuit: REF = V DD A 2 V A R S 2 SN3 S N2 S N 4 2 b b N3 b N2 bn A Transistor Array V A matched FETs 4 matched FETs 2 matched FETs Fig..25 Operation: = R 2 (b N b N2 2 b N3 4 b ) f = REF = V REF b, then v R OUT = 2 2 b 4 b 2 b N3 2 b N2 b N V REF Attributes: Fast (no floating nodes) and not monotonic Accuracy of MSB greater than LSBs

13 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 3425 HighSpeed Current DACs Current scaling DAC using current switches: b R L V DD R L b b b b 2 b2 b N bn where 2 = R b L 2 b 4 b 2 b N 2 N b i = ifthebitis ifthebitis A singleended DAC can be obtained by replacing the left R L by a short. Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 3426 HighSpeed, HighAccuracy Current Scaling DACs The accuracy is increased by using the same value of current for each switch as shown. d R L V DD R L d d d d 2 d2 d 3 d3 d 4 d4 d 2 N d 2 N d d d 2 d 3 d 4 d2 N N to 2 N Encoder b b b 2 b N For a 4 bit DAC, there would be 6 current switches. The MSB bit would switch of the current switches to one side. The nextmsb bit would switch 4 of the current switches to one side. Etc

14 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 3427 ncreasing the Accuracy of the Current Switching DAC The accuracy of the previous DAC can be increased by using dynamic element matching techniques. This is illustrated below where a butterfly switching element allows the switch control bits, d i, to be randomly connected to any of the current switches. q R L V DD R L q q q q 2 q2 q 3 q3 q 4 q4 q 2 N q 2 N q q q 2 q 3 q 4 q2 N Butterfly Randomizer Any d i can be connected to any q i according to the dynamic element matching algorithm selected. d d d 2 d 3 d 4 d 2 N N to 2 N Encoder b b b 2 b N Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 342 SUMMARY DACs scale a voltage reference as an analog output according to a digital word input Quantization noise is an inherent ±.5 LSB uncertainty in digitizing an analog value with a finite resolution converter The most significant bit requires the greatest accuracy with the least significant bit requiring the least accuracy ntegral Nonlinearity (NL) is the maximum difference between the actual finite resolution characteristic and the ideal finite resolution characteristic measured vertically (% or LSB) Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels measured at each vertical jump (% or LSB) The limits to DAC speed include: Parasitic capacitors The op amp gainbandwidth The op amp slew rate Current scaling DACs scale the reference voltage into binaryweighted currents that are summed into to a resistor to obtain the analog output voltage. Current scaling DACs are generally fast but have large element spreads and are not monotonic