GR16. Technical Manual. 10 M SPS, 16-bit Analog Signal Digitizer up to 8MB FIFO

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1 GR M SPS, -bit Analog Signal Digitizer up to MB FIFO Technical Manual 90 th Street, Davis, CA 9, USA Tel: Fax: sales@tern.com web site:

2 COPYRIGHT GR, EL, Grabber, and A-Engine are trademarks of TERN, Inc. AmES and AmES are trademarks of Advanced Micro Devices, Inc. Version.00 October, 0 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of TERN, Inc th Street, Davis, CA 9, USA Tel: Fax: sales@ tern.com Web site: Important Notice TERN is developing complex, high technology integration systems. These systems are integrated with software and hardware that are not 0% defect free. TERN products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices, or systems, or in other critical applications. TERN and the Buyer agree that TERN will not be liable for incidental or consequential damages arising from the use of TERN products. It is the Buyer's responsibility to protect life and property against incidental failure. TERN reserves the right to make changes and improvements to its products without providing notice.

3 . Functional Description The GR is an inexpensive high speed (up to M samples per second), -bit analog signal digitizer, designed to be driven by a host TERN -bit controller, such as -Engine, AE, or EE. The GR supports a -bit Delta-Sigma ADC (ADS). With its outstanding high-speed performance, it is well-suited for demanding applications in data acquisition, scientific instruments, test equipment and communications. The GR is designed as an expansion board, measuring. by. inches, for TERN -bit controllers such as A-Engine, -Drive, EE, and FN. The GR interfaces to TERN host controller via 0x pins at J, and x pins at J.. ADS -Bit, MSPS Analog-to-Digital Converter The ADS is a high-speed, high-precision, delta-sigma analog-to-digital converter (ADC) with -bit resolution. Inputs INP (H00.) and INN (H00.) are directly routed to the differential inputs of the ADS without buffer circuits. The GR also has two buffered inputs, A- (H0.) and A+ (H0.). A- and A+ are routed to INN and INP via Ohm resistors. Analog input signals must be able to handle the load presented by the switching capacitors within ADS. The GR configures the ADS with V REF = V (V REFN = V and V REFP = V). The -bit ADC data format is in binary two's complement. With V REFN = V and V REFP = V, the resulting input reference V REF = (V - V) = V. In this case, ADC outputs are: When INP > INN, the ADC outputs 0-0xFFF When INP < INN, the ADC outputs 0x000-0xFFFF. When INP INN = V, the ADC outputs 0xFFF. When INN INP = V, the ADC outputs 0x000. When INN = INP, the ADC outputs 0 or 0xFFFF. To achieve the highest analog performance, the recommended differential analog input voltage range is V x 0.9 =.V. The absolute input voltage with respect to, on either INN or INP pin, must be within V REFN = V to V REFP = V range. Recommended circuit designs are available when using single-ended or differential op amps, respectively. See ADS data sheet for details ( The GR has an array of through-hole pads (H0, H00, H0) to allow installing user custom analog signal conditioning circuits.

4 . ADC Sampling Modes Three operation modes are available: ADC-read, ADC-FIFO, and FIFO-read. Figure. show the various sampling modes. FIFO-Read MB FIFO ADC-FIFO TERN HOST CPU ADC-Read -bit ADC ADS Analog Input Figure. ADC Sampling Modes In ADC-read mode, application software running on the host can read the -bit ADC data at any time. Sampling rate would be limited to CPU and application processing speed. In ADC-FIFO mode, the GR can sample at far faster speeds (up to M samples per second). This data is recorded into the on-board FIFO SRAM. The ADC-FIFO operation is done entirely in hardware, without using any host CPU time. Finally, the system can be set to FIFO-read mode. The host CPU can then read as much FIFO data as desired via I/O or DMA access.

5 . ADC Sampling Frequency The ADC sampling clock can be driven by on-board clock oscillator, as default, or an external clock. With a 0MHz on-board oscillator, the sample rate is M samples per second maximum. User can control the sampling rate by using an external clock, or selecting different dividers using onboard jumpers (H). The default setting for H is H. = H. which is CLK/ or MHz sample rate. In order to change the default setting, the trace on H must be cut before wiring a new jumper. Figure. shows the H header and default trace jumper on the back of the GR. Table. the various sample rates for each H setting. H Figure. Frequency Divisor Jumper H Jumper Pins Clock Divisor Sample Rate for 0 MHz Oscillator H. (RDY) = H. (CKI) * DEFAULT * CLK / MHz H. (CK) = H. (CKI) CLK / MHz H.9 (CK) = H. (CKI) CLK /. MHz H. (CK) = H. (CKI) CLK /. MHz H. (CK) = H. (CKI) CLK / 9 khz Table. H Jumper Settings

6 . ADC-FIFO Operation The ADC-FIFO operation runs when signals SA=0 and TR is active *. The ADC-FIFO operation will stop immediately when SA=. Setting AST low causes the FIFO counter to reset. When AST=, SA=0 and TR is active * the GR continues filling up the FIFO with ADC readings until the selected recording length is reached forcing SA high (SA=). The record length of the FIFO can be configured via jumper block H. Available data lengths include MB (H. = H.), MB (H. = H.), or KB (H. = H.). The hardware trigger signal (TR) is routed to header locations H. and H.. By default H. and H. are jumpered (H.=H.=) forcing TR=0 *. It is important that the external hardware trigger signal (TR) must stay active while the GR is recording ADC readings. The FIFO will retain recorded data until it s powered-off or a new ADC-FIFO operation is initiated. To read data from the FIFO, reset the counter by bringing AST low then high, then read from the FIFO. Every FIFO-read increments FIFO address.. GR Stacks Multiple GR units can be stacked via pass through sockets on J and J. H pin =/PCS is the host I/O chip select. While H.=H.9, as default, the Host controller J.9 is the base I/O chip select. For each /PCS setting, there are GAL chips available: GRAB00, GRAB0, GRAB0, and GRABC0. Base I/O address are 0x00, 0x0, 0x0, and 0xC0 for these GALs. Stacked GR units can share a common external CK and SYNC signal on H header. With the CK inputs running, pulse the common shared SYNC line for the units to synchronize simultaneous conversions. Be aware that CK and SYNC signals are directly routed to ADS, with a voltage range of 0V-.V. Over voltage will damage ADS ADC.. GR-LM Version GR-LM version uses a different GAL set (GR-00, GR-0, GR-0, and GR-C0) that have an active high trigger TR. This version operates when TR=. By using an active high trigger, the SA output from one GR can trigger the TR signal of another GR allowing uninterrupted analog acquisition between GRs. By default, H. (TR) is not jumpered to at H. on the GR-LM version. * The original version of GR uses an active low (TR=0) trigger. The GR-LM version uses a different GAL that has an active high trigger. This version operates when TR=. GR-LM versions can be identified by the GAL labels: GR-00, GR-0, GR-0, and GR-C0.

7 . GR Photos Figure. Front view of a EL controller with GRs. Figure. Back view of an EL controller with GRs.

8 Figure. Side view of a EL controller with GRs. Figure. UD with GR TM

9 Figure. E-Engine with VE stacked on five GRs powered by 9-0V Figure. E-Engine with stacked on five GRs powered by external V

10 .9 Features. x. x 0. inches 00 ma at V DC power per GR High-Speed Delta-Sigma ADC (ADS) User Programmable Sample Rate, up to M SPS On-Chip Digital Filter Simplifies Anti-Alias User configurable FIFO data size, up to MB. Stackable multi units sharing Sync, and Trigger. On-board oscillator or external host clock. Driven by a -bit TERN controller Support ADC read, ADC-FIFO, FIFO-read modes Software programmable Power off mode controlled by PD signal.

11 . GR Physical Description The figure below shows the physical layout of the GR board. Step Jumper H TR, CK, SYNC and Sample Rate Divisor 0 MHz OSC Remove if using external CK H FIFO Size Ω Resistor A- to INN A+ to INP Analog Inputs A-, A+ (V-V) H. Chip Select /PCS = P H. Trigger = Host I/O GAL GRABC0 GRAB0 GRAB0 GRAB00 9

12 . GR-LM Physical Description The GR-LM version is the same hardware as the regular GR, but uses a different GAL set. The jumpers are set differently to accommodate the active high trigger TR. H FIFO Size MB H. (TR) Trigger is not jumpered to GAL GR-C0 GR-0 GR-0 GR-00

13 . GR Fifth Board Physical Description When stacking more than four GRs, a different chip select must be used to operate boards through. The image below shows the jumper setting for the th GR. H. Chip Select /PCS = /RTS

14 U SA SA SA A SA A SA A /RAM0 A A AD AD 9 D D AD D AD D AD D AD D AD /AD D S SA 9 A 0 SA A SA9 SA A SA SA SA SA SA /RAM A AD AD 9 AD AD AD AD AD /AD S SA 9 SA 0 SA9 SA RAM U A A A A D D D D D D D A A A RAM U SA A S SA SA A SA SA A A SA A /OE /RDF A /UB 0 SA A /RAM /LB 9 A D AD AD D AD AD 9 D D AD D D D AD AD D D D AD AD D D9 0 AD AD D D 9 AD9 AD D NC AD AD SA /AD A SA S 9 A A SA SA 0 A A A9 SA SA A A SA SA9 SA SA A A A /OE /UB 0 /LB 9 D D D D D D D9 0 D 9 NC A A A A9 A RAM U S SA SA SA SA SA A /RDF SA A A SA A /RAM AD A AD AD 9 D AD AD D AD AD D AD AD D AD AD D AD9 AD D AD AD SA /AD D SA S 9 A SA SA SA SA 0 A SA SA9 SA A SA V R0 V-V, ANALOG INPUT- V R V-V, ANALOG INPUT+ AV RBIAS R9 0K VCAP AV C VCAP CK V V V V0 V V C RAM U S SA A SA SA A SA SA A A /RDF SA A /OE A /UB 0 SA A /RAM /LB 9 AD A D AD AD D AD AD 9 D D D D D AD AD D D D AD AD D D9 0 AD AD D D 9 AD9 AD D NC AD AD SA /AD A SA 9 A A S SA 0 A SA A A9 SA SA A A SA SA9 SA SA A A A /OE /UB 0 /LB 9 D D D D D D D9 0 D 9 NC A A A A9 A H0 A- A+ 9 R R M V V V A A C A D D D D D D P P I R R C V G L G G V V G V V AG D E E A K NC V AV F F P N N NC AIN AG NC AIP AIN NC AIP D AD AG D AD V AV D AD RBIAS 9 BIAS D AD AG D 0 AD V AV D 9 AD AG D9 AD9 V AV D NC D AD REFEN M0 D AD M0 M S D AD M D AD NC Y O R P D D N C R T D D D AD D N N D D D D V D V G C S D R Y G V C C 0 C0 ADS ADS PD V V AD AD R SYNC RDY A V SYNC /ADL K U HDRD S SA SA /RDF SA SA SA SA SA /RAM AD AD A AD AD AD 9 AD AD AD AD AD AD AD9 AD AD AD SA /AD SA S SA SA 9 SA SA 0 SA SA9 SA SA AV V0 V V C C C9 C0 RAM U A A A A D D D D D D D A A A RAM H0 9 HDRD V V C C U S SA A SA SA A SA SA A A /RDF SA A /OE A /UB 0 SA A /RAM /LB 9 AD A D AD AD D AD AD 9 D D D D D AD AD D D D AD AD D D9 0 AD AD D D 9 AD9 AD D NC AD AD A SA /AD 9 A A SA S 0 A SA SA A A9 SA SA A A SA SA9 SA SA A A A /OE /UB 0 /LB 9 D D D D D D D9 0 D 9 NC A A A A9 A V C U GNG VO VO V=.V VI C V C UF BB K NC +V V CK CK CK CLK CK OS OS_SMT U Q Q Q Q Q Q Q Q Q9 Q RST Q CLK RDY Q 9 CK 00 V M0 S SA SA /RDF SA SA SA SA SA /RAM AD AD A AD AD AD 9 AD AD AD AD AD AD AD9 AD AD AD SA /AD SA S SA SA 9 SA SA 0 SA SA9 SA SA H00 9 C HDRD C RAM U9 A A A A D D D D D D D A A A RAM A- AIN AIP A+ REFEN M V V V V V C C C C C F V U R VA LM C CAPNP VA VA R R 0K 0K /AD PDN /ADL R R K K PD R R K K C9 V K C A A A /OE /UB 0 /LB 9 D D D D D D D9 0 D 9 NC A A A A9 A A A A /OE /UB 0 /LB 9 D D D D D D D9 0 D 9 NC A A A A9 A C S SA SA /RDF AD AD AD AD AD AD AD9 AD SA SA SA SA SA SA S SA SA /RDF AD AD AD AD AD AD AD9 AD SA SA SA SA SA SA V C0 0UF V V0 C UF C UF V0 V VA R 0K VA V VA V 9 I0- R 0K V U CLK RDY CK V 0 TR I O 9 I O /RDB A I O SA A I O I O /AD A I O /RDF /PCS 9 I O PDN /RD I O0 AST G /OE /RAM PALV AD-FF:/AD=0,/RDF=,PDN=,AST=0,/RDB=,TR=0 RD_FF:/AD=,/RDF=0,PDN=0,AST=0,/RDB=0 RD_AD:/AD=0,/RDF=,PDN=,AST=,/RDB=0 GRAB00.PDS BASE I/O 0X00 GRAB0.PDS BASE I/O 0X0 GRAB0.PDS BASE I/O 0X0 GRABC0.PDS BASE I/O 0XC0 CK CK RDY CK H TR SYNC CK RDY 9 CK HDRD J 0 9 P P CLK P /INT /RTS 9 D 0 9 D D D /RST D RST D /CTS P 9 0 D 0 9 D D D A D 9 0 A 9 /RD A D A D A D9 A D 9 0 HDR J HDR CK=ADC CLOCK, 0MHZ DEFAULT SYNC=MULTIPLE GR/ADS SYNC TR=EXTERNAL TRIGGER, ACTIVE LOW DEFAULT TRACE H. = H., M SPS CUT TRACE, WIRE H. = H., M SPS CUT TRACE, WIRE H. = H.,.M SPS H /RDB /AD /RDF RDY TR=EXTERNAL TRIGGER, ACTIVE LOW AST /RAM TR=H. = H.=, SOFTWARE START SAMPLE TR H.9 = H. = J.9 HOST SELECT P 9 /PCS H. = H. = J. HOST SELECT /CTS /RTS RDY=0: ADC DATA READY AST=: SAxx ADDRESS RESET HDRD P=J.9 HOST I/O SELECT /RTS=J. HOST I/O SELECT SA SA SA U SA9 A S SA B C /RAM AST LMC0 UA V0 LMC0 UB V LMC0 UC V RN K H G GA GB HDRD SA SA Y0 Y Y Y Y Y Y Y HC /PCS /RDB /AD /RDF TR AST /RAM 9 SA9 /RAM0 /RAM /RAM /RAM /RAM /RAM /RAM /RAM AIP R A+ AIN R A- AIN AIP C C PF PF H = FIFO SIZE SELECT H. = H., KB H. = H., MB H. = H., MB U AD AD9 A A AD AD A AD A AD A A AD A AD A /RDB 9 G G SA SA SA9 S SA SA Title HC Y Y Y Y Y 9 Y Y Y D D9 D D D D D D U Q SA SA S Q Q SA SA Q Q Q Q S SA SA SA Q Q9 Q RST SA Q CLK AST SA SA Q 9 SA 00 U9 A AD A A AD AD A AD A AD A A AD A AD A /RDB 9 G G STE/TERN HIGH SPEED -BIT ADC GRABBER Size Document Number B GRAB.SCH HC Y Y Y Y Y 9 Y Y Y D D D D D D D U 00 Q SA Q Q SA Q Q Q Q SA SA9 Q Q9 Q RST AST Q CLK /RAM Q 9 SA AST= SAxx=0 REV Date: June 9, 009 Sheet of

Grabber. Technical Manual

Grabber. Technical Manual Grabber 0 MHZ Analog Signal Digitizer Technical Manual 0 th Street, Davis, CA, USA Tel: 0--00 Fax: 0--0 Email: sales@tern.com http://www.tern.com COPYRIGHT Grabber, and A-Engine are trademarks of TERN,