RT Radiation Tolerant Multicell Battery Monitor

Transcription

1 FEATURES nn 5kRad (SI) Total Ionizing Dose (TID) per MIL- STD-883 TM09 Condition A n Single Event Effect (LET) Threshold Linear Energy Transfer (LET) 2.7MeV-cm 2 /mg n Processed Using MIL-PRF Class N and PEM-INST-00 as a Guideline n TID and SEE Reports Available n Measures Up to 2 Battery Cells in Series n Stackable Architecture Supports 00s of Cells n Built-In isospi Interface: Mbps Isolated Serial Communications Uses a Single Twisted Pair, Up to 00 Meters Low EMI Susceptibility and Emissions n.2mv Maximum Total Measurement Error n 290µs to Measure All Cells in a System n Synchronized Voltage and Current Measurement n 6-Bit Delta-Sigma ADC with Frequency Programmable 3rd Order Noise Filter n Engineered for ISO26262 Compliant Systems n Passive Cell Balancing with Programmable Timer Radiation Tolerant Multicell Battery Monitor DESCRIPTION The RT 6804 is a 3rd generation multicell battery stack monitor that measures up to 2 series connected battery cells with a total measurement error of less than.2mv. The cell measurement range of 0V to 5V makes the RT6804 suitable for most battery chemistries. All 2 cell voltages can be captured in 290µs, and lower data acquisition rates can be selected for high noise reduction. Multiple RT6804 devices can be connected in series, permitting simultaneous cell monitoring of long, high voltage battery strings. The RT6804 has an isospi interface for high speed, RF-immune, local area communications. Using the, multiple devices are connected in a daisy-chain with one host processor connection for all devices. Additional features include passive balancing for each cell, an on-board 5V regulator, and 5 general purpose I/O lines. In sleep mode, current consumption is reduced to 4µA. The RT6804 can be powered directly from the battery, or from an isolated supply. All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including , , TYPICAL APPLICATION 2SP IPB IMB IPA ILP IMA IPB IMB IPA IMA IPB IMB IPA MPU SPI IP LTC6820 MEASUREMENT ERROR (mv) Total Measurement Error vs Temperature of 5 Typical Units CELL VOLTAGE = 3.3V 5 TYPICAL UNITS TEMPERATURE ( C) TA0b IMA IM 6804 TA0a Document Feedback

2 ABSOLUTE MAXIMUM RATINGS (Note ) Total Supply Voltage V to V...75V Input Voltage (Relative to V ) C V to 0.3V C V to 75V C(n) V to MIN (8 n, 75V) S(n) V to MIN (8 n, 75V) IPA, IMA, IPB, IMB V to V REG 0.3V DRIVE Pin V to 7V All Other Pins V to 6V Voltage Between Inputs V to C V C(n) to C(n ) V to 8V S(n) to C(n ) V to 8V C2 to C V to 25V C8 to C V to 25V C4 to C V to 25V Current In/Out of Pins All Pins Except V REG, IPA, IMA, IPB, IMB, S(n)...0mA IPA, IMA, IPB, IMB...30mA Operating Temperature Range RT6804H C to 25 C Specified Temperature Range RT6804H C to 25 C Junction Temperature C Storage Temperature C to 50 C Lead Temperature (Soldering, 0sec) C PIN CONFIGURATION V C2 S2 C S C0 S0 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C TOP VIEW G PACKAGE 48-LEAD PLASTIC SSOP T JMAX = 50 C, θ JA = 55 C/W *THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD ISOMD TIED TO V : CSB, SCK, SDI, SDO ISOMD TIED TO V REG : IMA, IPA, NC, NC **THIS PIN MUST BE CONNECTED TO V IPB IMB ICMP IBIAS SDO (NC)* SDI (NC)* SCK (IPA)* CSB (IMA)* ISOMD WDT DRIVE V REG SWTEN V REF V REF2 GPIO5 GPIO4 V V ** GPIO3 GPIO2 GPIO C0 S ORDER INFORMATION LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE RT6804HG- RT6804HG-#TR RT6804G- 48-Lead Plastic SSOP 40 C to 25 C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2

3 ELECTRICAL CHARACTERISTICS (Pre-Irradiation) Specifications are at T A = 25 C. The test conditions are V = 39.6V, V REG = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS ADC DC Specifications I L Total Measurement Error (TME) in Normal Mode Total Measurement Error (TME) in Filtered Mode Input Leakage Current When Inputs Are Not Being Measured Voltage Reference Specifications T A = 25 C SUB- 40 C T A 25 C MIN TYP MAX GROUP MIN TYP MAX SUB- GROUP UNITS C(n) to C(n-) = ± , 3 mv GPIO(n) to V = , 3 mv C(n) to C(n-) = ± , 3 mv GPIO(n) to V = , 3 mv C(n) to C(n-) = ± , 3 mv GPIO(n) to V = , 3 mv VREG Pin 0.25 ± ± , 3 % VREG Pin 0.25 ± ± , 3 % C(n), n = 0 to , 3 na GPIO(n), n = to , 3 na V REF st Reference Voltage VREF Pin, No Load , 3 V V REF2 2nd Reference Voltage VREF2 Pin, No Load V General DC Specifications I VP V Supply Current State: Core = SLEEP, isospi = IDLE V REG = 0V µa V REG = 5V µa State: Core = STANDBY , 3 µa State: Core = REFUP or MEASURE , 3 ma I REG(CORE) V REG Supply Current State: Core = SLEEP, isospi = IDLE V REG = 5V µa State: Core = STANDBY , 3 µa State: Core = REFUP , 3 ma State: Core = MEASURE , 3 ma DRIVE output Voltage Sourcing µa , 3 V Discharge Switch ON Resistance SPI Interface DC Specifications V CELL = 3.6V Ω I LEAK(DIG) Digital Input Current Pins CSB, SCK, SDI,ISOMD, SWTEN, A0 to A3 isospi DC Specifications 2, 3 µa V BIAS Voltage on IBIAS Pin READY/ACTIVE State , 3 V A IB Isolated Interface Current Gain isospi Pulse Timing Specifications V A.6V I B = ma , 3 ma/ ma t /2PW(D) Data Half-Pulse Width , 6 ns 3

4 ELECTRICAL CHARACTERISTICS (Post-Irradiation) Specifications are at T A = 25 C. The test conditions are V = 39.6V, V REG = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS ADC DC Specifications I L Total Measurement Error (TME) in Normal Mode Total Measurement Error (TME) in Filtered Mode Input Leakage Current When Inputs Are Not Being Measured Voltage Reference Specifications 0kRad (SI) 5kRad (SI) MIN MAX MIN MAX UNITS C(n) to C(n-) = mv GPIO(n) to V = mv C(n) to C(n-) = mv GPIO(n) to V = mv C(n) to C(n-) = mv GPIO(n) to V = mv VREG Pin mv VREG Pin mv C(n), n = 0 to na GPIO(n), n = to na V REF st Reference Voltage VREF Pin, No Load V V REF2 2nd Reference Voltage VREF2 Pin, No Load V General DC Specifications I VP V Supply Current State: Core = SLEEP, isospi = IDLE V REG = 0V µa V REG = 5V µa State: Core = STANDBY µa State: Core = REFUP or MEASURE ma I REG(CORE) V REG Supply Current State: Core = SLEEP, isospi = IDLE V REG = 5V µa State: Core = STANDBY µa State: Core = REFUP ma State: Core = MEASURE ma DRIVE Output Voltage Sourcing µa V Discharge Switch ON Resistance V CELL = 3.6V Ω SPI Interface DC Specifications I LEAK(DIG) Digital Input Current Pins CSB, SCK, SDI,ISOMD, SWTEN, A0 to A µa isospi DC Specifications V BIAS Voltage on IBIAS Pin READY/ACTIVE State V A IB Isolated Interface Current Gain V A.6V I B = ma ma/ma isospi Pulse Timing Specifications t /2PW(D) Data Half-Pulse Width ns 4

5 ELECTRICAL CHARACTERISTICS: BURN-IN DELTA PARAMETERS Specifications are at T A = 25 C. SYMBOL PARAMETER CONDITIONS DELTA LIMITS V REF st Reference Voltage VREF Pin, No Load 5 5 mv V REF2 2nd Reference Voltage VREF2 Pin, No Load 5 5 mv I VP V Supply Current State: Core = STANDBY µa Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. MIN MAX UNITS Note 2: The ADC specifications are guaranteed by the Total Measurement Error specification. Note 3: V needs to be greater than or equal to the highest C(n) voltage for accurate measurements. 5

6 ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUP Final Electrical Test Requirements (Method 5004) *,2,3,4,5,6 Group A Test Requirements (Method 5005),2,3,4,5,6 Group B and D for Class S, and End Point Electrical Parameters (Method 5005) *PDA applies to subgroup. See PDA Test Notes.,2,3 PDA Test Notes The PDA is specified as 5% based on failures from group A, subgroup, tests after cooldown as the final electrical test in accordance with method 5004 of MIL-STD-883. The verified failures of group A, subgroup, after burn-in divided by the total number of devices submitted for burn-in in that lot shall be used to determine the percent for the lot. Analog Devices reserves the right to test to tighter limits than those given. 6

7 TOTAL DOSE BIAS CIRCUIT/BURN-IN CIRCUIT V MONITOR V PWR CHt F k W V IPB 48 00k k k 0k 0k C2 S2 C S IMB ICMP IBIAS NC Ω 4.99k 4.99k 4.99k 4.99k 0k 6 7 C0 S0 NC IPA k 8 C9 IMA 4 0k 9 0 S9 C8 ISOMD WDT k 499Ω W 0k S8 DRIVE 38 2N C7 V REG 37 N5550 0k 3 S7 SWTEN 36 µf 6V X7R 4 C6 V REF 35 µf 6V X7R 0k 5 S6 V REF C5 GPIO5 33 0k 7 S5 GPIO C4 V 3 0k 9 S4 V C3 GPIO3 29 0k 2 S3 GPIO C2 GPIO 27 0k 23 S2 C0 26 0k 24 C S 25 µf 6V X7R 6.8V W GROUND PWR GROUND MONITOR RT6804 BD 7

8 TYPICAL PERFORMANCE CHARACTERISTICS TME in Normal Mode C(n) to C(n-) =2V TME in Normal Mode C(n) to C(n-) = 3.3V TME in Normal Mode C(n) to C(n-) = 4.2V TME (mv) 00 0 C() C(2) C(3) C(4) C(5) C(6) C(7) C(8) C(9) C(0) C() C(2) TME (mv) 00 0 C() C(2) C(3) C(4) C(5) C(6) C(7) C(8) C(9) C(0) C() C(2) TME (mv) 00 0 C() C(2) C(3) C(4) C(5) C(6) C(7) C(8) C(9) C(0) C() C(2) RT6804 G RT6804 G RT6804 G Reference Voltage 2, V REF2, V REG = 5V 3.30 Reference Voltage, V REF, V REG = 5V V REF2 (V) V REF (V) RT6804 G RT6804 G05 8

9 TYPICAL PERFORMANCE CHARACTERISTICS IREG (ma) IREG, Core = MEASURE RT6804 G06 IREG (µa) IREG, Core = STANDBY 00k 0k k RT6804 G07 IREG (µa) IREG Core = SLEEP, V REG = 5V RT6804 G IVP, Core = MEASURE 0k IVP, Core = STANDBY 0k IVP, Core = SLEEP, V REG = 0V 4.5 IVP (ma) IVP (µa) k 00 IVP (µa) k RT6804 G RT6804 G RT6804 G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted more by information implication or otherwise under any patent or patent rights of Analog Devices. 9

10 PACKAGE DESCRIPTION G Package 48-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # Rev A).25 ± * ( ) ( ) 0.25 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.50 BSC * (.97.22) ( ) 2.0 (.079) MAX PARTING LINE ( ) ** ( ).25 (.0492) REF NOTE:.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSIONS ARE IN MILLIMETERS (INCHES) DRAWING NOT TO SCALE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE 0.50 (.0968) BSC ( ) TYP * DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED.5mm PER SIDE ** LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED 0.3mm PER SIDE 0.05 (.002) MIN SEATING PLANE G48 (SSOP) 084 REV A 0 03/9 ANALOG DEVICES, INC. 209