A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load

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1 A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1

2 Outline Introduction of LDO Regulator Multi-gain Stages in Output Capacitorless (OCL-LDO) regulator Negative Current Feedback (NCF) Technique Weighted Current Feedback (WCF) Technique Circuit Implementation of WCF LDO regulator Results and Discussions Conclusion

3 Introduction of LDO regulator Widely used due to its simple structure, fast response and low noise characteristics. Output capacitorless LDO (OCL-LDO) regulator eliminates the large output capacitor and support fully onchip applications. For large scale digital circuits, the effective supply line parasitic capacitance is large. The regulator needs to drive a wide range of load capacitance (C L ) with fast transient response.

4 Multi-gain Stages in a LDO Regulator Frequency Compensation V REF 1 st stage g m1 N 1 (V 1 ) p -3dB R 1 C 1 N 2 (V 2 ) N P (V P ) N O (V OUT ) p 2 p 3 p 2 nd stage 3 rd stage M P O -g m2 -g -g mp m3 R 2 1/g m C 2 R P C P Power T. R O C L Feedback Network 1. N 2 is low impedance node and N P is high impedance node. 2. p 3 and p O are low, limiting the stability at light I L. 3. Speed at node N P is small due to limited quiescent bias current in 3 rd stage.

5 Negative Current Feedback Technique Frequency Compensation V REF N 1 (V 1 ) p -3dB 1 st stage g m1 R 1 C 1 N 2 (V 2 ) p 2f 2 nd stage -g m2 3 rd stage N P (V P ) p 3 M P -g m3 -g mp N O (V OUT ) p O R 2 C 2 NCF Loop R P C P R P (1/g m ) Power T. R O C L g mf V P Current Sensor (+g mf ) Feedback Network 1. N P is low impedance node and N 2 is high impedance node rd stage is adaptively biased leading to a high speed. 3. Large R 2 and large C P results in two low frequency parasitic poles. 4. Negative feedback technique to reduce R 2.

6 Negative Current Feedback Technique Frequency Compensation V REF N 1 (V 1 ) p -3dB 1 st stage g m1 R 1 C 1 N 2 (V 2 ) p 2f 2 nd stage -g m2 3 rd stage N P (V P ) p 3 M P -g m3 -g mp N O (V OUT ) p O R 2 C 2 NCF Loop R P C P R P (1/g m ) Power T. R O C L g mf V P Current Sensor (+g mf ) Feedback Network 1. Negative feedback current reduce R 2 thus reduce the loop gain of the regulator as well. The regulation accuracy is degraded. 2. The charging/discharging rate at node N 2 is also reduced.

7 Weighted Current Feedback Technique: Operation WCF (+g mf ) Frequency Compensation V REF 1 st stage +g m1 N 1 (V 1 ) N 2 2 nd stage (V 2 ) 3 rd stage N P -g m2 -g m3 N P (V P ) Power T. M P (-g mp ) N O (V OUT ) 2 nd stage 3 rd stage V DD R L C L N 1 M 2 R X M d1 S M a1 B M a2 N P R P Overshoot Reduction R 2 N 2 M 3 WCF Loop I a1 M a3 I a2 V B M b1 M a5 M a4 Weighted Current Feedback (WCF) v fbin v fbout

8 Weighted Current Feedback Technique: Operation V DD V DD V DD N 1 M 2 R X Md1 S M a1 B M a2 N 1 M 2 R X Md1 S M a1 B M a2 N 1 M 2 R X Md1 S M a1 B M a2 N 2 M 3 I a1 M a3 I a2 N 2 M 3 I a1 M a3 I a2 N 2 M 3 I a1 M a3 I a2 V B V B V B M b1 M a5 M a4 WCF M b1 M a5 M a4 WCF M b1 M a5 M a4 WCF (a) (b) (c) 1. At low I L, both M a1 and M a2 are weakly biased. Feedback is small. 2. At moderate I L, both M a1 and M a2 are in saturation region. Feedback is strong. 3. At high I L, M a2 is forced to work in linear region by M a3 and M a4. Feedback is reduced.

9 Weighted Current Feedback Technique: Why it works? Frequency Compensation V REF N 1 (V 1 ) 1 st stage p -3dB g m1 R 1 C 1 N 2 (V 2 ) p 2f 2 nd stage -g m2 3 rd stage N P (V P ) p 3 M P -g m3 -g mp N O (V OUT ) p O R 2 C 2 WCF Loop R P C P R P (1/g m ) Power T. R O C L g mf V P Current Sensor (+g mf ) Feedback Network At low I L, R O is large, C L R O forms the dominant pole. ω UGF is small. Feedback can be small to achieve stability. At moderate I L, loop gain is large. R 2 and R P are moderate. A strong feedback is required to reduce R 2 and the loop gain. At high I L, R P is small. R 2 is also small due to a large bias current introduced by the WCF circuit. The feedback can be reduced.

10 WCF loaded Output Impedance & Feedback Factor 1. R 2f (feedback loaded impedance at node N 2 ) is significantly reduced at moderate and high I L. 2. The feedback (β is the feedback factor) is strong at moderate I L and weak at both low and high I L.

11 Parameters of WCF Regulator Case I: Large C L R O Case II: Moderate C L R O Case III: Small C L R O Parameter Low I L Moderate I L High I L Feedback Weak Strong Weak gm3gmf R2RP 1 g g g g R R R R A m1 m2 m3 mp 1 2 P O DC z 1 mc c 3dB Due to the WCF technique, p 4,5 f can be pushed to a higher frequency. The stability can be achieved. g p 1 CR L O 1 2CR L O 2,3 f C Cc gm2gm3gmpr1 R2RP RO p g mc Cc CPgmcRP CmR 1 2g mc Cc CPgmcRP CmR 1 gm2gm3gmpgmcr2 RP CmCL p Cc CPgmcRP CcC2CPR2R P C2CPR2R P 4,5 f Q Cc CPgmcRP Cmgmc R1 2Cc CPgmcRP CmgmcR1 p 2,3 f p 4,5 f CLgmc Cmgm2gm3gmpR2 RP Q Cc CPgmcRP C2R 2 CcCPRP C2R2 CPRP gm 1gm2gm3gmpR1 R2RP CL UGF m1 2 c g C gm 1 C c

12 X. L. Tan, S. S. Chong, P. K. Chan, and U. Dasgupta, A LDO Regulator with Weighted Current Feedback Technique for 0.47 nf- 10 nf Capacitive Load IEEE J. Solid-State Circuits, vol. 49, no. 11, Nov Circuit of WCF Regulator V DD M 3 M 4 M 9 R X S B N P M 12 M a1 M a2 M P C c V OUT V B M 1 M 2 M 0 V REF M 5 M 6 C m N 1 N 0 M 7 M 8 M 10 N 2 M 11 M a3 M a5 M a4 M 13 C B R B C L V B R L Weighted Current Feedback (WCF) Block 1 st Gain Stage 2 nd and 3 rd Gain Stage WCF, Power transistor, overshoot reduction, and output stage

13 Loop Gain and Phase Responses (a) (b) Stable for C L = 470 pf and 10 nf. Minimum PM = 45 o, Minimum GM = 11 db.

14 Microphotograph 76µm Start-up Cap Bias Gen. 150 µm C c +C m Control Circuit Power Transistor 120µm 16µm Area = mm 2

15 Measured Transient Responses 0 100ns 50mA 100ns 0 100ns 50mA 100ns C L = 470pF C L = 1nF 29mV 29mV 113mV 1µs 50mV 109mV 1µs 50mV (a) (b) 50mA 50mA 0 100ns 100ns 0 100ns 100ns C L = 3.3nF C L = 10nF 27mV 32mV 98mV 1µs 72mV 1µs 50mV 50mV (c) (d)

16 Performance Comparison Parameter JSSC 2005 no. 4 TCAS-I 2007 no.9 JSSC 2010 no. 2 JSSC 2010 no. 9 TCAS-I 2012 no. 5 TCAS-II 2012 no. 1 TCAS-I 2012 no. 9 TCAS-I 2013 no. 4 TCAS-II 2013 no. 6 Technology (μm) JSSC 2014 no. 11 Chip Area (mm 2 ) V IN (V) V OUT (V) Dropout Voltage (mv) I Q (μa) * I OUT (max) (ma) Total On-Chip Cap. (pf) Load Cap. Range (F) 600p 0-100p 0, 100p, 1n 0-50p 0-100p 0-100p 0-1n 0-100p 40p 470p-10n Line Reg. (mv/v) N/A 23 N/A N/A Load Reg. (mv/ma) N/A (db) N/A -57 N/A N/A N/A -58(@10kHz) N/A -51 Settling Time (μs) N/A N/A ~0.15 ~ I L(min) (ma) ΔI OUT (ma) ΔV OUT (mv) Edge Time (μs) Edge Time Ratio K FOM * Quiescent current includes the current consumption of bias circuit. The minimum I L used to test the transient performance.

17 Conclusion 1. A weighted current feedback technique is proposed in OCL- LDO Regulator. 2. Due to the smart control of the output impedance of the inter gain stage, the regulator can achieve a good stability, fast speed and high accuracy. 3. The comparison results have shown the WCF LDO regulator achieves a comparable or better FOM with respect to other reported designs whilst achieving wide range of C L driving ability.

18 Acknowledgment Thank MediaTek for the sponsorship of scholarship as well as the chip fabrication

Homework Assignment 08

Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance