Experimental Verification of a Timing Measurement Circuit With Self-Calibration

Transcription

1 19 th IEEE IMS3TW, Porto Alegre, Brazil Sept. 17, 2014 Experimental Verification of a Timing Measurement Circuit With Self-Calibration Kateshi Chujyo, Daiki Hirabayashi, Kentaroh Katoh Conbing Li, Yutaroh Kobayashi, Koshi Sato Haruo Kobayashi Gunma University, Tsuruoka National College of Tech Hikari Science Supported by STARC Gunma University Kobayashi Lab 1

2 Outline Research Background TDC Circuit and Problems Histogram Method Self-Calibration Analog FPGA Implementation Measurement Results Conclusions 2

3 Outline Research Background TDC Circuit and Problems Histogram Method Self-Calibration Analog FPGA Implementation Measurement Results Conclusions 3

4 Research Background Advanced CMOS VLSI Voltage domain Low power-supply voltages Fast switching speeds Time domain Supply voltage Fine CMOS time Fine CMOS time A Time-to-Digital Converter (TDC) provides a digital output proportional to the time between two clock transitions. The TDC is a key component in time-domain analog circuits, (e.g. Sensor Interfaces, All-Digital PLLs, ADCs,.. ) 4

5 Research Objective Validate TDC linearity self-calibration with histogram method All-digital implementation Suitable for fine CMOS Experimentally validate design with FPGA 5

6 Outline Research Background TDC Circuit and Problems Histogram Method Self-Calibration Analog FPGA Implementation Measurement Results Conclusions 6

7 Flash-type TDC T Dout=2 Digital output (Dout) proportional to time difference between rising edges (T) Time resolution τ START STOP τ τ τ τ τ τ T D 0 = 1 D 1 = 1 D 2 = 0 D 3 = 0 Dout=1 7

8 Delay Cell Variation Inside TDC Circuit Delay cell variation Δτk t t t t t +Dt 1 +Dt 2 +Dt 3 +Dt 4 +Dt 5 D Q D Q D Q D Q TDC nonlinearity D1 D2 D3 D4 T (a) Without delay variation T (b) With delay variation 8

9 Random Variation among Delay Cells Delay τ variation Relative variation TDC nonlinearity Absolute(average value) variation TDC input range & time resolution Focus on Relative variation here. 9

10 Outline Research Background TDC Circuit and Problems Histogram Method Self-Calibration Analog FPGA Implementation Measurement Results Conclusions 10

11 Research Objective (revisited) TDC linearity self-calibration with histogram Dout(0)=1 Dout(1)=3 Dout(2)=5 Dout(3)=8 Calibration Dout(0)=0.3 Dout(1)=2.8 Dout(2)=4.5 Dout(3)=7.3 Corrected based on delay variation evaluation Analog FPGA(PSoC) implementation, evaluation 11

12 TDC with Self-Calibration 24 START M U X t 1 t 2 t 3 t 4 t 23 t 24 Test mode 0 or 1 D Q D Q D Q D Q D Q D Q D Q STOP Encoder Dout Histogram Engine To histogram database 12

13 Normal Operation Mode START M U X t 1 t 2 t 3 t 4 t 23 t 24 Test mode 0 or 1 D Q D Q D Q D Q D Q D Q D Q STOP Encoder Dout 13

14 Self-Calibration Mode START f 1 M U X t 1 t 2 Ring oscillator t 3 t 4 t 23 t 24 Test mode 0 or 1 D Q D Q D Q D Q D Q D Q D Q STOP f 2 External clock Encoder Histogram Engine To histogram database 14

15 # of 1 output Self-Calibration Self-calibration mode START, STOP signals are NOT synchronized Code Histogram data in all bins will be equal, after collection of a sufficiently large number of data, if the TDC has perfect linearity 15

16 Principle of TDC Linearity Calibration START (ring oscillator) and STOP signals are asynchronous. f 1 START M U X t 1 t 2 t 3 t 4 t 23 t 24 Test mode 0 or 1 D Q D Q D Q D Q D Q D Q D Q STOP Probability of digital code for large delay is high. Probability of digital code for small delay is low. 16

17 Self-Calibration Histogram TDC is non-linear delay t Dt 2 t Dt 3 t Dt 4 t Dt 1 D Q D Q D Q Dt 2 Dt 3 Dt 5 Each bin of histogram t Dt 4 Varies with corresponding delay value TDC digital output 17

18 Principle of Self-Calibration 1 Histogram 2 n Nonlinear TDC INL calculation 3 n TDC digital output Dout f (T) 4 Histogram Histogram of ideally T Linearized by inverse function Linear TDC T 18 TDC digital output

19 # of 1 output # of 1 output Simulation Result of Self-Calibration 2.5 x 106 before calibration 2.5 x 106 after calibration MATLAB code Sampling points 28,848,432 t1 60~69ps t 2 10ns code Histogram for each bin is the same when the TDC is linear. 19

20 Outline Research Background TDC Circuit and Problems Histogram Method Self-Calibration Analog FPGA Implementation Measurement Results Conclusions 20

21 Implementation of TDC with Self-Calibration Programmable System-on-Chip (PSoC) 5LP and external components Variable capacitor array for individual cell delays Capacitor and var. resistor for loop (ring) delay 21

22 TDC Control Circuit in PSoC Generation of START, STOP signals for test purpose Reference clock PWM for self-calibration stop signal Control register for control mode change 22

23 START, STOP Generation for TDC Evaluation 48MHz reference clock inside PSoC CLKref 48MHz Reference Clock Program control Divide reference clock Timing difference of N x 20.8ns Divided clock (48/N) MHz Precise timing signal generation N x 20.8ns START STOP START STOP Use for TDC linearity evaluation

24 TDC and Ring Oscillator Circuit To encoder Each delay 5.6kΩ 0~120pF To encoder To encoder 24

25 Encoder Circuit Thermometer code to binary code Thermometer code Detection of transition from 1 to 0 Encode to binary code 25

26 Data Processing Software C program Data were transferred via USB to a PC and processed there. 26

27 Outline Research Background TDC Circuit and Problem Histogram Method Self-Calibration Analog FPGA Implementation Measurement Results Conclusions 27

28 Histogram in Calibration Mode Histogram 2,500 Histogram data for experiment 2,000 1,500 1, Bin Sample #1 Total number of data: Average number of data for each bin:

29 TDC Measurement Without Calibration TDC Digital Output Non-linearity 系列 1 Sample # ,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000 START, STOP Rising Edge Timing Difference [ns] 29

30 Actual Delay Data by Direct Measurement [ns] Sample #1 Delay Value Delay Cell 30

31 誤差 (%) Correlation Between Histogram and Delay Histogram and Delay Measurement Results Delay Cell Error between Delay and Histogram (%) 13% Delay Histogram Delay Cell 31

32 TDC Characteristics Before and After Calibration Digital output Sample #1 [ns] Time difference between two clock rising edges 32

33 INL Before and After Calibration (1) INL Sample #1 INL after calibration 57.5% INL before calibration % TDC digital output code

34 INL Before and After Calibration (2) Sample #2 Sample #3 Sample #4 Sample #5 34

35 Outline Research Background TDC Circuit and Problem Histogram Method Self-Calibration Analog FPGA Implementation Measurement Results Conclusions 35

36 Conclusion A TDC with self-calibration was implemented using an analog FPGA. Measurement results showed Linearity improved by self-calibration. All-digital implementation is possible. Suitable for fine CMOS BOST for timing signal test 36

37 Altera FPGA (Full digital Implementation) TDC with histogram method self-calibration Delay cell array was implemented with a CMOS inverter chain. 37

38 INL INL Before and After Self-Calibration Measurement results Before calibration After calibration TDC digital output code 38

39 19 th IEEE IMS3TW, Porto Alegre, Brazil Sept. 17, 2014 Thank you for kind attention Time continues indefinitely. We are analog design & test researchers, but we appreciate digital technology. Gunma University Kobayashi Lab 39

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