HCF4035B 4 STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER
|
|
|
- Nancy Young
- 6 years ago
- Views:
Transcription
1 4 STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER 4 STAGE CLOCKED SHIFT OPERATION SYNCHRONOUS PARALLEL ENTRY ON ALL 4 STAGES JK INPUTS ON FIRST STAGE ASYNCHRONOUS TRUE/COMPLEMENT CONTROL ON ALL OUTPUTS STATIC FLIP-FLOP OPERATION; MASTER-SLAVE CONFIGURATION BUFFERED INPUTS AND OUTPUTS HIGH SPEED 12MHz (Typ.) at V DD = 10V QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I I = 100nA (MAX) AT V DD = 18V T A = 25 C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4035B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is a four stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK logic. Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial PIN CONNECTION DIP ORDER CODES SOP PACKAGE TUBE T & R DIP HCF4035BEY SOP HCF4035BM1 HCF4035M013TR mode (PARALLEL/SERIAL control low). Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high. In the parallel or serial mode information is transferred on positive clock transitions. When the TRUE/ COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. The TRUE/ COMPLEMENT control functions asynchronously with respect to the CLOCK signal. JK input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence generation applications. With JK inputs connected together, the first stage becomes a D flip-flop. An asynchronous common RESET is also provided. September /11
2 IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 9, 10, 11, 12 PI-1 to PI-4 Parallel Inputs 1, 15, 14, 13 Q1/Q1 to Q4/ Q4 True/Complement Outputs 5 RESET Reset Input 4, 3 J, K Serial Inputs 6 CLOCK Clock Input 7 P/S Parallel/Serial Control 2 T/C True/Complement Control 8 V SS Negative Supply Voltage 16 V DD Positive Supply Voltage FUNCTIONAL DIAGRAM TRUTH TABLE CLOCK t n-1 (Inputs) t n (Outputs) J K R Q n-1 Q n L X L L L H X L L H X L L H L H L L Q n-1 Qn-1 Toggle Mode X H L H H X X L Q n-1 Q n-1 X : Don t Care X X X H X L 2/11
3 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DD Supply Voltage -0.5 to +22 V V I DC Input Voltage -0.5 to V DD V I I DC Input Current ± 10 ma P D Power Dissipation per Package 200 mw Power Dissipation per Output Transistor 100 mw T op Operating Temperature -55 to +125 C T stg Storage Temperature -65 to +150 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to V SS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V DD Supply Voltage 3 to 20 V V I Input Voltage 0 to V DD V T op Operating Temperature -55 to 125 C 3/11
4 DC SPECIFICATIONS Test Condition Value Symbol Parameter V I (V) V O (V) I O (µa) V DD (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max. Unit I L Quiescent Current 0/ / / / V OH High Level Output 0/5 < Voltage 0/10 < /15 < V OL V IH V IL I OH I OL Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current 5/0 < /0 < /0 < /4.5 < /9 < /13.5 < /0.5 < /1 < /1.5 < /5 2.5 < /5 4.6 < / < / < /5 0.4 < / < / < I I Input Leakage 0/18 Any Input 18 Current ±10-5 ±0.1 ±1 ±1 µa C I Input Capacitance Any Input pf The Noise Margin for both "1" and "0" level is: 1V min. with V DD =5V, 2V min. with V DD =10V, 2.5V min. with V DD =15V µa V V V V ma ma 4/11
5 DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25 C, C L = 50pF, R L = 200KΩ, t r = t f = 20 ns) Test Condition Value (*) Unit Symbol Parameter V DD (V) Min. Typ. Max. CLOCKED OPERATION t PLH t PHL Propagation Delay Time ns t THL t TLH Transition Time ns f Maximum Clock Input MAX Frequency MHz t W Clock Pulse Width ns t r, t Clock Input Rise or Fall 5 15 f Time µs t setup Data Setup Time J/K lines ns t setup Data Setup Time Parallel In Lines ns RESET OPERATION t PLH t PHL Propagation Delay Time ns t W Reset Pulse Width ns (*) Typical temperature coefficient for all V DD value is 0.3 %/ C. 5/11
6 TYPICAL APPLICATIONS Binary To BCD Converter Bidec Logic 6/11
7 DOUBLE SEQUENCE GENERATOR STATE SEQUENCES Using a control line (E) two different state sequences can be generated. For example, suppose the following two sequences are desiderated on command (control line E) Control = E = 0 1 Q 1 Q 2 Q 3 Q 4 Q 1 Q 2 Q 3 Q 4 A B C D A B C D SHIFT LEFT/SHIFT RIGHT REGISTER 7/11
8 TEST CIRCUIT C L = 50pF or equivalent (includes jig and probe capacitance) R L = 200KΩ R T = Z OUT of pulse generator (typically 50Ω) 8/11
9 Plastic DIP-16 (0.25) MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. a B b b D E e e F I L Z P001C 9/11
10 SO-16 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A a a b b C c1 45 (typ.) D E e e F G L M S 8 (max.) PO13H 10/11
11 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom 11/11
Obsolete Product(s) - Obsolete Product(s)
DUAL BINARY TO 1 OF 4 DECODER/DEMULTIPLEXER OUTPUT LOW ON SELECT EXPANDABLE WITH MULTIPLE PACKAGES STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V
HCF4555B DUAL BINARY TO 1 OF 4 DECODER/DEMULTIPLEXER OUTPUT HIGH ON SELECT
DUAL BINARY TO 1 OF 4 DECODER/DEMULTIPLEXER OUTPUT HIGH ON SELECT EXPANDABLE WITH MULTIPLE PACKAGES STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V
HCF4532B 8-BIT PRIORITY ENCODER
8-BIT PRIORITY ENCODER CONVERTS FROM 1 TO 8 TO INPUTS BINARY PROVIDES CASCADING FEATURE TO HANDLE ANY NUMBER OF INPUTS GROUP SELECT INDICATES ONE OR MORE PRIORITY INPUTS QUIESCENT CURRENT SPECIFIED UP
Obsolete Product(s) - Obsolete Product(s)
8-BIT PRIORITY ENCODER CONVERTS FROM 1 TO 8 TO INPUTS BINARY PROVIDES CASCADING FEATURE TO HANDLE ANY NUMBER OF INPUTS GROUP SELECT INDICATES ONE OR MORE PRIORITY INPUTS QUIESCENT CURRENT SPECIFIED UP
HCF4089B BINARY RATE MULTIPLIER
BINARY RATE MULTIPLIER CASCADABLE IN MULTIPLES OF 4-BITS SET TO "15" INPUT AND "15" DETECT OUTPUT QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC
HCF4543B BCD-TO-7-SEGMENT LATCH/DECODER/LCD DRIVER
BCD-TO-7-SEGMENT LATCH/DECODER/LCD DRIVER DISPLAY BLANKING OF ALL ILLEGAL INPUT COMBINATIONS LATCH STORAGE OF CODE INSTRUMENT DISPLAY DRIVER DASHBOARD DISPLAY DRIVER COMPUTER/CALCULATOR DISPLAY DRIVER
M74HCT138TTR 3 TO 8 LINE DECODER (INVERTING)
3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t PD = 16ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
Obsolete Product(s) - Obsolete Product(s)
3 TO 8 LINE DECODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
M74HCT688TTR 8 BIT EQUALITY COMPARATOR
8 BIT EQUALITY COMPARATOR HIGH SPEED: t PD = 21ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
M74HC147TTR 10 TO 4 LINE PRIORITY ENCODER
10 TO 4 LINE PRIORITY ENCODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
Obsolete Product(s) - Obsolete Product(s)
8-INPUT NAND GATE HIGH SPEED: t PD = 13ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: I
M74HC20TTR DUAL 4-INPUT NAND GATE
DUAL 4-INPUT NAND GATE HIGH SPEED: t PD = 9ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
Obsolete Product(s) - Obsolete Product(s)
BCD TO DECIMAL DECODER HIGH SPEED : t PD = 14ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
Obsolete Product(s) - Obsolete Product(s)
DUAL 4 CHANNEL MULTIPLEXER 3 STATE OUTPUT HIGH SPEED: t PD = 16ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
.SET-RESET CAPABILITY
DUAL D TYPE FLIP FLOP.SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEEL EITHER HIGH OR LOW MEDIUM-SPEED OPERATION - 16MHz (typ.) CLOCK TOGGLE RATE AT 10 QUIESCENT
HCC/HCF4042B QUAD CLOCKED D LATCH
QUAD CLOCKED D LATCH CLOCK POLARITY CONTROL Q AND Q OUTPUTS COMMON CLOCK LOW POWER TTL COMPATIBLE STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED TO 20 FOR HCC DEICE 5, 10,
M74HC4543TTR BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER
BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER HIGH SPEED: t PD = 14 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
HCC/HCF40181B 4-BIT ARITHMETIC LOGIC UNIT
4-BIT ARITHMETIC LOGIC UNIT FULL LOOK-AHEAD CARRY FOR SPEED OPERATIONS ON LONG WORDS GENERATES 16 LOGIC FUNCTIONS OF TWO BOOLEAN ARIABLES GENERATES 16 ARITHMETIC FUNCTIONS OF TWO 4-BIT BINARY WORDS A =
.EXPANDABLE WITH MULTIPLE PACKAGES
HCC/HCF4555B HCC/HCF4556B DUAL BINARY TO 1 OF 4 DECODER/DEMULTIPLEXERS 4555B OUTPUTS HIGH ON SELECT 4556B OUTPUTS LOW ON SELECT.EXPANDABLE WITH MULTIPLE PACKAGES STANDARD, SYMMETRICAL OUTPUT CHAR- ACTERISTICS
HCC/HCF4093B QUAD 2-INPUT NAND SCHMIDT TRIGGERS
QUAD 2-INPUT NAND SCHMIDT TRIGGERS SCHMITT-TRIGGER ACTION ON EACH INPUT WITH NO EXTERNAL COMPONENTS HYSTERESIS OLTAGE TYPICALLY 0.9 AT DD = 5 AND 2.3 AT DD = 10 NOISE IMMUNITY GREATER THAN 50% OF DD (typ.)
NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register
NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register Description: The NTE4035B is a 4 bit shift register in a 16 Lead DIP type package constructed with MOS P Channel an N Channel
74VHCT138ATTR 3 TO 8 LINE DECODER (INVERTING)
3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t PD = 7.6 ns (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 4 µa (MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS: V IH = 2V (MIN.), V IL = 0.8V (MAX) POWER
HCC40147B HCF40147B 10 TO 4 LINE BCD PRIORITY ENCODER
HCC40147B HCF40147B 10 TO 4 LINE BCD PRIORITY ENCODER ENCODES 10 LINE TO 4 LINE BCD ACTIE LOW INPUTS AND OUTPUTS STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERIZATION 100 % TESTED FOR QUIESCENT CURRENT. AT
HCC4527B HCF4527B BCD RATE MULTIPLEXER
HCC4527B HCF4527B BCD RATE MULTIPLEXER CASCADABLE IN MULTIPLES OF 4-BITS SET TO 9 INPUT AND 9 DETECT OUTPUT QUIESCENT CURRENT SPECIFIED TO 20 FOR HCC DEICE STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
HCC4543B HCF4543B BCD-TO-7 SEGMENT LATCH/DECODER/LCD DRIVER HCC/HCF4543B
HCC4543B HCF4543B BCD-TO-7 SEGMENT LATCH/DECODER/LCD DRIER DISPLAY BLANKING OF ALL ILLEGAL INPUT COMBINATIONS LATCH STORAGE OF CODE CAPABILITY OF DRIING TWO LOW POWER TTL LOADS, TWO HTL LOADS, OR ONE LOW
CD4021BC 8-Stage Static Shift Register
8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
TEA6422 BUS-CONTROLLED AUDIO MATRIX
BUS-CONTROLLED AUDIO MATRIX 6 Stereo Inputs 3 Stereo Ouputs Gain Control db/mute for each Output Cascadable ( different addresses) Serial Bus Controlled Very Low Noise Very Low Distorsion Fully ESD Protected
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC133 M74HC INPUT NAND GATE. tpd = 13 ns (TYP.) at VCC =5V
M54HC133 M74HC133 13 INPUT NAND GATE. HIGH SPEED tpd = 13 ns (TYP.) at VCC =5V.LOW POWER DISSIPATION I CC =1µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
CD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC148 M74HC148 8 TO 3 LINE PRIORITY ENCODER. tpd = 15 ns (TYP.
M54HC148 M74HC148 8 TO 3 LINE PRIORITY ENCODER. HIGH SPEED tpd = 15 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
7.5A LOW DROP POSITIVE VOLTAGE REGULATOR ADJUSTABLE AND FIXED. October 2002
THREE TERMINAL ADJUSTABLE OR FIXED OUTPUT VOLTAGE 1.5V,1.8V, 2.5V, 3.0, 3.3V OUTPUT CURRENT UP TO 7.5A 1.4V MAX DROPOUT VOLTAGE AT FULL LOAD LINE REGULATION: MAX 0.2% OVER FULL TEMPERATURE RANGE LOAD REGULATION:
NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register
NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel outputs
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC85 M74HC85 4-BIT MAGNITUDE COMPARATOR. tpd = 22 ns (TYP.) at VCC =5V
M54HC85 M74HC85 4-BIT MAGNITUDE COMPARATOR. HIGH SPEED tpd = 22 ns (TYP.) at VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
. HIGH SPEED .LOW POWER DISSIPATION .OUTPUT DRIVE CAPABILITY M54HCT138 M74HCT138 3 TO 8 LINE DECODER (INVERTING) t PD = 16 ns (TYP.
M54HCT138 M74HCT138 3 TO 8 LINE DECODER (INVERTING). HIGH SPEED t PD = 16 ns (TYP.) at V CC =5V.LOW POWER DISSIPATION ICC =4µAATTA =25 C.OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC354 M74HC354 8 CHANNEL MULTIPLEXER/REGISTER (3 STATE) tpd = 24 ns (TYP.
M54HC354 M74HC354 8 CHANNEL MULTIPLEXER/REGISTER (3 STATE). HIGH SPEED tpd = 24 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT
CD4024BC 7-Stage Ripple Carry Binary Counter
CD4024BC 7-Stage Ripple Carry Binary Counter General Description The CD4024BC is a 7-stage ripple-carry binary counter. Buffered outputs are externally available from stages 1 through 7. The counter is
TC4013BP,TC4013BF,TC4013BFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4013BP,TC4013BF,TC4013BFN TC4013B Dual D-Type Flip Flop TC4013B contains two independent circuits of D type flip-flop. The input level applied
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
LD1117A SERIES LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS
LD1117A SERIES LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS LOW DROPOUT VOLTAGE (1.15V TYP. @ I OUT =1A,25 C) VERY LOW QUIESCENT CURRENT (5 ma TYP. @ 25 C) OUTPUT CURRENT UP TO 1A FIXED OUTPUT
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
Obsolete Product(s) - Obsolete Product(s)
N-CHANNEL 3A - 600 D 2 PAK Power MESH IGBT TYPE CES CE(sat) I c STGB3NB60SD 600
NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4 Bit Counters
NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4Bit Counters Description: The NTE40160B (Decade w/asynchronous Clear), NTE40161B (Binary w/asynchronous Clear),
2N3904 SMALL SIGNAL NPN TRANSISTOR
SMALL SIGNAL NPN TRANSISTOR PRELIMINARY DATA Ordering Code Marking Package / Shipment TO-92 / Bulk -AP TO-92 / Ammopack SILICON EPITAXIAL PLANAR NPN TRANSISTOR TO-92 PACKAGE SUITABLE FOR THROUGH-HOLE PCB
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC4511 M74HC4511 BCD TO 7 SEGMENT LATCH/DECODER DRIVER. tpd = 28 ns (TYP.
M54HC4511 M74HC4511 BCD TO 7 SEGMENT LATCH/DECODER DRIVER. HIGH SPEED tpd = 28 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT
Dual JK Flip-Flop IW4027B TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE. Rev. 00
TECHNICAL DATA IW027B Dual JK Flip-Flop The IW027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and traferred
KD A LOW DROP POSITIVE VOLTAGE REGULATOR ADJUSTABLE AND FIXED
7.5A LOW DROP POSITIVE VOLTAGE REGULATOR ADJUSTABLE AND FIXED THREE TERMINAL ADJUSTABLE OR FIXED OUTPUT VOLTAGE 1.5V,1.8V, 2.5V, 3.0, 3.3V OUTPUT CURRENT UP TO 7.5A 1.4V MAX DROPOUT VOLTAGE AT FULL LOAD
STD5N20L N-CHANNEL 200V Ω - 5A DPAK STripFET MOSFET
N-CHANNEL 200V - 0.65Ω - 5A DPAK STripFET MOSFET Table 1: General Features TYPE V DSS R DS(on) I D Pw Figure 1: Package STD5N20L 200 V < 0.7 Ω 5 A 33 W TYPICAL R DS (on) = 0.65 Ω @ 5V CONDUCTION LOSSES
UNISONIC TECHNOLOGIES CO., LTD U74HC164
UNISONIC TECHNOLOGIES CO., LTD 8-BIT SERIAL-IN AND PARALLEL-OUT SHIFT REGISTER DIP-14 DESCRIPTION The is an 8-bit edge-triggered shift registers with serial input and parallel output. A LOW-to-HIGH transition
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. LM117/217 LM317 1.2V TO 37V VOLTAGE REGULATOR OUTPUT VOLTAGE RANGE: 1.2
NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder
NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder Description: The NTE4514B (output active high option) and NTE4515B (output active low option) are two output options of a 4
STTH6004W. Ultrafast high voltage rectifier. Table 1: Main product characteristics I F(AV) 60 A V RRM. 400 V T j (max) 175 C V F (typ)
STTH64W Ultrafast high voltage rectifier Table 1: Main product characteristics I F(AV) 6 A V RRM 4 V T j (max) 175 C V F (typ).83 V t rr (max) 5 ns Features and benefits Ultrafast switching Low reverse
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M74HC181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR. tpd = 13 ns (TYP.
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR. HIGH SPEED tpd = 13 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING) tpd = 11 ns (TYP.
M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING). HIGH SPEED tpd = 11 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE
LD1117A SERIES LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS
LD1117A SERIES LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS LOW DROPOUT VOLTAGE (1.15V TYP. @ I OUT = 1A, 25 C) VERY LOW QUIESCENT CURRENT (5 ma TYP. @ 25 C) OUTPUT CURRENT UP TO 1A FIXED
SD2902. RF POWER TRANSISTORS HF/VHF/UHF N-CHANNEL MOSFETs
SD292 RF POWER TRANSISTORS HF/VHF/UHF N-CHANNEL MOSFETs GOLD METALLIZATION COMMON SOURCE CONFIGURATION 2 - MHz WATTS 28 VOLTS 12. db MIN. AT 4 MHz CLASS A OR AB OPERATION EXCELLENT THERMAL STABILITY DESCRIPTION
AN1755 APPLICATION NOTE
AN1755 APPLICATION NOTE A HIGH RESOLUTION / PRECISION THERMOMETER USING ST7 AND NE555 INTRODUCTION The goal of this application note is to present a realistic example of a thermometer using an ST7 and
Obsolete Product(s) - Obsolete Product(s)
L494 MULTIFUNCTION OLTAGE REGULATOR FOR CAR RADIO PROGRAMMABLE OUTPUTS: TO (00mA); TO (00mA); TO (00mA) STANDBY OUT AND OUT2 WITH INDEPENDENT EN- ABLE CONTROL FOR STAND-BY MODE 0.4A HIGH SIDE DRIER LOAD
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
L79L00 SERIES NEGATIVE VOLTAGE REGULATORS
L79L00 SERIES NEGATIVE VOLTAGE REGULATORS OUTPUT CURRENT UP TO 100 ma OUTPUT VOLTAGES OF -5; -6; -8; -9; -12; -15 V THERMAL OVERLOAD PROTECTION SHORT CIRCUIT PROTECTION NO EXTERNAL COMPONENTS ARE REQUIRED
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-
CD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. L7900 SERIES NEGATIVE VOLTAGE REGULATORS OUTPUT CURRENT UP TO 1.5A OUTPUT
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity
BAR42FILM BAR43FILM SMALL SIGNAL SCHOTTKY DIODE. Table 1: Main Product Characteristics I F(AV) 0.1 A V RRM. 30 V T j 150 C 0.33 and 0.
BR42FILM BR43FILM SMLL SIGNL SCHOTTY DIODE Table 1: Main Product Characteristics I F(V) 0.1 V RRM 30 V T j 150 C V F (max) 0.33 and 0.40 V FETURES ND BENEFITS Very small conduction losses Negligible switching
Obsolete Product(s) - Obsolete Product(s)
STTH124TV1 Ultrafast high voltage rectifier Table 1: Main product characteristics I F(AV) 2 x 6 A V RRM 4 V T j (max) 15 C V F (typ) t rr (max) Features and benefits Ultrafast switching Low reverse current
MM74HC161 MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear
September 1983 Revised February 1999 MM74HC161 MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear General Description The MM74HC161 and MM74HC163
INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook
INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package
CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part.
DM74LS90/DM74LS93 Decade and Binary Counters
DM74LS90/DM74LS93 Decade and Binary Counters General Description Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage
L7800AB/AC SERIES PRECISION 1A REGULATORS
L7800AB/AC SERIES PRECISION 1A REGULATORS OUTPUT CURRENT IN EXCESS OF 1A OUTPUT VOLTAGES OF 5; 6; 8; 9; 12; 15; 18; 20; 24V THERMAL OVERLOAD PROTECTION OUTPUT TRANSITION SOA PROTECTION 2% OUTPUT VOLTAGE
2N2904A-2N2905A 2N2906A-2N2907A
2N2904A-2N2905A 2N2906A-2N2907A GENERAL PURPOSE AMPLIFIERS AND SITCHES DESCRIPTION The 2N2904A, 2N2905A, 2N2906A and 2N2907A are silicon planar epitaxial PNP transistors in Jedec TO-39 (for 2N2904A and
NE556 SA556 - SE556 GENERAL PURPOSE DUAL BIPOLAR TIMERS. LOW TURN OFF TIME MAXIMUM OPERATING FREQUENCY GREATER THAN 500kHz
SA - SE GENERAL PURPOSE DUAL BIPOLAR TIMERS. LOW TURN OFF TIME MAXIMUM OPERATING FREQUENCY GREATER THAN 00kHz. TIMING FROM MICROSECONDS TO HOURS. OPERATES IN BOTH ASTABLE AND MONOSTABLE MODES HIGH OUTPUT
MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear
MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear General Description These J-K Flip-Flops utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power dissipation of
MC MC35172 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS.. GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2.1MHz, 2V/µs
MC3372 MC3572 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2MHz, 2/µs SINGLE (OR DUAL) SUPPLY OPERATION FROM +4 TO +44 (±2 TO ±22) WIDE INPUT COMMON MODE
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
MM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter
February 1984 Revised February 1999 MM74HC4020 MM74HC4040 14-Stage Binary Counter 12-Stage Binary Counter General Description The MM74HC4020, MM74HC4040, are high speed binary ripple carry counters. These
ST3L01 TRIPLE VOLTAGE REGULATOR
TRIPLE VOLTAGE REGULATOR DUAL INPUT VOLTAGE (12V AND 5V) TRIPLE OUTPUT VOLTAGE (2.6V, 3.3V, 8V) 2.6V GUARANTEED I OUT UP TO 1.2A 3.3V GUARANTEED I OUT UP TO 1.0A 8V GUARANTEED I OUT UP TO 200mA THERMAL
12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS
TECHNICAL DATA IW4040B 2-Stage Binary Ripple Counter High-oltage Silicon-Gate CMOS The IW4040B is ripple-carry binary counter. All counter stages are masterslave flip-flops. The state of a counter advances
MM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. CD4020BC CD4040BC CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage
CD4013BM CD4013BC Dual D Flip-Flop
CD4013BM CD4013BC Dual D Flip-Flop General Description The CD4013B dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors
MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter
4-Bit Decade Counter 4-Bit Binary Counter General Description The MM74C90 decade counter and the MM74C93 binary counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel
74LS195 SN74LS195AD LOW POWER SCHOTTKY
The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped
Table 3: Absolute Ratings (limiting values) Symbol Parameter Value Unit I T(RMS)
TYN61M 1 SCR Table 1: Main Features Symbol Value Unit I T(RMS) 1 V DRM /V RRM 6 V I T (min./max.) 1.5 / 5 m K DESCRIPTION The TYN61M SCR is suitable to fit modes of control found in applications such as
HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder
Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.
BCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,
TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIER
TURBO 2 ULTRAAST HIGH VOLTAGE RECTIIER Table 1: Main Product Characteristics I (AV) Up to 2 x A V RRM 6 V T j 175 C V (typ).95 V t rr (max) 55 ns EATURES AND BENEITS Ultrafast switching Low reverse current
DM7490A Decade and Binary Counter
Decade and Binary Counter General Description The DM7490A monolithic counter contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter
CD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders
CD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed
MM74HC138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features
MM54HC175 MM74HC175 Quad D-Type Flip-Flop With Clear
MM54HC175 MM74HC175 Quad D-Type Flip-Flop With Clear General Description This high speed D-TYPE FLIP-FLOP with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise
INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook
INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger 1997 Apr 07 IC24 Data Handbook FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V