INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC6 74HC/HCT/HCU/HCMOS Logic Package Information The IC6 74HC/HCT/HCU/HCMOS Logic Package Outlines File under Integrated Circuits, IC6 December 199

2 FEATURES Output capability: standard I CC category: MSI GENERAL DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with the 4518 of the 4B series. They are specified in compliance with JEDEC standard no. 7A. The are dual 4-bit internally synchronous BCD counters with an active HIGH clock input (ncp ) and an active LOW clock input (ncp 1 ), buffered outputs from all four bit positions (nq to nq 3 ) and an active HIGH overriding asynchronous master reset input (nmr). The counter advances on either the LOW-to-HIGH transition of ncp if ncp 1 is HIGH or the HIGH-to-LOW transition of ncp 1 if ncp is LOW. Either ncp or ncp 1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nmr resets the counter (nq to nq 3 = LOW) independent of ncp and ncp 1. APPLICATIONS Multistage synchronous counting Multistage asynchronous counting Frequency dividers QUICK REFERENCE DATA GND = V; T amb =25 C; t r =t f = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS HC HCT UNIT t PHL / t PLH propagation delay ncp, ncp 1 to nq n C L = 15 pf; V CC =5 V 2 ns t PHL propagation delay nmr to nq n ns f max maximum clock frequency MHz C I input capacitance pf C PD power dissipation capacitance per counter notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 199 2

3 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 9 1CP, 2CP clock inputs (LOW-to-HIGH, edge-triggered) 2, 1 1CP 1, 2CP 1 clock inputs (HIGH-to-LOW, edge-triggered) 3, 4, 5, 6 1Q to 1Q 3 data outputs 7, 15 1MR, 2MR asynchronous master reset inputs (active HIGH) 8 GND ground ( V) 11, 12, 13, 14 2Q to 2Q 3 data outputs 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 199 3

4 FUNCTION TABLE ncp ncp 1 MR MODE H L counter advances L L counter advances X L no change X L no change L L no change H L no change X X H Q to Q 3 = LOW Fig.4 Functional diagram. Notes 1. H = HIGH voltage level L = LOW voltage level X = don t care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition Fig.5 Logic diagram (one counter). Fig.6 Timing diagram. December 199 4

5 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = V; t r =t f = 6 ns; C L = 5 pf T amb ( C) TEST CONDITIONS SYMBOL PARAMETER 74HC to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t PHL / t PLH propagation delay 66 ncp, ncp 1 to nq n ns 2. Fig.9 t PHL propagation delay 44 nmr to nq n ns 2. t THL / t TLH output transition time ns 2. Fig.9 clock pulse width HIGH or LOW ns 2. master reset pulse width HIGH ns 2. t rem removal time nmr to ncp, ncp ns 2. t su set-up time ncp 1 to ncp ; ncp to ncp ns 2. Fig.7 f max maximum clock pulse frequency ncp, ncp MHz 2. December 199 5

6 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard I CC category: MSI Note to HCT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT ncp, ncp 1 nmr UNIT LOAD COEFFICIENT AC CHARACTERISTICS FOR 74HCT GND = V; t r =t f = 6 ns; C L = 5 pf T amb ( C) TEST CONDITIONS SYMBOL PARAMETER 74HCT to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS ns Fig ns t PHL / t PLH propagation delay ncp, ncp 1 to nq n t PHL propagation delay nmr to nq n t THL / t TLH output transition time ns Fig.9 t rem t su f max clock pulse width HIGH or LOW ns master reset pulse width ns HIGH removal time 11 ns nmr to ncp, ncp 1 set-up time ns Fig.7 ncp 1 to ncp ; ncp to ncp 1 maximum clock pulse frequency ncp, ncp MHz December 199 6

7 AC WAVEFORMS (1) HC : V M = 5%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing hold and set-up times for ncp to ncp 1 and ncp 1 to ncp. Conditions: ncp 1 = HIGH while ncp is triggered on a LOW-to-HIGH transition and ncp = LOW, while ncp 1 is triggered on a HIGH-to-LOW transition. (1) HC : V M = 5%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the minimum pulse widths for ncp, ncp 1 and nmr inputs; the removal time for nmr and the propagation delay for nmr to nq n outputs and the maximum clock pulse frequency. Conditions: ncp 1 = HIGH while ncp is triggered on a LOW-to-HIGH transition and ncp = LOW, while ncp 1 is triggered on a HIGH-to-LOW transition. (1) HC : V M = 5%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the propagation delays for ncp, ncp 1 to nq n outputs and the output transition times. PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines. December 199 7

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS