Successive Approximation ADCs

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1 Department of Electrical and Computer Engineering Successive Approximation ADCs Vishal Saxena Vishal Saxena -1-

2 Successive Approximation ADC Vishal Saxena -2-

3 Data Converter Architectures Resolution [Bits] 20 1 level/t clk 1 word/osr*t clk 1 bit/t clk Integrating Nyquist Oversampling Oversampling Partial word/t clk Successive Approximation Algorithmic Subranging Pipeline Folding & Interpolating 1 word/t clk Interleaving Flash 0 1k 10k 100k 1M 10M 100M 1G 10G 100G Sample Rate [Hz] Vishal Saxena -3-

4 Successive Approximation ADC V i V X V DAC b 1 DAC D o b N Shift Register Binary search over DAC inputs N*T clk to complete N bits successive approximation register or SAR High accuracy achievable (16+ bits) Relies on highly accurate comparator Moderate speeds (typically MHz parts) Vishal Saxena -4-

5 Binary Search Algorithm V DAC V i V i V X V FS V DAC b 1 DAC D o V FS 2 b N Shift Register MSB T clk LSB t DAC output gradually approaches the input voltage Comparator differential input gradually approaches zero Vishal Saxena -5-

6 Binary Search Algorithm contd. Vishal Saxena -6-

7 High Performance Example Vishal Saxena -7-

8 Charge Redistribution SAR ADC Φ 1e V X 8C 4C 2C C C SAR D o V R Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 V i 4-bit binary-weighted capacitor array DAC (aka charge scaling DAC) Capacitor array samples input when Φ 1 is asserted (bottom-plate) Comparator acts as a zero crossing detector Practical implementation is fully-differential Vishal Saxena -8-

9 Charge Redistribution (MSB) Φ 1e V X 8C 4C 2C C C SAR D o V R Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 V i Start with C 4 connected to V R and others to 0 (i.e. SAR=1000) VR 8C - Vi 16C VR Vi 16C = VR - VX C4 - VX C 3 +C 2 +C 1 +C0 VX - Vi 16C 2 Vishal Saxena -9-

10 Comparison (MSB) V X 1 0 t Sample 1 MSB MSB TEST : V X V 2 R V i If V X < 0, then V i > V R /2, and MSB = 1, C 4 remains connected to V R If V X > 0, then V i < V R /2, and MSB = 0, C 4 is switched to ground Vishal Saxena -10-

11 Charge Redistribution (MSB 1) Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 SAR=1100 VR 12C Vi 16C 3 Vi 16C VR VX 12C VX 4C VX VR Vi 16C 4 Vishal Saxena -11-

12 Comparison (MSB 1) V X t Sample 1 0 MSB 3 MSB -1 TEST : VX VR Vi 4 If V X < 0, then V i > 3V R /4, and MSB-1 = 1, C 3 remains connected to V R If V X > 0, then V i < 3V R /4, and MSB-1 = 0, C 3 is switched to ground Vishal Saxena -12-

13 Charge Redistribution (Other Bits) Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 SAR=1010, and so on Test completes when all four bits are determined w/ four charge redistributions and comparisons Vishal Saxena -13-

14 After Four Clock Cycles V X t Sample MSB LSB Usually, half T clk is allocated for charge redistribution and half for comparison + digital logic V X always converges to 0 (V os if comparator has nonzero offset) Vishal Saxena -14-

15 Summing-Node Parasitics Φ 1e C P 8C 4C 2C C C V os SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 If V os = 0, C P has no effect eventually; otherwise, C P attenuates V X Auto-zeroing can be applied to the comparator to reduce offset Vishal Saxena -15-

16 SAR ADC Considerations Power efficiency only comparator consumes DC power Conversion rate typically limited by finite bandwidth of RC network during sampling and bit-tests For high resolution, the binary weighted capacitor array can become quite large E.g. 16-bit resolution, C total ~100pF for reasonable kt/c noise contribution If matching is an issue, an even larger value may be needed E.g. if matching dictates C min =10fF, then 2 16 C min =655pF Vishal Saxena -16-

17 SAR ADC Considerations contd. Comparator offset V os introduces an input-referred offset ~ (1+C P /ΣC j )*V os C P in general has little effect on the conversion (V X 0 at the end of the search) however, V X is always attenuated due to charge sharing of C P Binary search is sensitive to intermediate errors made during search if an intermediate decision is wrong, the digitization process cannot recover DAC must settle into ±½ LSB bound within the time allowed Comparator offset must be constant (no hysteresis or time-dependent offset) Non-binary search algorithm can be used (Kuttner, ISSCC 02) Vishal Saxena -17-

18 SAR ADC Considerations contd. Commonly used techniques Implement "two-stage" or "multi-stage" capacitor network to reduce array size [Yee, JSSC 8/79] Split DAC or C-2C network Calibrate capacitor array to obtain precision beyond raw technology matching [Lee, JSSC 12/84] Vishal Saxena -18-

19 SAR ADC Speed Estimation Model RC network when VIN is charged Replace switches with R s Assume switches are sized proportional to capacitors Vishal Saxena -19-

20 SAR ADC Speed Estimation contd. Speed limited by RC time constant of capacitor array and switches For better than 0.5 LSB accuracy Sets minimum value for the charging time T Vishal Saxena -20-

21 Fully-differential Implementation Vishal Saxena Vishal and Saxena Venkatesh Acharya -21-

22 Recap: Advantages of SAR ADC Mostly digital components good for technology scaling No linear, high precision amplification is required fast, low power Minimal hardware 1 comparator is needed Vishal Saxena -22-

23 SAR Evolution Digital friendly architecture in scaled CMOS has renewed interest in SAR innovation Vishal Saxena -23-

24 Limitations of Synchronous SAR Cost High-speed internal clock needed Speed Limitation Worst-case cycle time Margin for clock jitter Vishal Saxena -24-

25 Asynchronous SAR Concept Self-timed Asynchronous comparisons Master clock used for synchronizing with the sample rate Vishal Saxena -25-

26 How much comparison time is saved? Conv. time between sync. and async. SAR, assuming regenerative comparator is used. It varies with residue voltage profile Vishal Saxena -26-

27 Asynchronous SAR ADC Concept Vishal Saxena -27-

28 Asynchronous SAR ADC Concept Dynamic to save power and generate ready signal Reset switches for fast recovery Ready signal is generated by NAND gate! Vishal Saxena -28-

29 Monotonic Capacitor Switching Monotonic switching procedure Input-common mode voltage gradually converges to ground Exploit differential configuration Asynchronous comparisons Switching energy reduced by 81% Vishal Saxena -29-

30 Monotonic Capacitor Switching contd. Vishal Saxena -30-

31 Monotonic Capacitor Switching contd. Conventional switching procedure Vishal Saxena -31-

32 Monotonic Capacitor Switching contd. Monotonic switching procedure Vishal Saxena -32-

33 Monotonic Capacitor Switching contd. Vishal Saxena -33-

34 Loop-unrolled SAR ADC Use N comparators for each bit of conversion loop unrolling Asynchronous individual comparisons 1.25Gbps 6-bit Serial links application Vishal Saxena -34-

35 Loop-unrolled SAR ADC contd. High speed comparator IDAC for offset cancellation Metastability detection Vishal Saxena -35-

36 Time Interleaving Sampling rate scale proportionally to the number of interleaved channels Calibration is required for interchannel mismatch Relaxed clock distribution For example: 8bit 56GS/s 320 of 175MS/s SAR (Fujitsu) Vishal Saxena -36-

37 90GS/s 8bit with 64x Time Interleave Two comparators ping-pong in two consecutive conversions implemented in 32nm SOI Vishal Saxena -37-

38 References 1. Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2 nd Ed., Springer, Y. Chiu, Data Converters Lecture Slides, UT Dallas B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley Vishal Saxena -38-

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