The influence of parasitic capacitors on SAR ADC characteristics

Transcription

1 The influence of parasitic capacitors on SAR ADC characteristics DMITRY NORMANOV, DMITRY OSIPOV National Research Nuclear University MEPHI ASIC Lab 59, Moscow, Kashirskoe shosse, 3 RUSSIA simplere@ya.ru Abstract: The analysis of the effect of the parasitic capacitors of the split capacitor array on the successive approximation register analog-to-digital converter s charachteristics is presented. The Verilog-A model of the split capacitor array is developed based on the analysis. The model takes the effects of parasitic capacitors into account, and the values of these parasitic capacitors can be extracted from the circuit topology by using Calibre by Mentor Graphics or a similar tool. The influence of the two main parasitic capacitor types (those parallel to and those common to the capacitors in the arrays) on the DAC characteristics is analyzed. We provide expressions for fast manual calculation of the integral non-linearity (INL) and differential non-linearity (DNL) errors according to the values of the parasitic capacitors. Simulation results from a Verilog-A module based on this model are given. Key Words: SAR ADC, parasitic capacitors, INL, DNL, Verilog-A, behavioral model Introduction The use of behavioral models describing the low-level effects that arise in real circuits can save time while providing levels of accuracy close to that of transistorlevel simulations. Use of such a model gives designers the opportunity to analyze how these low-level effects affect the whole chip on a system level and also to find the possible range of low-level effects (for example, parasitic capacitance) that is acceptable for the design ] ]. In this paper the model of a switched capacitor digital-to-analog converter (DAC) based on a split capacitor array is presented for use during the design of a successive approximation register (SAR) analog-to-digital converter (ADC). The model takes the effects of parasitic capacitors into account, and the values of these parasitic capacitors can be extracted from the circuit topology by using Calibre by Mentor Graphics or a similar tool. The split capacitor array, used as both a DAC and a sample-and-hold circuit, is an important element of the SAR ADC. Its non-idealities were previously discussed by several authors 3,, 5, ]. A theoretical expression for the capacitor array s output voltage, involving the effects of common parasitic capacitors, is given in 3]. Unlike the analysis of 3], we also analyze the impact of the parasitic capacitors that are parallel to the capacitors in the array. The dependence of the output voltage from a unity capacitor capacitance distribution is analyzed in ]. A Matlab model for the DAC s transfer function computing is also proposed in ]. The distribution is considered to be normal. However, the actual value of the unity capacitor is determined by the values of the parasitic capacitors, which are binary weighted. Similarly, 5] considers only the errors in unity capacitor values, which are Gaussian random variables. Influence of the internal DAC on the ADC characteristics A well-known architecture for the SAR ADC with a split capacitor array is shown in Figures - 7]. An attenuator capacitor C a is used to split the array into two subarrays. After the sampling phase, the output voltage at the array output is V in V ref, where V in is the ADC input voltage of and V ref is a reference voltage. Then, during the approximation phase, the output voltage reaches a value of V ref + V qe, where V qe is the quantization error. The combination of the DAC s inputs leading to this value is considered to be the conversion result. Thus, the following relationship can be written: σ ( V offset + N V in + V eq = ) β i i (V LSB + V i err ), () where V i n is the input voltage, σ is the amplification error, N is the number of bits used by the DAC, β i =, is the value of the corresponding DAC bit, ISBN:

2 where V p is the voltage on the top plates of the capacitors in the array. () can be rewritten as follows: Figure : Architecture of SAR ADC V LSB is the least significant bit (LSB) voltage of an appropriate ideal DAC, Vi err is the error voltage of the corresponding DAC bit, and V offset is the offset error. The ADC s output code can thus be expressed as: ( ) Vin + V qe D = K V offset Err(D), () V LSB V LSB where D is the ADC s output code, K = /σ is the gain and Err(D) is the code dependent error, which can be expressed as: Err(D) = N β i i V i err /V LSB (3) Thus, according to equations ( - 3), the code dependent errors of the DAC can easily be converted into ADC errors. 3 Analysis of the influence of the common parasitic capacitor on the DAC transfer function First, we consider the influence of the parasitic capacitors C pl and C pm, which are connected as shown in Fig.??. We consider these capacitors as top plates connected to the supply voltage V p, but we show later that the value of this voltage does not matter. It can be shown that the parasitic capacitance to ground has no influence on the DAC performance. From the charge conservation law, we can write (for simplicity, we assume that all bottom plates of the array capacitors are connected to ground): Q M = (V ref V p )C pm, Q L = (V ref V p )C pl, () Q M = V out i β i M i C + (V out V ref ) i M β ii C + (V out V p )C pm + (V out V x )C a, Q L = V x i β L i C + C + (V x V ref ) i β L i C + C + (V x V p )C p L + (V x V out )C a, (5) where C is the unity capacitor value, βi M =, is equal to if the corresponding DAC bit on the most significant bit (MSB) half of the array is set to NULL (the bottom plate of the corresponding capacitor is connected to ground) and if it is not, and βi M =, is equal to if the corresponding DAC bit on the MSB half of the array is set to ONE (the bottom plate of the corresponding capacitor is connected to V ref ) and if it is not. Similar behavior applies for the LSB half of the array. V x is the voltage at the top plates of the capacitors in the LSB half of the array, and V out is the output voltage (the voltage at the top plates of the capacitors in the MSB half of the array). Thus, from equations ( - 5), we can write: =V out i β i M C + (V out V ref ) i β M i C + (V out V ref )C pm + (V out V x )C a, =V x i β L i C + C + (V x V ref )( i β L i C + C ) + (V x V ref )C pl + (V x V out )C a. () We can see from () that the output voltage is independent of the voltage at the bottom plates of the parasitic capacitors. The output voltage of the DAC can be calculated ISBN:

3 Figure : Capacitor DAC as follows: V out = V ref (C suml + C pl + C a ) i βi M C + C pm + C a i βic L + C + C pl (C suml + C pl + C a )(C summ + C pm ) + C a (C suml + C pl )] (7) where C suml is the total capacitance of the LSB half of the array and C summ is the total capacitance of the MSB half of the array. By rewriting equation (7) as a function of the DAC s input code j, we obtain: V out (j) = σ (V outideal (j) + V offset C pl C j + V N/ ref, (8) In (8), we introduced the following notations: σ = ] (C summ + C pm )(C suml + C a + C pl ) + C a (C suml + C pl )], (9) which is the DAC s gain, V offset = V ref C pm (C suml + C a + C pl ) + C a C pl, () which is the offset voltage of the DAC, and, j V outideal (j) = V ref (C suml + C a )C )] + C a C ((j mod ) + (C suml + C a )C summ + C a C suml ], () which is the output voltage of a corresponding ideal DAC (without any errors, including offset, gain and code dependent errors). Thus, we can see that only C pl has an influence on the DAC output voltage. Also, from equation (8), it follows that a nonlinearity in the transfer function occurs only when a capacitor in the MSB half of the array is switched. We calculate the DNL based on the work of 8]: DNL(j) = V (j + ) V (j) LSB e, () where LSB e = V F S / N, and V F S is the voltage corresponding to the maximum DAC input code value. From (8): V F S = σ V outideal ( N ) + V offset + ( )V ref ] C pl C (3). Thus, by substituting (3) and (8) into (), we obtain: DNL(j) = C ( ) pl j + δ C a () The INL can then be calculated based on the following relation 8]: INL(j) = V (j) LSB e j LSB e, (5) ISBN:

4 By substituting (8) into (5), we obtain: INL(j) = C pl C a ( ) j N + (j mod N/ ), () Influence of parasitic capacitors parallel to array capacitors on DAC performance With proper design of the capacitor array (if all of the capacitors in the array are identical unit capacitors), the parasitic capacitors in parallel to the array capacitors are binary weighted. In other words, parallel parasitic capacitors affect the unity capacitor value, so that the value of the attenuation capacitor deviates from the required value. The attenuation capacitor is usually chosen according to the following: C a = C, (7) However, if the real unity capacitor value is C = C + C, where C is the change in capacitance because of binary weighted parasitic capacitors parallel to the array capacitors, the choice of C a as defined in equation (7) will cause an error, which is analyzed below. The following notation is introduced: χ = + C, (8) C Then, C a can be expressed as follow: C a = χc, (9) Taking equation (9) into account, the expression for the ideal output voltage in equation () can be rewritten as follows: V out (j) = V ref + C a C (C suml + C a )C ( (j mod ) + (C suml + C a )C summ j )] + C a C suml], () or, j V out (j) = V ref ( + χ ) ( ) ] + χ (j mod ) + ( + χ )(N/ ) ] + χ N/, () Then, the differential non-linearity arising from the wrong choice of C a value (not taking into account C ) is: DNL(j) = ( )( χ). () By substituting () into (5), we obtain the expression for the integral non-linearity: INL(j) ( χ)( ) ( ) j mod N/ N (j/ ).(3) It is then possible to fully compensate for this nonlinearity through the proper choice of the attenuation capacitor C a, where: 5 Conclusion C a = C suml N. () In order to evaluate the theoretical conclusions, we modeled the internal DAC of the currently developed bit SAR ADC at the level of topology extraction using the Cadence Spectre simulator. As a result of modeling, we constructed the transfer function. The data on the rates of the parasitic capacitors were also transferred as parameters of the Verilog-A model. The results of modeling the developed model and the full transistor level array model with parasitic extraction are compared in the table. A Verilog-A module was written based on expression (8). This module takes the values of C pl, C pm, C a and χ as module parameters. These values can be extracted from the topology view using software tools such as Mentor Graphics Calibre. The accuracy of the model was proved during the design of a -bit SAR ADC, fabricated in a.35 µm standard CMOS technology. Acknowledgements: This research was supported by the Ministry of Science and Education of the Russian Federation (RF Governmental resolution No ) ISBN:

5 Table : Simulation results comparison of the proposed Verilog-A module and the transistor-level model with extracted parasitics DNL, max value, bits Verilog-A model Transistor-level model with extracted parasites Gain error, % Offset, V Simulation time, min References: ] A. Mariano, D. Dallet, Y. Deval, and J. B. Begueret. Top-down design methodology of a multibit continuous-time delta-sigma modulator. Analog Integrated Circuits and Signal Processing, (-):5 53, aug. 7. ] K. Kundert, H. Chang, D. Jefferies, G. Lamant, E. Malavasi, and F. Sendig. Design of mixedsignal systems-on-a-chip. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 9():5 57, dec. 3] Si-Seng Wong, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, U Seng-Pan, and R.P. Martins. Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs. In SoC Design Conference (ISOCC), 9 International, pages , nov Verilog-A model transistor-level model Input Code, bits Verilog-A model transistor-level model Figure 3: Simulation Results ] S. Haenzsche, S. Henker, and R. Schuffny. Modelling of capacitor mismatch and non-linearity effects ini charge redistribution SAR ADCs. In Mixed Design of Integrated Circuits and Systems (MIXDES), Proceedings of the 7th International Conference, pages 3 35, june. 5] B.P. Ginsburg and A.P. Chandrakasan. 5-MS/s 5-bit ADC in 5-nm CMOS With Split Capacitor Array DAC. Solid-State Circuits, IEEE Journal of, ():739 77, april 7. ] B. Bechen, D. Weiler, T. v. d. Boom, and B. J. Hosticka. A bit very low-power cmos sar-adc for capacitive micro-mechanical pressure measurement in implants. Advances in Radio Science, :3,. 7] J. Bialek, A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. Implementation of a digital trim scheme for sar adcs. Advances in Radio Science, :7 3, 3. 8] Maxim. INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs), November. ISBN: