D/A Converters. D/A Examples

Transcription

1 D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction filter DAC Examples D/A Converters EECS 47 Lecture 4: D/A Converter B. Boser D/A Examples Voltage, Charge, or Current Based E.g. Resistor string Charge redistribution M-DAC EECS 47 Lecture 4: D/A Converter B. Boser

2 R-String DAC Unit element Inherently monotonic B resistors and B switches for B bits Simple and relatively fast up to ~ bits High element count, settling time for B > : τ.5 x B RC Vref R R R3 S S S3 S4 Vout S_N Ref: M. Pelgrom, A -b 5-MHz CMOS D/A Converter with 75-W Buffer, JSSC, Dec. 99, pp R_N C EECS 47 Lecture 4: D/A Converter B. Boser 3 Charge Redistribution DAC reset CP Vout ^(B-) C b_b- (msb) 8C b3 4C b C b C b (lsb) C Vref V out B i bi C i V B C + C P ref Binary weighted Monotonicity depends on element matching B+ capacitors ( B unit elements) EECS 47 Lecture 4: D/A Converter B. Boser 4

3 M-DAC Iout ^(B-) Iref 4 Iref Iref Iref Binary weighted Often realized with unit elements also Monotonicity depends on element matching B current sources ( B - unit elements) EECS 47 Lecture 4: D/A Converter B. Boser 5 Static DAC INL / DNL Errors Component Matching Systematic Errors Contact resistance Edge effects in capacitor arrays Process gradient Finite current source output resistance Random Errors Lithography Often Gaussian distribution (central limit theorem) C. Conroy et al, Statistical Design Techniques for D/A Converters, JSSC Aug. 989, pp EECS 47 Lecture 4: D/A Converter B. Boser 6

4 Gaussian Distributions p ( x µ ) ( ) x e π Probability density p(x) x / EECS 47 Lecture 4: D/A Converter B. Boser 7 Yield.4 P ( X x + X ) + X x X e X erf dx Probability density p(x).3.. π P(-X x +X) X EECS 47 Lecture 4: D/A Converter B. Boser 8

5 Yield X/s P(-X x X) [%] X/s P(-X x X) [%] EECS 47 Lecture 4: D/A Converter B. Boser 9 Example Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with mv and µ. Fraction of opamps with V os < X 6mV: X/ % yield (we d still test before shipping!) Fraction of opamps with V os < X 4µV: X/ % yield EECS 47 Lecture 4: D/A Converter B. Boser

6 DNL Unit Element DAC E.g. Resistor string DAC: R I i i DNLi Ri R R DNL o R I i ref Ri Ri ref o o Ri R o Ri R DNL of unit element DAC is independent of resolution! i Example: If R/R %, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec? Answer: From table: X/ 3.3 DNL R/R % 3.3 DNL 3.3% +/-.33 LSB EECS 47 Lecture 4: D/A Converter B. Boser DAC INL Error is maximum at mid-scale: INL B ε B with N Depends on DAC resolution and element matching ε Ref: Kuboki et al, TCAS, 6/98 EECS 47 Lecture 4: D/A Converter B. Boser

7 Untrimmed DAC INL Example: INL B + log ε B ε INL INL. LSB ε % B 8.6 ε.5% B.6 ε.% B 3.3 ε.% B 5.3 EECS 47 Lecture 4: D/A Converter B. Boser 3 Simulation Example DNL [in LSB] - DNL and INL of Bit converter (from converter decision thresholds) -.4 / +.3 LSB, avg6.7e-5, std.dev., range bin ε % B INL.3 LSB (midscale) INL [in LSB] -. / +.8 LSB, avg., std.dev., range bin EECS 47 Lecture 4: D/A Converter B. Boser 4

8 Binary Weighted DAC INL same as for unit element DAC Sample realization of binary weighted DAC: DNL depends on transition Iout ^(B-) Iref 4 Iref Iref Iref Consider EECS 47 Lecture 4: D/A Converter B. Boser 5 DNL of Binary Weighted DAC ( DNL / ε ) 5 Worst-case transition occurs at mid-scale: DNL B B ( ) + ( ) 443 ε B... ε 443 ε DAC input code Example: B, ε % DNL.64 LSB EECS 47 Lecture 4: D/A Converter B. Boser 6

9 Simulation Example DNL [in LSB] - DNL and INL of Bit converter (from converter decision thresholds) -.9 / +.4 LSB, avg-7.5e-5, std.dev.39, range bin ε % B DNL.6 LSB (midscale) INL [in LSB] / +.7 LSB, avg3.3e-4, std.dev.33, range bin MSB transitions clearly visible EECS 47 Lecture 4: D/A Converter B. Boser 7 Another Random Run DNL [in LSB] - - DNL and INL of Bit converter (from converter decision thresholds) - / +. LSB, avg-9.3e-5, std.dev.35, range bin Now (by chance) worst DNL is mid-scale. Statistical result! INL [in LSB] -.8 / +.8 LSB, avg-.e-3, std.dev.37, range bin EECS 47 Lecture 4: D/A Converter B. Boser 8

10 Unit Element vs Binary Weighted Unit Element DAC DNL INL ε B ε Binary Weighted DAC DNL INL B B ε ε INL Number of switched elements: S B S B Significant difference in performance and complexity! EECS 47 Lecture 4: D/A Converter B. Boser 9 DAC INL/DNL Summary DAC architecture has significant impact on DNL INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision Results are for uncorrelated random element variations Systematic errors and correlations are usually also important Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string converters. IEEE Transactions on Circuits and Systems, vol.cas-9, (no.6), June 98. p EECS 47 Lecture 4: D/A Converter B. Boser

11 Segmented DAC Objective: compromise between unit element and binary weighted DAC Approach: B MSB bits unit elements B B-B LSB bits binary weighted INL: unaffected DNL: worst case occurs when LSB DAC turns off and one more MSB DAC element turns on: same as binary weighted DAC with B + bits Switched Elements: ( B -) + B EECS 47 Lecture 4: D/A Converter B. Boser Comparison Example: B, B 5, B 7 ε % DAC Architecture INL DNL # s.e. Unit element Binary weighted Segmented EECS 47 Lecture 4: D/A Converter B. Boser

12 Dynamic DAC Error: Glitch Consider binary weighted DAC transition DAC output depends on timing ideal early 5 Plot shows situation where MSBs switch on time LSBs switch On time Early Late late Time EECS 47 Lecture 4: D/A Converter B. Boser 3 Glitch Energy Glitch energy (worst case): t B- LSB energy: T Need t B- << T or t << -B+ Examples: f s [MHz] B 6 t [ps] << 488 <<.5 << Compare to digital circuit clock skew EECS 47 Lecture 4: D/A Converter B. Boser 4

13 DAC Reconstruction Filter Need for and requirements depend on application Tasks: Correct for sinc distortion Remove aliases (stair-case approximation) DAC Input sinc DAC Output x x 6.5 B f s /.5.5 Frequency.5 3 x 6 EECS 47 Lecture 4: D/A Converter B. Boser 5 Reconstruction Filter Options Digital Filter DAC SC Filter ZOH CT Filter Digital and SC filter possible only in combination with oversampling (signal bandwidth B << f s /) Digital filter can prewarp spectrum to compensate inband sinc attenuation (from ZOH) EECS 47 Lecture 4: D/A Converter B. Boser 6

14 Sample DAC Implementations Untrimmed segmented T. Miki et al, An 8-MHz 8-bit CMOS D/A Converter, JSSC December 986, pp A. Van den Bosch et al, A -GSample/s Nyquist Current-Steering CMOS D/A Conveter, JSSC March, pp. 35. Current copiers: D. W. J. Groeneveld et al, A Self-Calibration Techique for Monolithic High-Resolution D/A Converters, JSSC December 989, pp. 57. Dynamic element matching: R. J. van de Plassche, Dynamic Element Matching for High- Accuracy Monolithic D/A Converters, JSSC December 976, pp EECS 47 Lecture 4: D/A Converter B. Boser 7 EECS 47 Lecture 4: D/A Converter B. Boser 8

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18 EECS 47 Lecture 4: D/A Converter B. Boser 35 Dynamic Element Matching During Φ During Φ () () I Io( + ) I Io( ) () () I I ( ) I I ( + ) o o I o / I o / I I I () () I + I Io Io ( ) + ( + ) f clk / error I o EECS 47 Lecture 4: D/A Converter B. Boser 36

19 Dynamic Element Matching During Φ During Φ () () I Io( + ) I Io( ) () () I I ( ) I I ( + ) I () 3 I o () I 4 o ( + ) ( + )( + ) () I3 + I I3 Io 4 Io 4 () 3 I () 3 I o () I 4 o ( + )( + ) + ( )( ) ( + ) ( ) ( )( ) I o /4 I o /4 I o / I 3 I 4 I f clk / error I f clk / error E.g. % matching error is (%).% I o EECS 47 Lecture 4: D/A Converter B. Boser 37