High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments

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1 Erik Jonsson School of Engineering & Computer Science High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments Yun Chiu Erik Jonsson Distinguished Professor Texas Analog Center of Excellence University of Texas at Dallas

2 ADC = Sampling + Quantization ref CT, CA in out DT, DA Analog Input Digital Output f s V Vin t N Vin nt FS s LSB = =, Dout n = = 2 N 2 VFS t=nt s Quantization = division + normalization + truncation V FS is the Full-Scale range of ADC determined by V ref IHEP, 11/3/14-2- Y. Chiu

3 ADC Figure-of-Merit (FoM) Walden FoM: FoM W P Joule ENOB 2BW 2 Conversion - Step Schreier FoM: FoM 10log S 10 2BW 4 P ENOB db P: power consumption ENOB: effective number of bits BW: min{f s /2, ERBW} ERBW: effective resolution BW Walden FoM is intuitive works better for lower resolution designs. Schreier FoM is more fair for higher dynamic range designs. IHEP, 11/3/14-3- Y. Chiu

4 Performance, Efficiency, and Power Performan ce =2 BW α ENOB Hz Step Performance = Speed Precision α/2 Energy Efficiency P J α/2 2BW α ENOB Step Note: Performance Efficiency ENOB P =2 BW α = Power ENOB 2BW α α=2-4 IHEP, 11/3/14-4- Y. Chiu

5 Performance Efficiency (PE) Chart 1E+17 1E+16 Constant performance Performance = 2 BW 3 ENOB 1E+15 1E+14 (log scale) 1E+13 1E+12 1E+11 1E+10 Constant efficiency 1E+09 1E-18 1E-17 1E-16 1E-15 1E-14 1E-13 1E-12 (log scale) X Y = Power α=3 Energy Efficiency = Power/(2 BW 3 ENOB ) IHEP, 11/3/14-5- Y. Chiu

6 PE Chart: SAR ADC (<2014) 1E+15 SAR (<2005) 1E+14 12b,160MS/s 5mW SAR ( ) SAR ( ) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IHEP, 11/3/14-6- Y. Chiu

7 PE Chart: SAR and Pipeline ADCs (<2014) 1E+15 1E+14 12b,160MS/s 5mW Industry ADCs Pipeline (<2005) Pipeline ( ) Pipeline ( ) SAR (<2005) SAR ( ) SAR ( ) Performance 1E+13 1E+12 University ADCs 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IHEP, 11/3/14-7- Y. Chiu

8 PE Chart: SAR and Pipeline ADCs (<2014) 1E+15 1E+14 ADI TI KENET NSC BCM Agilent Pipeline (<2005) Pipeline ( ) Pipeline ( ) SAR (<2005) SAR ( ) SAR ( ) Performance 1E+13 OSU IMEC 1E+12 NCTU NCKU OSU AKM Panasonic MIT Michigan Fujitsu ADI 10W 1E+11 EUT 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IHEP, 11/3/14-8- Y. Chiu

9 Our ADC Roadmap ISSCC 04, 14b pipelined ADC (Jack Kilby Outstanding Paper Award) ISSCC 09, 8b 600MS/s TI-ADC (ISSCC/DAC Student Design Contest Award) ISSCC 10, 12b 45MS/s SAR ADC (most read/downloaded JSSC article of Nov. 2011) CICC 12, 12b 50MS/s SAR ADC (Best Regular Paper Award) VLSI 12, 240MS/s, 8X OSR SD ADC VLSI 14, 12b, 160MS/s SAR ADC CICC 14, 9b, 215MS/s RNS TDC (Intel/TI/Catalyst CICC Student Scholarship Award) ADC FoM [pj/step] ISSCC 04 VLSI 06 CICC 08 ISSCC 09 ISSCC 10 CICC ITRS 2009 ITRS Our ADCs VLSI Year IHEP, 11/3/14-9- Y. Chiu

10 Our Approach Adaptive Digital Equalization IEEE Comm. Magazine April, IHEP, 11/3/ Y. Chiu

11 Precision in Presence of Analog Impairments Model of Wireless Comm. Channel Berkeley, 2001 h 1 h 2 h 4 n yn=hxn+hxn-1+hxn-2+hxn h 3 Model of A Pipeline ADC D o =h1 d 1+h2 d 2+h3 d 3+h4 d4 IHEP, 11/3/ Y. Chiu

12 ADC in Phase-II LAr Readout FEB High resolution: bits High speed: MS/s Low power, low area Radiation tolerant Detector Output Signal Potential Phase-II Upgrade FEB (On detector) Preamp Analog Shaper ADC MUX & Serializer To Back-end Optical Links IHEP, 11/3/ Y. Chiu

13 Architecture Choice: SAR vs. Pipeline SAR Pipeline V i V X d 0 V DAC DAC... D o d N-1 Pipelined ADC: High-gain residue amplifier hard to scale w/ process SAR ADC: low-power, low-area is a strong candidate for Phase-II IHEP, 11/3/ Y. Chiu

14 Moore s Law The number of transistors on a chip doubles every 18 months - Gordon Moore, IEDM 1975 R. Chau, ICSICT 2004 Source: IHEP, 11/3/ Y. Chiu

15 Challenges for Analog Design Courtesy of K. Bult IHEP, 11/3/ Y. Chiu

16 12-bit, 45-MS/s, 0.13-μm CMOS ADC Sub-binary DAC ODC V X CLK CMP n Ready CLK C 13 C 1 C 0 C 0 C C 13,d C 6,d CMP p d 13 d 1 d 0 +V R V R SAR Logic ACLK V in V i V X REDUNDANCY CAL d 0 V DAC DAC... D o d N-1 IHEP, 11/3/ Y. Chiu

17 Sub-Binary DAC and Redundancy 2 N D out No redundancy MSB = 0 2 N MSB = 1 0 FS/2 FS V in Binary Super-binary Sub-binary Built-in redundancy helps combat dynamic conversion errors (DAC mismatch, comparator, DAC settling, even SEU) Redundancy is also needed for digital claibration IHEP, 11/3/ Y. Chiu

18 Offset Double Conversion (ODC) Digital Post-Processing ODC is implemented in DAC w/ a small cap IHEP, 11/3/ Y. Chiu

19 How to determine Bit Weights? Is the transfer curve shift-invariant? IHEP, 11/3/ Y. Chiu

20 How to determine Bit Weights? Is the transfer curve shift-invariant? IHEP, 11/3/ Y. Chiu

21 How to determine Bit Weights? Is the transfer curve shift-invariant? IHEP, 11/3/ Y. Chiu

22 How to determine Bit Weights? Shift-invariant ONLY when the transfer curve is completely linear! Non-constant difference b/t D + and D reveals bit weight information IHEP, 11/3/ Y. Chiu

23 12-bit, 45-MS/s, 0.13-μm CMOS ADC Sub-binary DAC ODC V X CLK CMP n Ready CLK C 13 C 1 C 0 C 0 C C 13,d C 6,d CMP p d 13 d 1 d 0 +V R SAR Logic ACLK V R V in Die size: 0.06 mm 2 12 b, 45 MS/s in FG mode 3-mW power (36.3 fj/step) Most read JSSC article Nov IHEP, 11/3/ Y. Chiu

24 Measured ADC Spectra (BG Mode) 0-20 SNDR = 60.2dB SFDR = 66.4dB THD = -61.7dB 0-20 SNDR = 70.7dB SFDR = 94.6dB THD = -89.1dB Before Cal. After Cal. db -60 db Freq [MHz] Freq [MHz] IHEP, 11/3/ Y. Chiu

25 Comparison with 12-bit ADCs 10 1 (@ time of publication) FoM (pj/conv. step) MS/s MS/s Year Total Power: 3.0 mw Active area (mm 2 ) mm Year IHEP, 11/3/ Y. Chiu

26 12-bit, 160-MS/s, 40-nm CMOS ADC (5b + 8b) synchronous two-step pipelined SAR architecture First-stage capacitor weights identified w/ opportunistic DAC dither IHEP, 11/3/ Y. Chiu

27 Subranging, Swing, and Linearity C f =C s /32 C f =C s /8 Stage1 +V ref Stage2 +V ref Stage1 Stage2 +0.5V ref C s V in A 0 V out V out V out C s -V ref 5bit 7bit Smaller output swing for residue amplifier Compensated by 2 nd stage SAR ADC Increased resolution (7 bit 8 bit) Scaled reference voltage (V ref 0.5V ref ) -V ref5bit -0.5V ref 8bit 1-bit redundancy tolerates offset IHEP, 11/3/ Y. Chiu

28 Simple Residue Amplifier Two-stage amplifier provides ~ 30-dB gain Gain error is lumped into bit weights and calibrated IHEP, 11/3/ Y. Chiu

29 Second-Stage SAR ADC Reference voltage is effectively halved Minimal loading determined by kt/c noise IHEP, 11/3/ Y. Chiu

30 Die Photo 300μm 139μm Clock Sub& ADC1 PN Gen. Integrator + DAC SubADC2 SubADC3 SubADC4 SubADC5 MDAC1 MDAC2 MDAC3 MDAC4 40-nm digital CMOS process (die size = mm2) IHEP, 11/3/ Y. Chiu

31 Measured ADC Dynamic Performance 90 fs = 160MHz after cal. 90 fin = 25MHz after cal db f Nyquist =80M Hz db f s =160MH z SNDR SFDR Fin fin [MHz] 60 SNDR SFDR Fs fs [MHz] IHEP, 11/3/ Y. Chiu

32 Power Breakdown (VLSI 14 Version) Analog 1.1V 2.8mW (53.6%) Total power is ~ 5 mw at 160-MS/s operation IHEP, 11/3/ Y. Chiu

33 ADC PE Chart Revisited 1E+15 1E+14 12b,160MS/s 5mW Pipeline (<2005) Pipeline ( ) Pipeline ( ) SAR (<2005) SAR ( ) SAR ( ) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IHEP, 11/3/ Y. Chiu

34 TID Test of 40-nm CMOS SAR ADC DUT under X-ray radiation when powered up w/ clock input. ADC performance (e.g., SNDR, SFDR, power, etc.) measured after irradiation is complete. IHEP, 11/3/ Y. Chiu

35 Measured SNDR and 80 MS/s fin=10mhz fin=25mhz fin=40mhz SNDR [db] ENOB [bit] SFDR [db] ENOB [bit] Radiation dose [krad] Radiation dose [krad] IHEP, 11/3/ Y. Chiu

36 Measured SNDR and 160 MS/s fin=10mhz fin=25mhz fin=40mhz fin=70mhz SNDR [db] ENOB [bit] SFDR [db] ENOB [bit] Radiation dose [krad] Radiation dose [krad] IHEP, 11/3/ Y. Chiu

37 Annealing (f s = 80 MS/s) SNDR [db] After 300-krad Radiation fin = 10MHz fin = 25MHz fin = 40MHz After 500-krad Radiation fin = 10MHz fin = 25MHz fin = 40MHz After 1000-krad Radiation fin = 10MHz fin = 25MHz fin = 40MHz SFDR [db] Time after radiation [hour] Time after radiation [hour] Time after radiation [hour] IHEP, 11/3/ Y. Chiu

38 Annealing (f s = 160 MS/s) SNDR [db] After 300-krad Radiation fin = 10MHz fin = 25MHz fin = 40MHz fin = 70MHz After 500-krad Radiation fin = 10MHz fin = 25MHz fin = 40MHz fin = 70MHz After 1000-krad Radiation fin = 10MHz fin = 25MHz fin = 40MHz fin = 70MHz SFDR [db] Time after radiation [hour] Time after radiation [hour] Time after radiation [hour] IHEP, 11/3/ Y. Chiu

39 Measured ADC Power Total Power consumption [mw] fs=80mhz fs=160mhz Power consumption [mw] Digital fs=80mhz Analog fs=80mhz Digital fs=160mhz Analog fs=160mhz Radiation dose [krad] Radiation dose [krad] IHEP, 11/3/ Y. Chiu

40 To conclude Low power, small area, increasing conversion speed, and resolution of SAR ADC bode well for future HEP applications. TID testing results confirm the long-term radiation tolerance of CMOS SAR ADCs. Great potential for treating short-term effects (SEU etc.) using simple circuit techniques. Targeting 14b, 80MS/s for ATLAS Phase2 IHEP, 11/3/ Y. Chiu

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