Analog Design Challenges in below 65nm CMOS

Transcription

1 Analog Design Challenges in below 65nm CMOS T. R. Viswanathan University of Texas at Austin 4/11/2014 Seminar 1

2 Graduate Students Amit Gupta (TI):Two-Step VCO based ADC K. R. Raghunandan (Si Labs): Analog Design challenges in Emerging Technologies Mikel Ash (Cirrus Logic): High-Speed Serial Data Com; New low power analog ideas. Rohit Yadav (Si Labs): 3-D printed Devices - SWCNT, Metal Oxide Funded fun work Peijun Wang (UT): Linear VCO Design Revanna (UT): Low-power Sinusoidal Oscillator for Impedance Spectroscopy-Biomedical 4/11/2014 Seminar 2

3 Two-Step VCO ADC Architecture Pseudo-differential 10-bit two step Architecture 2,3 First Step: 5bit-Flash (SAR for low power-lower speed) Second Step: 5bit VCO-based ADC 2 Low value of residue that becomes the input to the second step of conversion reduces the linearity requirements of the VCO 2 Aggressive reference scaling 2 enables smaller inter-stage closed loop-gain. Higher open loop gain becomes possible by Cascoding 2. Reference recycling to mitigate gain-error 2. Equivalent of a dual slope converter : Integrator is replaced by VCO and counter. Calibration is simple. Noise shaping can be obtained by Phase counting of VCO 3 1. IEEE Trans. on Circuits and Systems II, Volume:57, Issue: 11 Nov (966) 2.IEEE Trans. On Circuits and Sys. II,Volume:58,Issue: 11, Nov pp IEEE 56th Midwest Symp. on Circuits and Systems, 2013, Aug pp /11/2014 Seminar 3

4 Analog Design Challenges in below 65nm CMOS High-speed Building Blocks (+,-,scale) using Class A-B CMOS inverter: 6-bit resolution. Forget about op-amp and infinitegain feedback at these speeds: Remember that the second world war was won without even the notion of an op-amp. Believe in this new mindset at these speeds. Think finite- Gain (2,4) with controlled feedback amplifiers for fast ADC. For example - Unity-Gain Buffer is a good starting point. Traditional use of a replica is not very effective because adjacent devices do not pretend to match. Multiplex the same device as replica when needed. Use S-C s. Anti-alias Filter will need g m - control. Use V/I/T References We can do more energy-efficient ASP at GHz range 4/11/2014 Seminar 4

5 Transconductances V DD V DD v g m v v g m v V LT V SS Transconductance (a) V SS Inverting Transconductance + + v v - g m v - g m v (b) 4/11/2014 Seminar 5

6 Forming a sort of Virtual ground (V LT ) g m Virtual ground V OUT = I IN /g m I IN 4/112/2014 Seminar 6

7 Finite Voltage -Gain 1 1 V IN 2 V IN 2 V OUT = V IN V OUT = -V IN Voltage gain Av 4/11/2014 Seminar 7

8 Multiplier 2V LT K(V ON +v) 2 V LT +v V LT -v K(V ON -v) 2 4/11/2014 Seminar 8

9 Input to the multiplier I LT V LT +v X v X v X +v Y v X v Y V LT +v Y I LT v X v X -v Y v Y v Y 1/15/2008 EE438 9

10 High-Speed Serial Data Minimize ISI Communication use a pulse with a leading exponential edge. Minimize dispersion (Mikel Ash) Generate an exponential pulse V o e t/t Bipolar Transistor I C =I s exp (v BE /v T ) Get rid of the nasty temperature sensitive I S an Compensate for v T =kt/q Control of time-constant t 4/11/2014 Seminar 10

11 Better BJT: I C = I REF exp(v IN /v T ) v T ln(i REF /I S ) V in - I REF I C + V BE _ PTAT Generator I c = I S exp (v BE /v T ) V BE =V in + v T ln(i REF /I S ) I c = I REF exp (v in /v T ) - v T + I T I S is gone! T =nt v T t/t 4/11/2014 Seminar 11

12 Impedance Spectroscopy Identification of large molecules, DNA etc in liquid state. Also known as Cyclic Voltametry Measure the real and imaginary parts of complex impedance. Challenge: Low freq. resonance KHz to 5 MHz Sinusoidal Oscillators: Sine and Cosine outputs Hand held instruments like Blood Glucometer Low-power :Throw away chip after a single test. Two Designs are investigated, W-B and L-C 4/11/2014 Seminar 12

13 Wein Bridge Oscillator 1/15/2008 EE438 13

14 Transfer functions 4/11/2014 Seminar 14

15 Implementation 4/11/2014 Seminar 15

16 Transconductance 4/11/2014 Seminar 16

17 Additional I-inversion Via Mirrors 4/11/2014 Seminar 17

18 Both types of g m elements 4/11/2014 Seminar 18

19 Amplitude Detection Sin 2 f +cos 2 f=1 4/11/20148 Seminar 19

20 Diode-Connected Squarer Gives Squareroot 4/11/2014 Seminar 20

21 i=kv 2 and v= (i/k) 4/11/2014 Seminar 21

22 Sine and Cosine Outputs 4/11/2014 Seminar 22

23 Gyrated L= C/gm 2 Symmetric Design C1=C2, Use the Q=gm/go=Av gm1=gm2=gm, w= gm/c formula Pretty? L= C/gm 2 Q =wl/r 4/11/2014 Seminar 23

24 LC - Oscillator 4/11/2014 Seminar 24

25 Negative resistance 4/11/20014 Seminar 25

26 Cap-Scaling by shunt A i NFB 4/11/2014 Seminar 26

27 Controlled Oscillators for Low- Power ADC A controlled- Oscillator with linear tuning characteristics quantizes phase which is proportional to the integral of the input. A key objective is to design an ICO with adequate linearity.( Peijun Wang) Count the output frequency for a known period : Too slow Both the operations of integration and quantization are performed by a simple controlled oscillator. In a traditional S-D converter we do this with an op-amp integrator and 1-b comparator Low-power converters are needed for v/i- meters, Bio, Audio signals In two-step converters the residue from the first step is converted with a VCO or Voltage to time converter. 4/11/2014 Seminar 27

28 ICO integrates and quantizes +V C - V REF I IN Counter quantizes Phase at 2p Think that the Integrator with a rest switch to short C when V C reaches V REF (2p) When we want to integrate for a long time ( say one year) we abandon our inhibitions and jump into the digital world for obvious reasons. Living beings have built-in clocks (obviously not designed in Si Labs). Recently I found out that that the DNA is piezo-electric! Why do we integrate for a long time? ( think of 401K or 401 M). Generate gain (money grows without paying tax). Now we differentiate in the digital domain to get the signal and in that process shape the additive quantization noise. 4/11/2014 Seminar 28 f 2p

29 Source-Coupled Multivibrator First Consider Resistive Loads (I IN /C)(T/2) = 2 I IN R Rr Rr I cancels and f CR There are many ways to clamp The voltage change across the load Substitute Active loads (I/C)(T/2) = 2 l -1 We get linear currentcontrol of Frequency Simple circuit Works at High frequencies 6-bit INL is obtainable Without calibration 4/11/2014 Seminar 29

30 Active Load 4/11/20148 Seminar 30

31 Transfer Characteristics Temperature Variation 4/11/2014 Seminar 31

32 Process Variation 4/11/2014 Seminar 32

33 Linear CCO Design Define T = CV REF /I or f = I/2CV REF No temperature or process variation Switch the input current-direction for discharging C Input Current-Mirror for charging l -1 or discharging C V REF I D = k ( V GS -V TH ) 2 (1+lV DS ) T* T*/T = r ln[r/(r-1)] where r= l -1 /V REF >1 This can be verified by simulation. 4/11/2014 Seminar 33

34 Switching Delay 4/11/2014 Seminar 34

35 Model f = 1/ (T + 2t d ) t d = c /g = c / (ki IN ) DV= (I IN /C) t d = (I IN /C) [c / (ki IN )] DV=aV ON where V ON = (I IN /k) and a= c /C DV is an offset in a differential pair or the V DS of a triode-operated output transistor of a current-mirror. 4/11/2014 Seminar 35

36 Generating a V ON I IN I IN V ON 1: n + g V ON - g=1- [1- (1/n)] 4/11/2014 Seminar 36

37 Start with this known circuit 4/11/2014 EE438 37

38 CCO 4/11/2014 Seminar 38

39 V th based reference V REF = V th + l v T.(1) CTAT + PTAT (Obtained as usual) CTAT is V th instead of V BE why? Minimal-circuit operates with < 1V powersupply. There is enough head room left for supply-regulation to get good PSRR Many references if there are V thl & V thh Select the right circuit instead of trimming. 4/11/2014 Seminar 39

40 Voltage Reference MS Thesis of Stefan Mastovich : Simplified further m V DD 1 10 M P1 M P2 1 M P5 M P6 M P3 P M P4 C I BI I D1 I D2 I B2 I 1 I 2 V+V REF2 V REF V BE1 M 1 M 2 =M 1 V BE2 M 3 V REF1 V M P7 Q 1 V SS Q 2 =10Q 1 I B1 =I s exp ( V REF /v T ) 4/11/2014 Seminar 40

41 How it works + FB for CM from V BE1 = FB, from V BE2 for m>1 The currents balance at the node P giving k (V BE1 -V th ) 2 = m k(v BE2 -V th ) 2 V BE1 -V th = m (V BE2 -V th ) V BE1 - V BE2 = (V BE2 - V th ) ( m -1) (gv PTAT )/( m -1) +V th = V BE2 V BE1 = (gv PTAT ) ( m) /( m -1) 4/11/2014 Seminar 41

42 ( m) /( m -1) PTAT Gain 4/11/2014 m seminar 42

43 Know more about signals Signals vary in time in different ways. When we sample and hold we collect only the instantaneous value. We throw away its history Know its history and use it to estimate where it is heading. Controlled oversampling enables this. New ADC designs use all the information in novel ways to reduce power. 4/11/2014 Seminar 43

44 SAR using VCO A comparator performs some amplification a single-bit quantization. It has an amplifier and a latch What kind of an amplifier is it? Is it really algebraic? At high speeds it is more like a gm/c pseudo integrator What does a latch do? V o e t/t CCO Integrates and does multi-bit quantization. 4/11/2014 Seminar 44

45 Getting More Information to Simplify Search Oversample with delayed clocks This is not a clock- multiplexed ADC Delay need not be exact fraction of Tclk We estimate derivatives This information is used to simplify the search Can we reduce N to N/2 to obtain N-bits? 4/11/2014 Seminar 45