An Anti-Aliasing Multi-Rate Σ Modulator

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1 An Anti-Aliasing Multi-Rate Σ Modulator Anthony Chan Carusone Depart. of Elec. and Comp. Eng. University of Toronto, Canada Franco Maloberti Department of Electronics University of Pavia, Italy May 6, 009

2 Outline Motivation and background Anti-aliasing multi-rate modulator front-end Practical considerations Mismatch Clocking Opamp settling requirements Simulation results Conclusions

3 Aliasing in Discrete-Time Σ Modulators Desired signal Alias f 0 OSR 3

4 Anti-Aliasing in Discrete-Time Σ Modulators Desired signal Alias Desired signal Alias 0 s fs OSR f 0 s fs OSR f Σ DSP AAF AAF may be either a continuous-time filter or a discrete-time filter operating at a higher sampling rate [6,7], M 4

5 Discrete-Time Σ Modulator with Discrete-Time Anti-Aliasing Filter L(z) M Σ M Basic idea is to incorporate L(z) into the frontend of the Σ modulator with minimal circuit overhead 5

6 Hybrid Σ Modulators from DAC in C i to modulator There are several examples of modulators incorporating a continuous-time front-end to provide an anti-aliasing STF [-5], but these are still susceptible to clock jitter, like all CT modulators. 6

7 Conventional Σ Modulator Front-end from DAC in φ C φ i C i φ i φ to modulator in from DAC C C i z to modulator 7

8 Σ Modulator with Anti-Aliasing Front-end Sampler from SC-DAC in φ, C φ C i in φ φ i from DAC C φ φ i C i to modulator φ C φ, φ, φ φ φ, φ, φ, to modulator φ, φ φ φ φ, φ, φ φ φ,, φ φ, φ 8

9 Σ Modulator with Anti-Aliasing Front-end Sampler from SC-DAC in φ, C φ C i φ C φ, φ, φ to modulator φ φ, φ, φ, φ φ φ, φ, φ φ, in M M k = C k z C k M from DAC ( C C i )z z to modulator φ φ φ,, φ φ, φ 9

10 Σ Modulator with Anti-Aliasing Front-end Sampler in M M k = L(z) M Σ Similar approach has been applied to C k z C k M from DAC ( C C i )z z to modulator M integrate antialiasing into the front-end of a discrete-time filter [8,9] and SAR ADC [0] 0

11 Other Multi-Rate Σ Modulators e.g. []: M M H(z) M

12 Other Multi-Rate Σ Modulators e.g. []: M M H(z) M Multi-bit quantizer is replaced by a single-bit modulator + decimator operating at increased sampling rate

13 Choice of capacitor values, C k Zeros of L(z) with M = 5 : C k = (C/M) C k chosen to maximize anti-aliasing around 3

14 Choice of capacitor values, C k C k optimized C k = (C/M) Increased width of the anti-aliasing notch is particularly important in low-osr modulators 4

15 Capacitor Mismatch Alias frequency band for OSR = 4 C k = (C/M) C k optimized 00 Monte-Carlo frequency responses with capacitor value standard deviation of 0.% 5

16 from SC-DAC Clocking in φ, C φ C i This scheme requires the generation of multiple clock phases [] φ C φ, φ, φ to modulator Faster settling of the sampling capacitors necessitates larger switches and, hence, some overhead in the clock distribution φ φ, φ, φ φ, φ, φ Skew between the clock phases results in harmonic at ±f in, which will be filtered by the following digital decimation filter φ φ, φ, φ φ φ,, φ φ, φ 6

17 OpampSettling Time Conventional Σ modulator front-end during the integration phase: Anti-aliasing multi-rate Σ modulator front-end during the integration phase: C C i C C i C in C in Since only ½ of the total sampling capacitance is integrated at any time, the feedback factor in the integration phase is increased, thus permitting the use of an opampwith lower GBW. 7

18 Simulation Results 3 rd -oder modulator OSR = 4 Two-tone input: - dbfsin-band -30 dbfsat 0.98 a) Conventional front-end b) Anti-aliasing multi-rate front-end with M= 5 and C k = C/M c) Anti-aliasing multi-rate front-end with M= 5 and optimized C k (a) SNDR = 8.5 db (b) SNDR = 6.3 db (c) SNDR = 84.3 db Aliased tone 8

19 Simulation Results 35 db 30 db 9

20 Conclusions Splitting the input sampling capacitor in a discrete-time Σ modulator into multiple parallel branches sampled at increased rate enables the STF to be shaped by an FIR transfer function, here used for anti-aliasing Example 3 rd -order modulator with OSR=4 and M=5 demonstrates: 35 db of anti-aliasing is provided by a uniformly segmented input sampling capacitor, C k = C/5 An additional 30 db of anti-aliasing is provided when the values of C k are optimized for a total of 65 db of anti-aliasing 0

21 EXTRAS

22 Simulation Model

23 Table of optimized capacitor values 3

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