ir. Georgi Radulov 1, dr. ir. Patrick Quinn 2, dr. ir. Hans Hegt 1, prof. dr. ir. Arthur van Roermund 1 Eindhoven University of Technology Xilinx
|
|
- Todd Nichols
- 5 years ago
- Views:
Transcription
1 Calibration of Current Steering D/A Converters ir. eorgi Radulov 1, dr. ir. Patrick Quinn 2, dr. ir. Hans Hegt 1, prof. dr. ir. Arthur van Roermund 1 1 Eindhoven University of Technology 2 Xilinx
2 Current-steering D/A converters Applications demand performance; Errors limit performance; Small errors demand huge resources. Correction methods: Improve performance and Relax design requirements 2
3 Overview Mismatch problem; Current calibration method; MSB unary currents calibration in a 12b 250nm DAC All (MSB unary and LSB binary) currents calibration in a quad-core 12b 180nm DAC; All currents calibration in a 12b-16b flexible 40nm DAC Conclusions 3
4 Mismatch problem Elements real values deviate PDF(I) Deviation depends on: Area Tech. and Circuit parameters I MEAN I I High resolution D/A require Many and accurate elements 2 σ I K I ~ W L ( ) I Large silicon areas Large silicon areas cause Systematic errors Drop of performance INL max ~ n σ I I 4
5 Start-up calibration scheme Mismatch correction; Input offset cancellation; Two phases: φa, φb; φa: I temp =I ref -I offset ; φb: I th (i)=i temp + I offset =I ref ; I offset 1-bit ADC FSM φa: open φa: closed φb: closed φb: open I th (i) I ref I temp with I ref =ΣI bin + I LSB ; Simple logic: 8-state FSM. CALDAC(i) temp CALDAC 5
6 12bit self-calibrating DAC in 250nm CMOS, see ESSCIRC 05
7 12bit DAC implementation 12b current-steering DAC; Segmentation: 6LSB/6MSB; 63 thermo bits calibrated; 6 binary not calibrated; Reference: binary bits; 5bit signed CALDACs; CMOS 0.25µm; Vdd 2.5V. technische universiteit eindhoven 7
8 Chip micrograph 0.98mm Input drivers Latches & Decoder 1.16mm Latches & Decoder CMOS 0.25µm, 1P5M; Coarse (main) current sources designed for 10b Decoder Decoder accuracy in 0.1mm 2 ; FSM & 1bit ADC Cascodes M2, M3a, M3b Array of CALDACs Fully integrated selfcalibration in 0.3mm 2 ; Coarse current sources 5 extra pads for calibration: 4 in & 1 out; technische universiteit eindhoven 8
9 Self-calibration of MSB unary currents measurements SFDR = 68dB SFDR = 81dB Before calibration +13dB After calibration 9
10 Self-calibration of MSB unary currents measurements HD (2,3,4,5) (max) improvement +18dB SFDR improvement +13dB 10
11 Calibration potential Distribution before calibration 3.5 LSB span, σ=1.06lsb; Tech. and design tolerances; Unary currents: +4 bits Distribution after calibration 0.2 LSB span, σ=0.03lsb; Calibration step sets the span; technische universiteit eindhoven 11
12 Static performance INL [LSB] Before 10b MSB unary part dominate; INL max = 1.5LSB; Digital code LSB non-calibrated binary part dominate; INL max = 0.4LSB INL: +2b After 12b INL [LSB] Digital code technische universiteit eindhoven 12
13 Calibration of binary currents Binary no redundancy New sub-dac segmentation (M binary sets) redundancy B 1 1: I ( B)(1) + I ( i)(1) + 1 LSB: = I bin bin ref _ u i= 1 I ref _ bn B 1 2 : I ( B)(2) + I ( i)(1) + 1 LSB: = I bin ref _ bn 3: I ( B)( 1) + I ( B)(2) : = I bin bin ref _ u i= 1 I bin ref _ u equal 1/2 13
14 12b-14b self-calibrating flexible DAC in 180nm CMOS, see APCCAS 08
15 Parallel sub-dac units architecture Current-steering DACs: Parallel current sources (switch current cells), which are switched in groups to create the analog output; a) Unary (Thermometer) grouping; b) Binary grouping; c) Segmented grouping; d) Our NEW grouping: parallel sub-dacs (with an exemplary implementation). technische universiteit eindhoven 15
16 A 12-bit self-calibrated quad-core current-steering DAC recall: 1mm 2 for the presented 12b DAC (250nm CMOS) 0,2mm 2 per 12b DAC (180nm CMOS) -Large LSB binary part; -Full calibration. 16
17 Calibration of unary and binary currents, measurements INL Before calibration After calibration DNL 17
18 Calibration of all DAC currents, measurements DAC accuracy depends only on a design parameter 18
19 Calibration of all DAC currents, dynamic measurements SFDR = 80dB SFDR = 75dB 19
20 12b-16b self-calibrating flexible DAC in 40nm CMOS, unpublished yet
21 A 12b-16b self-calibrated flexible DAC in 40nm CMOS Off-chip calibration engine; Flexibility; Analog outpu N OP K L M H IJ D EF C B A N OP K L M H IJ D EF C B A N OP K L M H IJ D EF C A B N OP M K L H IJ E F D A BC Construction of the full transfer characteristic Narrow gray - sub-dacs set to full-scale 0 ; Italic - sub-dacs convert the12 LSB input data; BOLD - sub-dacs set to full-scale 1. N OP K L M H IJ F E D A BC N OP K L M H IJ F D E A BC N OP K L M H IJ D EF A BC N OP M K L J I H D EF A BC N OP M K L J I H D EF A BC Digital input O N OP MNOP N M M N L M M K L M NOP N OP O P P L K K K L K L K L J H I D EF A BC H IJ D EF A BC H IJ D EF A BC H IJ D EF A BC H IJ D EF A BC H IJ D EF A BC P N O K L M H IJ D EF A BC 15b output 13b output 14b output 12b output 12b output 0.047mm 2 per 12b sub-dac (recall: 1mm 2 for 250nm; 0.2mm 2 for 180nm)
22 Calibration of all DAC currents, INL & slow signals measurements +5 bits Before: SFDR = 59dB After: SFDR = 79dB Before: SFDR = 63dB After: SFDR = 80dB +4 bits
23 Calibration of all DAC currents, dynamic measurements
24 Conclusions Calibration: improves performance; relaxes design requirements; reduces product risks; 3 test-chip demonstrated: aggressive analog area reduction; high current accuracy; analog performance supported by digital.
25 Acknowledgements Xilinx Ireland, Mixed-Signal Design roup Financial support of Dutch Tech. Foundation STW 25
26 Thanks for attention! Discussion technische universiteit eindhoven 26
A novel Capacitor Array based Digital to Analog Converter
Chapter 4 A novel Capacitor Array based Digital to Analog Converter We present a novel capacitor array digital to analog converter(dac architecture. This DAC architecture replaces the large MSB (Most Significant
More informationPARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.2-1 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS CMOS Analog IC Design Page 10.2-2 CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationEXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.3-1 10.3 - EXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG CONVERTERS TECHNIQUE: Divide the total resolution N into k smaller sub-dacs each with a resolution of N k. Result:
More informationEE 435. Lecture 38. DAC Design Current Steering DACs Charge Redistribution DACs ADC Design
EE 435 Lecture 38 DAC Design Current Steering DACs Charge edistribution DACs ADC Design eview from last lecture Current Steering DACs X N Binary to Thermometer ndecoder (all ON) S S N- S N V EF F nherently
More informationDigital to Analog Converters I
Advanced Analog Building Blocks 2 Digital to Analog Converters I Albert Comerma (PI) (comerma@physi.uni-heidelberg.de) Course web WiSe 2017 DAC parameters DACs parameters DACs non ideal effects DACs performance
More informationNyquist-Rate D/A Converters. D/A Converter Basics.
Nyquist-Rate D/A Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = 2 1
More informationEE 435. Lecture 36. Quantization Noise ENOB Absolute and Relative Accuracy DAC Design. The String DAC
EE 435 Lecture 36 Quantization Noise ENOB Absolute and elative Accuracy DAC Design The String DAC . eview from last lecture. Quantization Noise in ADC ecall: If the random variable f is uniformly distributed
More informationA Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation
A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation Congbing Li Haruo Kobayashi Gunma University Gunma University Kobayashi Lab Outline Research Objective & Background
More informationD/A Converters. D/A Examples
D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction
More informationAnalog and Telecommunication Electronics
Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D2 - DAC taxonomy and errors» Static and dynamic parameters» DAC taxonomy» DAC circuits» Error sources AY 2015-16
More informationResearch Article Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs
Hindawi Publishing Corporation LSI Design olume 1, Article ID 76548, 8 pages doi:1.1155/1/76548 Research Article Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs Yan Zhu, 1
More informationDigital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II
Digital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II Administration: o Prayer Electricity and Electronics, Section 20.1, Digital Fundamentals: o Fundamentals:
More informationData Converter Fundamentals
Data Converter Fundamentals David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 33 Introduction Two main types of converters Nyquist-Rate Converters Generate output
More informationEE 435. Lecture 26. Data Converters. Data Converter Characterization
EE 435 Lecture 26 Data Converters Data Converter Characterization . Review from last lecture. Data Converter Architectures n DAC R-2R (4-bits) R R R R V OUT 2R 2R 2R 2R R d 3 d 2 d 1 d 0 V REF By superposition:
More informationSlide Set Data Converters. Digital Enhancement Techniques
0 Slide Set Data Converters Digital Enhancement Techniques Introduction Summary Error Measurement Trimming of Elements Foreground Calibration Background Calibration Dynamic Matching Decimation and Interpolation
More informationThe influence of parasitic capacitors on SAR ADC characteristics
The influence of parasitic capacitors on SAR ADC characteristics DMITRY NORMANOV, DMITRY OSIPOV National Research Nuclear University MEPHI ASIC Lab 59, Moscow, Kashirskoe shosse, 3 RUSSIA simplere@ya.ru
More informationLecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
More informationBehavioral Model of Split Capacitor Array DAC for Use in SAR ADC Design
Behavioral Model of Split Capacitor Array DAC for Use in SAR ADC Design PC.SHILPA 1, M.H PRADEEP 2 P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur Asst Professor, Dept. of
More informationBEHAVIORAL MODEL OF SPLIT CAPACITOR ARRAY DAC FOR USE IN SAR ADC DESIGN
BEHAVIORAL MODEL OF SPLIT CAPACITOR ARRAY DAC FOR USE IN SAR ADC DESIGN 1 P C.SHILPA, 2 M.H PRADEEP 1 P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur 2 Asst Professor, Dept.
More informationPipelined multi step A/D converters
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 04 Nov 2006 Motivation for multi step A/D conversion Flash converters: Area and power consumption increase
More informationAnalog and Telecommunication Electronics
Politecnico di Torino - ICT School Analog and Telecommunication Electronics D3 - A/D converters» Error taxonomy» ADC parameters» Structures and taxonomy» Mixed converters» Origin of errors 12/05/2011-1
More informationExtremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors
Extremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors Zhiheng Wei 1a), Keita Yasutomi ) and Shoji Kawahito b) 1 Graduate School of Science and Technology,
More informationFUNCTIONALS OF BROWNIAN BRIDGES ARISING IN THE CURRENT MISMATCH IN D/A CONVERTERS
Probability in the Engineering and Informational Sciences, 3, 009, 149 17. Printed in the U.S.A. doi:10.1017/s069964809000114 FUNCTIONALS OF BROWNIAN BRIDGES ARISING IN THE CURRENT MISMATCH IN D/A CONVERTERS
More informationDigitally Assisted A/D Conversion- Trading off Analog Precision for Computing Power
Digitally Assisted A/D Conversion- Trading off Analog Precision for Computing Power UCB IC-Seminar November 25, 2002 Boris Murmann Prof. Bernhard E. Boser Outline Motivation Research Overview Analog Errors
More informationEE 435. Lecture 26. Data Converters. Differential Nonlinearity Spectral Performance
EE 435 Lecture 26 Data Converters Differential Nonlinearity Spectral Performance . Review from last lecture. Integral Nonlinearity (DAC) Nonideal DAC INL often expressed in LSB INL = X k INL= max OUT OF
More informationHigh-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments
Erik Jonsson School of Engineering & Computer Science High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments Yun Chiu Erik Jonsson Distinguished Professor Texas Analog
More informationLecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1
Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 LECTURE 34 CHARACTERZATON OF DACS AND CURRENT SCALNG DACS LECTURE ORGANZATON Outline ntroduction Static characterization of DACs
More informationEE 435. Lecture 26. Data Converters. Data Converter Characterization
EE 435 Lecture 26 Data Converters Data Converter Characterization . Review from last lecture. Data Converter Architectures Large number of different circuits have been proposed for building data converters
More informationSuccessive Approximation ADCs
Department of Electrical and Computer Engineering Successive Approximation ADCs Vishal Saxena Vishal Saxena -1- Successive Approximation ADC Vishal Saxena -2- Data Converter Architectures Resolution [Bits]
More information8-bit 50ksps ULV SAR ADC
8-bit 50ksps ULV SAR ADC Fredrik Hilding Rosenberg Master of Science in Electronics Submission date: June 2015 Supervisor: Trond Ytterdal, IET Norwegian University of Science and Technology Department
More informationAnalog / Mixed-Signal Circuit Design Based on Mathematics
群馬大学 小林研究室 S23-1 Analog Circuits III 10:15-10:45 AM Oct. 28, 2016 (Fri) Analog / Mixed-Signal Circuit Design Based on Mathematics Haruo Kobayashi Haijun Lin Gunma University, Japan Xiamen University of
More informationPipelined A/D Converters
EE247 Lecture 2 AC Converters Pipelined ACs EECS 247 Lecture 2: ata Converters 24 H.K. Page Pipelined A/ Converters Ideal operation Errors and correction Redundancy igital calibration Implementation Practical
More informationMulti-bit Cascade ΣΔ Modulator for High-Speed A/D Conversion with Reduced Sensitivity to DAC Errors
Multi-bit Cascade ΣΔ Modulator for High-Speed A/D Conversion with Reduced Sensitivity to DAC Errors Indexing terms: Multi-bit ΣΔ Modulators, High-speed, high-resolution A/D conversion. This paper presents
More informationEE 521: Instrumentation and Measurements
Aly El-Osery Electrical Engineering Department, New Mexico Tech Socorro, New Mexico, USA September 23, 2009 1 / 18 1 Sampling 2 Quantization 3 Digital-to-Analog Converter 4 Analog-to-Digital Converter
More informationEdited By : Engr. Muhammad Muizz bin Mohd Nawawi
Edited By : Engr. Muhammad Muizz bin Mohd Nawawi In an electronic circuit, a combination of high voltage (+5V) and low voltage (0V) is usually used to represent a binary number. For example, a binary number
More informationEE 435. Lecture 29. Data Converters. Linearity Measures Spectral Performance
EE 435 Lecture 9 Data Converters Linearity Measures Spectral Performance Linearity Measurements (testing) Consider ADC V IN (t) DUT X IOUT V REF Linearity testing often based upon code density testing
More informationEE 435. Lecture 28. Data Converters Linearity INL/DNL Spectral Performance
EE 435 Lecture 8 Data Converters Linearity INL/DNL Spectral Performance Performance Characterization of Data Converters Static characteristics Resolution Least Significant Bit (LSB) Offset and Gain Errors
More informationNyquist-Rate A/D Converters
IsLab Analog Integrated ircuit Design AD-51 Nyquist-ate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD-1 Nyquist-ate MOS A/D onverters Nyquist-rate : oversampling
More informationSummary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold T/H circuits T/H combined
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. References
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution
More informationA 74.9 db SNDR 1 MHz Bandwidth 0.9 mw Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC
A 74.9 db SNDR 1 MHz Bandwidth 0.9 mw Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology,
More informationUnit 3 Session - 9 Data-Processing Circuits
Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction
More informationTop-Down Design of a xdsl 14-bit 4MS/s Σ Modulator in Digital CMOS Technology
Top-Down Design of a xdsl -bit 4MS/s Σ Modulator in Digital CMOS Technology R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla CNM-CSIC
More informationChapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability. Memory
SRAM Design Chapter Overview Classification Architectures The Core Periphery Reliability Semiconductor Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationA DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DACs
A DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DACs Abstract A design for test (DFT) hardware is proposed to increase the controllability
More informationCSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April
CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April Objective - Get familiar with the Xilinx ISE webpack tool - Learn how to design basic combinational digital components -
More informationEE 435. Lecture 25. Data Converters. Architectures. Characterization
EE 435 Lecture 5 Data Coverters Architectures Characterizatio . eview from last lecture. Data Coverters Types: A/D (Aalog to Digital) Coverts Aalog Iput to a Digital Output D/A (Digital to Aalog) Coverts
More informationEE247 Lecture 19. EECS 247 Lecture 19: Data Converters 2006 H.K. Page 1. Summary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Clock boosters (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationEE 505 Lecture 11. Statistical Circuit Modeling. R-string Example Offset Voltages
EE 505 Lecture 11 Statistical Circuit Modeling -string Example Offset oltages eview from previous lecture: Current Steering DAC Statistical Characterization Binary Weighted IL b= 1 1 IGk 1 1 I
More informationLow-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement Markus Bingesser austriamicrosystems AG Rietstrasse 4, 864 Rapperswil, Switzerland
More informationEE100Su08 Lecture #9 (July 16 th 2008)
EE100Su08 Lecture #9 (July 16 th 2008) Outline HW #1s and Midterm #1 returned today Midterm #1 notes HW #1 and Midterm #1 regrade deadline: Wednesday, July 23 rd 2008, 5:00 pm PST. Procedure: HW #1: Bart
More informationEE 505 Lecture 7. Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 7 Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling . Review from last lecture. MatLab comparison: 512 Samples
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationA DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DACs
A DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DACs 502 Rasit Onur Topaloglu and Alex Orailoglu University of California San Diego Computer
More informationWORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of
27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +
More informationSistemas de Aquisição de Dados. Mestrado Integrado em Eng. Física Tecnológica 2016/17 Aula 4, 10th October
Sistemas de Aquisição de Dados Mestrado Integrado em Eng. Física Tecnológica 216/17 Aula 4, 1th October ADC Amplitude Quantization: ADC Digital Output Formats V REF +FS RANGE (SPAN) OR FS ANALOG INPUT
More informationSpurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. University of California at San Diego, La Jolla, CA
Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL Kevin Wang 1, Ashok Swaminathan 1,2, Ian Galton 1 1 University of California at San Diego, La Jolla, CA 2 NextWave
More informationDeep Submicron CMOS and the New Era of Creativity in Analog Design
Deep Submicron CMOS and the New Era of Creativity in Analog Design John A. McNeill Worcester Polytechnic Institute (WPI), Worcester, MA mcneill@ece.wpi.edu McNEILL: CREATIVITY IN DSM CMOS MAY 3, 2006 Overview
More informationIntroduction to CMOS VLSI Design Lecture 1: Introduction
Introduction to CMOS VLSI Design Lecture 1: Introduction David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Introduction Integrated circuits: many transistors
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationOversampling Converters
Oversampling Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 56 Motivation Popular approach for medium-to-low speed A/D and D/A applications requiring
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna Today! Memory " Classification " ROM Memories " RAM Memory
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)
More informationS.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]
More informationDigital Circuits ECS 371
Digital Circuits ECS 371 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 18 Office Hours: BKD 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,
More informationCHW 261: Logic Design
CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals CHAPTER 8 Counters Slide 2 Counting
More informationEE 230 Lecture 43. Data Converters
EE 230 Lecture 43 Data Converters Review from Last Time: Amplitude Quantization Unwanted signals in the output of a system are called noise. Distortion Smooth nonlinearities Frequency attenuation Large
More informationDATASHEET AD7520, AD7521. Features. Ordering Information. Pinouts. 10-Bit, 12-Bit, Multiplying D/A Converters. FN3104 Rev.4.
DATASHEET AD720, AD72 0Bit, 2Bit, Multiplying D/A Converters The AD720 and AD72 are monolithic, high accuracy, low cost 0bit and 2bit resolution, multiplying digitaltoanalog converters (DAC). Intersil
More informationMeasurement and Modeling of MOS Transistor Current Mismatch in Analog IC s
Measurement and Modeling of MOS Transistor Current Mismatch in Analog IC s Eric Felt Amit Narayan Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences University of
More informationA Nonuniform Quantization Scheme for High Speed SAR ADC Architecture
A Nonuniform Quantization Scheme for High Speed SAR ADC Architecture Youngchun Kim Electrical and Computer Engineering The University of Texas Wenjuan Guo Intel Corporation Ahmed H Tewfik Electrical and
More informationNPSAT1 Solar Cell Measurement System
NPSAT1 Solar Cell Measurement System Presented by Captain John Salmon, USMC Space Systems Academic Group 777 Dyer Rd., Bldg. 233 Code (SP/Sd), Rm. 125 Monterey, CA 93943 (831) 656-7521 Topics NPSAT1 Overview
More informationINTRODUCTION TO DELTA-SIGMA ADCS
ECE37 Advanced Analog Circuits INTRODUCTION TO DELTA-SIGMA ADCS Richard Schreier richard.schreier@analog.com NLCOTD: Level Translator VDD > VDD2, e.g. 3-V logic? -V logic VDD < VDD2, e.g. -V logic? 3-V
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC 27001 2005 Certified) SUMMER 14 EXAMINATION Model Answer Subject Code : 17320 Page No: 1/34 Important Instructions to examiners: 1)
More informationEarly Monolithic Pipelined ADCs
Early Monolithic Pipelined ADCs Stephen H. Lewis Solid-State Circuits Research Laboratory Department of Electrical and Computer Engineering University of California, Davis CA USA 1 Pipelining Stage 1 Stage
More informationExperimental Verification of a Timing Measurement Circuit With Self-Calibration
19 th IEEE IMS3TW, Porto Alegre, Brazil Sept. 17, 2014 Experimental Verification of a Timing Measurement Circuit With Self-Calibration Kateshi Chujyo, Daiki Hirabayashi, Kentaroh Katoh Conbing Li, Yutaroh
More informationShift Register Counters
Shift Register Counters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states.
More informationAn Approximate Parallel Multiplier with Deterministic Errors for Ultra-High Speed Integrated Optical Circuits
An Approximate Parallel Multiplier with Deterministic Errors for Ultra-High Speed Integrated Optical Circuits Jun Shiomi 1, Tohru Ishihara 1, Hidetoshi Onodera 1, Akihiko Shinya 2, Masaya Notomi 2 1 Graduate
More informationChapter 8. Low-Power VLSI Design Methodology
VLSI Design hapter 8 Low-Power VLSI Design Methodology Jin-Fu Li hapter 8 Low-Power VLSI Design Methodology Introduction Low-Power Gate-Level Design Low-Power Architecture-Level Design Algorithmic-Level
More information5 Binary to Gray and Gray to Binary converters:
5 Binary to Gray and Gray to Binary converters: Aim: To realize a binary to Grey and Grey Code to binary Converter. Components Required: Digital IC trainer kit, IC 7486 Quad 2 input EXOR The reflected
More informationNJW CHANNEL ELECTRONIC VOLUME
2-CHANNEL ELECTRONIC VOLUME GENERAL DESCRIPTION NJW9 is a two channel electronic volume IC. It is included output buffer amplifier and also resistor output terminal for using external amplifier to customize
More informationPipelined ADC Design. Sources of Errors. Robust Performance of Pipelined ADCs
Pipelined ADC Design Sources of Errors Robust Perforance of Pipelined ADCs 1 Review Standard Pipelined ADC Architecture V ref CLK V in S/H Stage 1 Stage 2 Stage 3 Stage k Stage -1 Stage n 1 n 2 n 3 n k
More informationBinary Multipliers. Reading: Study Chapter 3. The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding
Binary Multipliers The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 4 6 8 2 4 6 8 3 3 6 9 2 5 8 2 24 27 4 4 8 2 6
More informationA Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs
204 UKSim-AMSS 6th International Conference on Computer Modelling and Simulation A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs Stefano Brenna, Andrea
More informationCSE241 VLSI Digital Circuits Winter Lecture 07: Timing II
CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns
More informationMinimization techniques
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation
More informationDigital Logic and Design (Course Code: EE222) Lecture 1 5: Digital Electronics Fundamentals. Evolution of Electronic Devices
Indian Institute of Technolog Jodhpur, Year 207 208 Digital Logic and Design (Course Code: EE222) Lecture 5: Digital Electronics Fundamentals Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationSTATISTICAL analog-to-digital converters (ADCs) refer
538 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 62, NO. 6, JUNE 2015 Statistical ADC Enhanced by Pipelining and Subranging Sen Tao, Student Member, IEEE, Emmanuel Abbe, Member, IEEE,
More informationAnalog to Digital Conversion. Gary J. Minden October 1, 2013
Analog to Digital Conversion Gary J. Minden October 1, 2013 1 Mapping Input Voltage to Digital Value Vhigh 0.999 1,023 Vin Vlow 0.0 0 2 Analog to Digital Conversion Analog -- A voltage between Vlow and
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Original slides from Gregory Byrd, North Carolina State University Modified by C. Wilcox, M. Strout, Y. Malaiya Colorado State University Computing Layers Problems Algorithms
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More informationDAC10* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017
* PRODUCT PAGE QUICK LINKS Last Content Update: 0/3/07 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Data Sheet : 0-Bit Current-Out DAC Data Sheet REFERENCE MATERIALS Solutions
More informationUNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018
DIGITAL ELECTRONICS SYSTEM DESIGN LL 2018 PROFS. IRIS BAHAR & ROD BERESFORD NOVEMBER 9, 2018 LECTURE 19: BINARY ADDITION, UNSIGNED BINARY NUMBERS For the binary number b n-1 b n-2 b 1 b 0. b -1 b -2 b
More information