14 Gb/s AC Coupled Receiver in 90 nm CMOS. Masum Hossain & Tony Chan Carusone University of Toronto

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1 14 Gb/s AC Coupled Receiver in 90 nm CMOS Masum Hossain & Tony Chan Carusone University of Toronto

2 OUTLINE Chip-to-Chip link overview AC interconnects Link modelling ISI & sensitivity AC Receiver architecture Implementation in 0.18 um CMOS Measured results Speed and sensitivity improvement techniques Implementation in 90nm CMOS Measured results Conclusion 2

3 Chip-to-Chip Link Overview chip-to-chip link DC coupled serial link AC coupled serial link Proximity coupling [Miura 05, Drost 04] AC coupled link over PCB trace [Luo 05] Goals : Achieve high speed Small area : small coupling capacitor High sensitivity Achieve good FOM mw/gb/s 3

4 AC Coupled Link Overview Input Pulse swing (mv pp ) Kohn ISCAS 95 Gabara JSSC 97 Kim CICC 04 Drost JSSC 04 Luo JSSC 06 Miura ISSCC 07 Luo CICC Data Rate (Gb/s) Achieves high density 3-D Integration is possible All NMOS I/O driver 1. Multi-standard integration 2. Compatible common mode 3. DC offset immune Low speed Complexity increases Have poor FOM mw/gb/s >10 mw/gb/s 4

5 AC Coupled Link Overview Input Pulse swing (mv pp ) Kohn ISCAS 95 Kim CICC 04 Miura ISSCC 07 Gabara JSSC 97 Drost JSSC 04 Luo JSSC 06 Luo CICC 06 Increase sensitivity Data Rate (Gb/s) Increase speed 0.18 um 90 nm 0.18 um 90 nm Our goal is to increase both sensitivity and speed using standard CMOS process 5

6 AC Coupled Link Modeling W/o T line 20 db/dec With 30 cm T line 6

7 ISI & Rx Sensitivity 14 Gb/s input eye 20 mv 40 mv 80 mv C = 50 ff C = 80 ff C = 150 ff Coupling capacitor area ISI sensitivity requirement Coupling capacitor area ISI sensitivity requirement 7

8 AC coupled Rx Rx Architecture Linear Rx Non-linear Rx 8b10b code Inductors Not robust Clock forwarded [Miura 05] Complexity & power Timing margin Clock distribution Data recovery without clock [Drost 04,Luo 05] Robust Low power Requires high speed hysteresis 8

9 Non-linear Clock less Rx Hysteresis Regenerates data from the transitions 9

10 Hysteresis Architecture Positive feedback Hysteresis Condition : g m R L > 1 Unstable points : M,N (large gain g m R L ) Bi-Stable points : A,B (non-linear gain) 10

11 Hysteresis Analysis Latch Mode ΔV in << V th [A-B] R L g m-in g m I tail ( ) = + ( ) v t I R v t g R out tail L in m in L ( ) ( ) V t << V v t + V in th out 0 ( ) ( ) V t V v t 0 in th out 2gm sensitivity => 2 Vth = V g m in o 11

12 Hysteresis Analysis Switching Mode ΔV in V th [B-C] R L g m-in C Tot g m t v t V exp Kv t ( ) = ( ) 0 0 in τsettle exponential Linear K g R R C = τ = g R 1 g R 1 m in L L Tot settle m L m L 12

13 Hysteresis Analysis Latch Mode ΔV in >> V th [C-D] R L g m-in g m I tail ( ) = ( ) v t I R v t g R out tail L in m in L ( ) ( ) v t >> V v t V in th out 0 13

14 Hysteresis Architecture R L C Tot g m-in g m τ = settle RLCTot g R 1 m L 14

15 Hysteresis Design Consideration R L C Tot g m-in g m Speed Improvement τ = settle RLCTot g R 1 m L Increase g m R L Increase C Tot Increase power consumption Reduce C Tot 15

16 Improved Hysteresis Architecture Condition for hysteresis : (g m2 R L2 )(g m3 R L1 ) >1 g m2 buffers node V HYST from capacitive loading R L2, R L3 distributes the output capacitance 16

17 10+ Gb/s Hysteresis Design R out R L g m3 g m-in g m2 g m-in =6.5 ms g m2 =7.1 ms g m3 =7.8 ms R L =300-ohm R out =80-ohm Hysteresis condition: Sensitivity & Logic levels: Rise time: τ = R C = 18ps HYST L Tot ( )( ) m2 L m3 OUT g R g R = > 1 2g V = 40mV; 2 V = V = 76mV m in th 0 th gm2 Power Consumption: (1.8 X10) < 20 mw 17

18 Implementation & Measurement Scope 150 ff Capacitance 600 um On chip channel Off chip termination 400 um Active area 200 um X 300 um Only single ended testing was possible Measured swing will be 25% of actual swing 18

19 10 Gb/s Measured eye 20 mv 19

20 10 Gb/s Measured sequence Error free operation verified with 127 bit pattern 20

21 14 Gb/s Measured eye Rx eye Recovered eye 50 mv 20 mv 21

22 Performance Summary Process 0.18 um CMOS Bit rate 10+ Gb/s Output Eye amplitude 80 mvp-p differential Coupling capacitor of 150 ff Power consumption 20 mw 90-nm Implementation Coupling C = 80fF : improve sensitivity Eye Amplitude > 250 mv : increase output swing Bit Rate = 15 Gb/s : improve speed 22

23 Improving sensitivity 5x Improvement in sensitivity!! 23

24 Bandwidth of the Pre-amp Slope eye [10 Gb/s] +V th -V th Recovered NRZ eye [10 Gb/s] Jitter due to pre-amp (BW = 8GHz) Pre-amp requires more BW in AC coupled receivers!!! 24

25 Bandwidth of the Pre-amp BW 8 GHz Gain 18 db Rise Time 25 ps 14 Gb/s eye diagram 16 Gb/s eye diagram How can we improve Jitter and ISI?? 25

26 Speed Improvement Improve speed by using available data transitions How to match the latency? Can we have sufficient BW? 26

27 Speed Improvement A 2 Avoωn v = 2 2 s + 2ζω ns+ ωn [Galal 02] 27

28 Speed Improvement 16 Gb/s eye diagram 16 Gb/s eye diagram V HYST V EQ 28

29 Implementation in 90-nm CMOS Each stage A V =g m R L = 1.9 Bandwidth >15 GHz Power consumption 2mW Total Gain: 7.6 > 5 Bandwidth = 11 GHz Total power = 8 mw 29

30 Implementation in 90-nm CMOS Pre-amp Pre-amp + Slope-amp 2 GHz 30

31 Implementation in 90-nm CMOS 200 mv V HYST 10 Gb/s eye -200 mv 200 mv V SLOPE -200 mv 0 100pS 200pS 300pS 400pS 31

32 Implementation in 90-nm CMOS Arrow indicates error bits Transmitted sequence Bit period 50 ps 32

33 Implementation in 90-nm CMOS 300 um Slope Amp 150 um 80 ff Pre-amp Adder Hysteresis Active area 100 um X 300 m Total power 32 mw 33

34 10 Gb/s Measured eye 50 mv Slope path was turned off at 10 Gb/s 34

35 14 Gb/s Measured eye Slope Path OFF Slope Path ON Vertical scale : 25 mv/div Horizontal scale : 50 ps/div Vertical scale : 50 mv/div Horizontal scale : 50 ps/div 35

36 14 Gb/s Measured BER Bathtub 14 Gb/s recovered eye with Hysteresis only 14 Gb/s recovered eye with Hysteresis + Slope-path 36

37 Conclusion 10+ Gb/s hysteresis circuit topology is implemented and tested in 0.18-um CMOS process (FOM 2 mw/gb/s) High speed AC coupled receiver architecture is introduced: 1. Additional slope path reduces ISI at hysteresis output 2. Additional slope path reduces jitter 14 Gb/s AC coupled receiver is implemented and tested in 90-nm CMOS FOM Gb/s FOM Gb/s 37

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