Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation


 Cornelius Robertson
 3 years ago
 Views:
Transcription
1 Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp ; sec 3.2 pp
2 Current source Ideal goal Small signal model: Open circuit RD=
3 Realizing current source: MOSFET Large signal nonideality: Compliance range Looks like current source only for V DS >V eff
4 MOSFET I D V DS characteristic for fixed V GS Smallsignal nonideality: slope in active region
5 Cause: Channel length modulation
6 Channel length modulation
7 Channel length modulation
8 Modify smallsignal model: Finite r ds current source Slope = I/ V r ds = DV DI SLOPE = DI DV = 1 r ds Ideal: zero slope fi r ds =
9 Caution: r DS(on) vs. r ds confusion! r DS(on) Triode region Large signal True resistance (VI through origin) r ds Active region Small signal Models nonideality of current source
10 Refined MOSFET Small Signal Model Add r ds in parallel with g m v gs current source at output SAME FOR Nch, Pch How to relate r ds to DC operating point? Example: g m = 2I D /V eff
11 I D  V DS Characteristic for Different V GS "Family" of curves
12 I D  V DS Characteristic for Different V GS Extrapolate backward: intersect at V DS axis
13 1/slope provides small signal resistance r ds Intersect at 1/l Slope: 1 r ds = I D 1 l fi r ds = 1 li D
14 MOSFET small signal model g m = 2I D V eff r ds = 1 li D
15 Increasing Gain Typical gain (resistive load) Lab 4 example: a v 2 Class example: a v 11.1 How to increase a v?
16 Definition Transconductance g m g m = di D dv GS
17 Transconductance g m Definition I D from Square law: g m in terms of W/L, V eff g m = di D dv GS di D dv GS = d dv GS È Í Í Î m n C ox 2 g m = m n C ox W 2 L 2 V eff W 2 L 2 ( ) V GS  V tn 3 V eff 2
18 Summary of g m expressions All equivalent! choose whichever gives easier math Can t memorize? rederive from definition of g m g m = di D dv GS g m = m n C ox W 2 L 2 V eff g m = 2I D V eff g m = 2m n C ox W L I D
19 Common source circuit (Lab 4) Setting operating point: Adjusted function generator offset for DC output at midpoint of signal swing
20 Common source circuit (Lab 4) DC operating point Chosen for halfway between rails I D =1.25mA V eff 2.0V (depends on parameters) V OUT = V DD  I D R D V OUT = +2.5V I D = V DD  V OUT R D 5V  2.5V = 2kW = 1.25mA
21 Common source circuit (Lab 4) Small signal gain magnitude = 2.5 Not impressive! g m = 2I D = 2(1.25mA) V eff 2.0V g m =1.25mA / V a v = g m R D = (1.25mA/ V)(2 kw) a v = 2.5
22 How to increase a v? Look at gain expression: a v = g m R D
23 Increase R D New R D = 10kΩ (5X old value) Problem: DC operating point Violates condition for active region: triode! DC operating point stuck at negative rail V OUT = V DD  I D R D V OUT = 5V  (1.25mA)(10kW) V OUT = 7.5V? 12.5V
24 Look at problem symbolically Use g m =2I D /V eff I D R D = DC drop on load Optimal bias at output: constrained to V DD / 2 g m = 2I D V eff a v = g m R D = 2I DR D V eff I D R D = V DD 2 I D, R D not involved! a v = V DD V eff Value of approximate symbolic approach vs. exact numerical results from simulation
25 How to increase gain (resistive load) increase V DD usually fixed by application, process decrease Veff a v = V DD V eff does increase g m but...
26 Problems decreasing V eff V eff, W/L g m expression: 2X increase in g m : 4X increase in size (can t increase I D R D ) Increased area: cost penalty Increased capacitance speed penalty g m = V eff < 200 mv: subthreshold region 2m n C ox W L I D Not square law: g m expressions invalid
27 Increase a v : Different approach Give up on resistive load... What is highest resistance?
28 Increasing a v : Different approach What is highest resistance? Infinite: open circuit Problem: no path for I D Any circuit element that: provides DC current, but is open circuit in small signal model?
29 Open in small signal model Realizing current source: MOSFET Current source!
30 Lab Circuit: MOSFET with active load Small signal model for M1 Thevenin equivalent looking into drain of M2 (see text sec. 3.1)
31 Small signal model M1 common source M2 Thevenin equivalent
32 Simplify small signal model Combine r ds1, r ds2 in parallel
33 Small signal gain v out v in = a v = g m1 ( r ds1 r ds2 )
34 Current source load: Large signal considerations Output swing limits Top: M2 crash into triode Bottom: M1 crash into triode
35 Common Source with Active Load DC Sweep Schematic
36 Active Load Simulation Result (DC Sweep)
37 Determining DC Operating Point Set small signal v in = 0
38 Determining DC Operating Point Active region: V eff determines I D Correct V IN : M1, M2 agree Example: V eff1 = 1.0V I D = 100 µa
39 If DC bias at input is wrong? Current source "disagreement" KCL crisis at output: 2µA, nowhere to go What happens?
40 If DC bias at input is wrong? Capacitance at output node V out 2µA flows into cap, charges up fi V DS1 increases fi I 1 increases fi V DS2 decreases fi I 1 decreases Changes in V DS cause changes in I D until agreement is reached: I D1 = I D2
41 How much change in V DS? Changes in V DS cause changes in I D until agreement is reached: I D1 = I D2 BUT Active region: I D is a weak function of V DS Large change in V DS for small change in I D Output very sensitive to changes in I D : Small V eff at input fi Small I D fi Requires large V DS at output for I D agreement Good: high voltage gain Bad: tricky to get correct input bias point
42 Frequency Domain Considerations Ideal opamp goals: Infinite gain Infinite bandwidth Active load helps gain What about bandwidth?
43 Start simple: Assume single C L at output (Ignore MOS capacitances for now ) Find transfer function v out /v in Frequency Domain Analysis
44 Small signal model Combine r ds1 r ds2 = r out
45 Simpler small signal model Combine r out C L into impedance Z L
46 Simplified Small Signal Model Small signal gain: v out /v in = a v = g m Z L Frequency dependence of Z L provides frequency dependence of transfer function
47 Closer Look at Z L : Impedance is parallel combination of r out, 1/sC L Z L = r out 1 sc L = sc L r out r out Z L = 1 + sr out C L
48 Let s=jw Behavior of Z L over frequency: Z L = r out 1 + jwr out C L Low frequency limit:mostly r out w << 1 r out C L fi Z L = r out 1 + jwr out C L ª r out High frequency limit: mostly C L w >> 1 r out C L fi Z L = r out 1 + jwr out C L ª r out jwr out C L ª 1 jwc L
49 Substitute in Z L v out v in = g m Z L = Transfer function g m r out 1 + jwr out C L Magnitude v out v in = g m r out 1 + ( wr out C L ) 2
50 Bode Plot of Transfer Function Magnitude v out v in = g m r out 1 + ( wr out C L ) 2 Magnitude vs. Frequency (loglog plot) Bandwidth: w 3dB
51 3dB Frequency / Bandwidth Frequency at which magnitude is 3 db down (reduced by factor 1/ 2) MAX v out v in = g m r out AT w = 0 THEN AT w 3dB, v out v in 1 = 1 2 g m r out 2 g m r out = g m r out 1+ ( w 3dB r out C L ) 2 fi w 3dB = 1 r out C L
52 Revisit Bode Plot: Gain, Bandwidth inversely related!
53 Unity Gain Frequency w T / GainBandwidth Product w T : Frequency at which magnitude is 1 Use approximation w T >> 1/r out C L 1 = g m r out ( ) ª g m r out 2 ( ) fi w = g m 2 T C L 1+ w T r out C L w T r out C L Gain x Bandwidth Product a v = g m r out w 3dB = 1 fi g m r out r out C L r GAIN out C 12 3 L BANDWIDTH = g m C L Independent of r out! Poorly controlled r out OK
54 Summary: Active Load Active load DC considerations: Output swing limited by triode crash To voltage within V eff of rail Active load good news / bad news: Good news: high gain Bad news: very sensitive to input DC bias
55 Massage small signal gain result Small signal gain Look at parallel combination Substitute expression for r ds a v = g m1 ( r ds1 r ds2 ) 1 r ds1 r ds2 = r ds1 r ds2 1 r ds1 r ds2 = l 1 I D + l 2 I D 1 r ds1 r ds2 = ( l 1 + l 2 )I D
56 Massage small signal gain result Small signal gain Substitute for g m, parallel r ds I D drops out! a v = g m1 ( r ds1 r ds2 ) a v = 2I D 1 V { eff1 ( l 1 + l 2 )I D a v = g m1 2 r ds1 r ds2 ( l 1 + l 2 )V eff1 Only l, V eff to work with
57 Improve Gain Reduce V eff Minimum 200 to 300mV (subthreshold) May not want to go that low (W,L too big) Reduce l 1, l 2 How? Where does l 1 come from?
58 Square law model with channel length mod I D = m nc ox W ( 2 L V GS  V tn ) l V DS  V eff I D sat [ ( )] I Dsat term (at pinchoff) + "extra"
59 Square law model with channel length modulation I D = m nc ox W ( 2 L V GS  V tn ) l V DS  V eff I D sat [ ( )] Fractional extra part is l(v DS V eff ) Meaning of l: Fractional change in current I D per volt change in V DS
60 What causes change? Where does l come from? Change in effective channel length L One way to reduce l: longer L Change L represents smaller fraction
61 After some semiconductor physics... Definition of l Fractional change Semiconductor physics... (see J&M p. 26) l = DI D I D DV DS DI D I D l = 1 L = DL L DL DV DS DL DV DS = 2K S e 0 qn SUB 1 2 V DS  V eff l = 1 L 2K S e 0 1 qn SUB 2 V DS  V eff K S Silicon dielectric constant 11.8 N SUB Substrate doping units /cm 3 Sanity check: 1E+14 to 1E+17 V DS from activetriode edge to large V DS Caution: consistent length units on L, N SUB, e 0
62 Substrate doping NSUB parameter Needed for SPICE Extraction procedure: 1) Calculate slope from I D V DS plot 2) r ds = 1/ slope (small signal model) 3) Calculate l 4) Calculate NSUB
63 Example V DS I D data from Lab 5 for Pchannel MOSFET:
64 1) Calculate slope from I D V DS plot 2) r ds = 1/slope (small signal model)
65 3) Calculate l I D = 482 µa l = 1 I D r ds = 1 ( 482mA) 40.2kW ( ) = V = 0.052V 1
66 4) calculate NSUB l = 1 L 0.052V 1 = 2K S e 0 1 qn SUB 2 V DS V eff 1 1E  5m ( ) ( )( 8.85E 12F /m) N SUB = 3.32E + 22 m 3 = 3.32E +16 cm 3 V DS = 4.48 V ( 1.6E 19coul)N SUB V V For CD4007, L = 10µm = 1.0E5m V DS, V eff for largest V DS data point
67 Simulation exercise Add NSUB to Nchannel, Pchannel models DC sweep for CS Amplifier with Active Load
68 Common Source with Active Load (DC) Sweep input over full range 0 to +5V
69 DC Sweep Around Operating Point
Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.
Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232242 Twostage opamp Analysis Strategy Recognize
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationStudio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS )
Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS ) 1 Simulation Review: Circuit Fixed V GS, Sweep V DS I
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 WideSwing Current Mirrors I bias I V I in out out = I in V W L bias 
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC baseemitter voltage (note: normally plot vs. base current, so we must return to EbersMoll): I C I S e V BE V th I S e V th
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics Lena Peterson 20151013 Outline (1) Why is the CMOS inverter gain not infinite? Largesignal
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationECE343 Test 2: Mar 21, :008:00, Closed Book. Name : SOLUTION
ECE343 Test 2: Mar 21, 2012 6:008:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationECE305: Fall 2017 MOS Capacitors and Transistors
ECE305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525530, 563599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More informationFrequency Response Prof. Ali M. Niknejad Prof. Rikky Muller
EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & MixedSignal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationECE342 Test 3: Nov 30, :008:00, Closed Book. Name : Solution
ECE342 Test 3: Nov 30, 2010 6:008:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More informationSwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto
SwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ualwell TrenchIsolated
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationAssignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.
Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT3 Department of Electrical and Computer Engineering Winter 2012 1. A commonemitter amplifier that can be represented by the following equivalent circuit,
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationEE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i  v o V DD v bs  v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs  C
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationEE 435. Lecture 3 Spring Design Space Exploration with applications to singlestage amplifier design
EE 435 Lecture 3 Spring 2016 Design Space Exploration with applications to singlestage amplifier design 1 Review from last lecture: Singleended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationECE 546 Lecture 11 MOS Amplifiers
ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationThe Gradual Channel Approximation for the MOSFET:
6.01  Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS V th " VGS vi  I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationLecture 04: Single Transistor Ampliers
Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 SingleTransistor
More informationECE315 / ECE515 Lecture 11 Date:
ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationECE315 / ECE515 Lecture2 Date:
Lecture2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS IV Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cutoff Linear/Triode
More informationEE105  Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105  Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:007:30pm; 060 alley
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and crosssectional area 100µm 2
More informationV in (min) and V in (min) = (V OH V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs
ECE 642, Spring 2003  Final Exam Page FINAL EXAMINATION (ALLEN)  SOLUTION (Average Score = 9/20) Problem  (20 points  This problem is required) An openloop comparator has a gain of 0 4, a dominant
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More informationChapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majoritycarrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationI. Frequency Response of Voltage Amplifiers
I. Frequency Response of Voltage Amplifiers A. CommonEmitter Amplifier: V i SUP i OUT R S V BIAS R L v OUT V Operating Point analysis: 0, R s 0, r o >, r oc >, R L > Find V BIAS such that I C
More informationVoltage AmpliÞer Frequency Response
Voltage AmpliÞer Frequency Response Chapter 9 multistage voltage ampliþer 5 V M 7B M 7 M 5 R 35 kω M 6B M 6 Q 4 100 µa X M 3 Q B Q v OUT V s M 1 M 8 M9 V BIAS M 10 Approaches: 1. brute force OCTC  do
More informationFigure 1: MOSFET symbols.
c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationSampleandHolds David Johns and Ken Martin University of Toronto
SampleandHolds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 SampleandHold Circuits Also called trackandhold circuits Often needed in A/D converters
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Threeterminal device whose voltagecurrent relationship is controlled by a third voltage
More informationLecture 18 FieldEffect Transistors 3
Lecture 18 FieldEffect Transistors 3 Schroder: Chapters, 4, 6 1/38 Announcements Homework 4/6: Is online now. Due Today. I will return it next Wednesday (30 th May). Homework 5/6: It will be online later
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationEE 330 Lecture 16. MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationLecture 310 OpenLoop Comparators (3/28/10) Page 3101
Lecture 310 OpenLoop Comparators (3/28/10) Page 3101 LECTURE 310 OPENLOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, openloop comparators Twopole, openloop
More informationEECS 105: FALL 06 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 23:30 Wednesday December 13, 12:303:30pm EECS 105: FALL 06 FINAL NAME Last
More informationElectronics II. Final Examination
f3fs_elct7.fm  The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm
More informationChapter 10 Feedback. PART C: Stability and Compensation
1 Chapter 10 Feedback PART C: Stability and Compensation Example: Noninverting Amplifier We are analyzing the two circuits (nmos diff pair or pmos diff pair) to realize this symbol: either of the circuits
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact
ESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation
More informationLecture 06: Current Mirrors
Lecture 06: Current Mirrors Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture VI 1 / 26 Lowered Resistance Looking into
More informationQuantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
More informationThe KInput FloatingGate MOS (FGMOS) Transistor
The KInput FloatingGate MOS (FGMOS) Transistor C 1 V D C 2 V D I V D I V S Q C 1 C 2 V S V K Q V K C K Layout V B V K C K Circuit Symbols V S Control Gate Floating Gate Interpoly Oxide Field Oxide Gate
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationLECTURE 380 TWOSTAGE OPENLOOP COMPARATORS  II (READING: AH ) Trip Point of an Inverter
Lecture 380 TwoStage OpenLoop ComparatorsII (4/5/02) Page 3801 LECTURE 380 TWOSTAGE OPENLOOP COMPARATORS  II (READING: AH 445461) Trip Point of an Inverter V DD In order to determine the propagation
More informationECE343 Test 1: Feb 10, :008:00pm, Closed Book. Name : SOLUTION
ECE343 Test : Feb 0, 00 6:008:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationChapter 5 MOSFET Theory for Submicron Technology
Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationSystematic Design of Operational Amplifiers
Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESATMICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 1005 061 Table of contents Design of Singlestage OTA Design of
More informationEE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More information(Refer Slide Time: 1:49)
Analog Electronic Circuits Professor S. C. Dutta Roy Department of Electrical Engineering Indian Institute of Technology Delhi Lecture no 14 Module no 01 Midband analysis of FET Amplifiers (Refer Slide
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationBipolar Junction Transistor (BJT)  Introduction
Bipolar Junction Transistor (BJT)  Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More informationECE 6412, Spring Final Exam Page 1
ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Openloop Gain: g m r o
More informationEE 330. Lecture 35. Parasitic Capacitances in MOS Devices
EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A  β β VXX Q 2
More informationII III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III  V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationLecture 7, ATIK. Continuoustime filters 2 Discretetime filters
Lecture 7, ATIK Continuoustime filters 2 Discretetime filters What did we do last time? Switched capacitor circuits with nonideal effects in mind What should we look out for? What is the impact on system
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
More informationCMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationExact Analysis of a CommonSource MOSFET Amplifier
Exact Analysis of a CommonSource MOSFET Amplifier Consider the commonsource MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel
More informationCircuits. L2: MOS Models2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. GNumber
EE610: CMOS Analog Circuits L: MOS Models (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
More informationMICROELECTRONIC CIRCUIT DESIGN Second Edition
MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113
More informationLecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER
Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multistage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationELEC 3908, Physical Electronics, Lecture 27. MOSFET Scaling and Velocity Saturation
ELEC 3908, Physical Electronics, Lecture 27 MOSFET Scaling and Velocity Saturation Lecture Outline Industry push is always to pack more devices on a chip to increase functionality, which requires making
More information