An Analysis on a Pseudo- Differential Dynamic Comparator with Load Capacitance Calibration
|
|
- Leonard Day
- 5 years ago
- Views:
Transcription
1 An Analysis on a Pseudo- Differential Dynamic omparator with Load apacitance alibration Daehwa Paik, Masaya Miyahara, and Akira Tokyo Institute of Technology, Japan 011/10/7
2 ontents 1 Topology of Dynamic omparator Analysis onditions General Analysis Gain of Dynamic Amplifier Load apacitance alibration What Decides ompensated oltage Influence of PT ariation onclusion 011/10/7
3 An Analyzed omparator oltage [] Fig. Transient waveform of a comparator [6], [7]. 011/10/7 LK Latch becomes high 1. Electric charge on the node Out int flows into gnd. urrent difference is determined by input signals The difference is integrated on Out int and becomes larger as time passes 3. The second stage regenerates the voltage difference [6] M. Miyahara, et al., ASS, 008 [7] D. Paik, et al., IEIE Trans. on Fundamentals, 010
4 Analysis onditions of a Pre-amplifier 3 Process is 90-nm MOS The size of all transistors is µm/100 nm To simplify the analysis The rising time of LK Latch to 1 ps M 3 and M 4 are in the deep triode when LK Latch is high out_int can be approximated as the drain voltage of M 1 (or M gnd In p Out p_int I DSp LK Latch M 5 M 6 M 3 M 4 M 1 M gnd gnd Out n_int I DSn gnd In n Simplify Fig. Simplified schematic of a dynamic amplifier when the LK Latch is high. gnd In p Out p_int I DSp out_int = LK Latch I M 1 M gnd gnd DS t Out n_int I DSn gnd In n 011/10/7
5 Mismatch ontribution 4 011/10/7 Fig. Mismatch contribution (Remains are.4 %. []. Giannini, et al., ISS, 008 [3] G. an der Plas, et al., ISS, 008 Mismatch is dominated by a pair of input transistors Mismatch of the second stage is suppressed by the gain of the pre-amplifier I DS is mainly decided by input transistors Mismatch changes I DS and the slew rate of Out int is also varied out_int = I DS t d out_int dt = Load capacitance calibration [], [3] is commonly used to compensate mismatch To figure out the calibration ect, the gain is required I DS
6 hannel-length Modulation 5 I DS is affected by the channel-length modulation λ is the channel-length coicient out_int = I DS t I DS = 1 µ OX W L ( 1+ λ( DS DS_sat IDS [A] Actual model (I DS w/ Ideal model (I DS w/o GS th DS_sat = the saturation condition of drain-source voltage (= DS [] Fig. Influence of the channel-length modulation. 011/10/7
7 Gain of A Dynamic Amplifier 6 G amp_trans is satisfied only when out_int If out_int falls to, G amp_trans reaches its maximum 011/10/7 G amp_trans v = v out in idst 1 = v a. = 0.15 b. = 0.0 c. = 0.5 d. = 0.30 e. = Simulation results a 5 Estimation b 4 c 3 e d DS [] in = ( 1+ λ( Gain [times] DS λ 1+ ( + (a various (b various channel length when is 0. Fig. Gain of a pre-amplifier. DS DS DS [] a. (W/L input = 6 m/300 nm b. (W/L input =.4 m/10 nm c. (W/L input = m/100 nm Simulation results Estimation Estimation ( = 0 a b c
8 Load apacitance alibration 7 Using binary-weighted PMOS varactors By turning on or off PMOS, capacitance is varied Reduce offset voltage LK Latch M 5 M 6 Out p_int M 3 M 4 Out n_int out_int outp_int outn_int out_int DB[0:N al 1] In p M 1 M In n Error is decreased gnd gnd Error apacitors for calibration (A number of unit cap. at each code = D[i] LK Latch Time LK Latch cal. Time Before calibration After calibration D[0] D[1] D[] D[N al 1] Fig. Load capacitance calibration. Fig. Error reduction by calibration ( inp = inn. 011/10/7
9 Input-Referred ompensated oltage 8 Assumption Input signal of the second stage is decided when gain reaches its maximum v in_diff_cal dout_int = d = 1+ input-referred λ Ncal 1 ( ( N ( cal ode on off (N ode Ncal 1 : N ode from the mile of calibration code N ode : calibration code N al : calibration resolution ( on off : capacitance difference of a unit PMOS varactor on : on capacitance of a unit PMOS varactor off : off capacitance of a unit PMOS varactor 011/10/7
10 Simulation Results 9 Simulation condition 1 LSB = 1.5 m = 1.0 and in_com = 0.5 Size of a unit varactor is W/L = 600 nm/100 nm Estimation : 1+ λ Ncal 1 ( ( N ( ode on off Input-referred compensated voltage [m] Fig. Input-referred compensated voltage by the capacitance calibration. 011/10/7
11 PT ariation 10 If surrounding condition is varied after compensation, calibration accuracy is degraded Process is fixed in the factory oltage and Temperature should be considered Assumption An error due to PT variation, σ _PT, is uncorrelated with offset after calibration, σ _offset0 σ _offset = σ _offset0 + σ _PT (σ _offset0 is extracted from simulation data 011/10/7
12 Input ommon-mode oltage 11 Input common-mode voltage is fluctuated Standard deviation of calibration code is σ ode σ _ PT _ OM Error due to Error due to λ = Error due to = = v = in_diff_cal in _ com 1+ λ in _ com ( ( on off σ ode λ ( ( on off σ ode λ ( = ( on off σ ode 1+ λ ( λ + λ ( + + ( λ λ( ( on off σ ode 011/10/7
13 Simulation Results 1 alibration is conducted when is 1.0, in_com is 0.5, and Temp is 7 _offset [m] SNDR decrease [db] SNDR decrease = SNDR SQNR 1 = 10log 1+ σ q Fig. Influence of input common-mode voltage on the capacitance calibration (1 LSB = 4.5 m and a number of the Monte arlo simulation is /10/7
14 Influence of Supply oltage 13 alibration is conducted when is 1.0, in_com is 0.5, and Temp is 7 Simulation results Estimation SNDR decrease σ _ PT _ = 1+ λ λ ( + λ( ( on off σ ode Supply voltage after calibration [] Fig. Influence of supply voltage on the capacitance calibration (1 LSB = 4.5 m and a number of the Monte arlo simulation is /10/7
15 Influence of Temperature 14 alibration is conducted when is 1.0, in_com is 0.5, and Temp is 7 _offset [m] σ SNDR decrease [db] _ PT _ T = + 1+ th λ ( λ + + λ ( λ + λ( ( on off σ ode ( th 1 Fig. Influence of temperature on the capacitance calibration (1 LSB = 4.5 m and a number of the Monte arlo simulation is /10/7
16 onclusions 15 A pseudo-differential dynamic comparator with load capacitance calibration is analyzed The gain of a dynamic amplifier Expressed by a ratio of to and λ of an input transistor Gain is inversely proportional to Thermal noise, input-referred compensate voltage, and influence of PT variation are analyzed A dynamic comparator is sensitive to PT variation Mainly decided by 011/10/7
17 Acknowledgements 16 This work was partially supported by MI, REST in JST, NEDO, Berkeley Design Automation for the use of the Analog FastSPIE(AFS Platform, and DE in collaboration with adence Design Systems, Inc. 011/10/7
18 References 17 [1] Tsuguo Kobayashi, et al., in IEEE Journal of Solid-State ircuits, vol. 8, no. 4, pp , Apr., [] ito Giannini, et al., in IEEE International Solid-State ircuits onference Digest of Technical Papers, pp , Feb., 008. [3] Geert an der Plas, et al., in IEEE International Solid-State ircuits onference Digest of Technical Papers, pp. 4-43, Feb., 008. [4] Michiel van Elzakker, et al., in IEEE Journal of Solid-State ircuits, vol. 45, no. 5, pp , May, 010. [5] Daniël Schinkel, et al., in IEEE International Solid-State ircuits onference Digest of Technical Papers, pp , Feb., 007. [6] Masaya Miyahara, et al., in IEEE Proceedings of Asian Solid-State ircuits onference, pp. 69-7, Nov., 008. [7] Daehwa Paik, et al., in IEIE Transactions on Fundamentals of Electronics, ommunications and omputer Sciences, vol. E93-A, no., pp , Feb., 010. [8] Asad A. Abidi, in IEEE Journal of Solid-State ircuits, vol. 41, no. 8, pp , Aug., 006. [9] John K. Fiorenza, et al., in IEEE Journal of Solid-State ircuits, vol. 41, no. 1, pp , Dec., 006. [10] Pierluigi Nuzzo, et al., in IEEE Transactions on ircuits and System I: Regular Papers, vol. 55, no. 6, pp , Jul., 008. [11] To Sepke, et al., in IEEE Transactions on ircuits and System I: Regular Papers, vol. 56, no. 3, pp , Mar., 009. [1] Akira, in IEEE Proceedings of International onference on ASI, pp. 18-1, Oct., 009. [13] Jun He, et al., in IEEE Transactions on ircuits and System I: Regular Papers, vol. 56, no. 5, pp , May, /10/7
Discrete-Time Filter (Switched-Capacitor Filter) IC Lab
Discreteime Filter (Switchedapacitor Filter) I Lab Discreteime Filters AntiAliasing Filter & Smoothing Filter f pass f stop A attenuation FIR Filters f max Windowing (Kaiser), Optimization 0 f s f max
More informationCMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators
IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater
More informationEnergy efficient A/D converter design
Energy efficient A/D converter design Akira Matsuzawa Tokyo Institute of Technology 0.06.8 A. Matsuzawa,Titech Matsuzawa & Okada Lab. Outline Overview of ADs OpAmp based AD design omparator based AD design
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationGAMINGRE 8/1/ of 7
FYE 09/30/92 JULY 92 0.00 254,550.00 0.00 0 0 0 0 0 0 0 0 0 254,550.00 0.00 0.00 0.00 0.00 254,550.00 AUG 10,616,710.31 5,299.95 845,656.83 84,565.68 61,084.86 23,480.82 339,734.73 135,893.89 67,946.95
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationNoise and Delay Uncertainty Studies for Coupled RC Interconnects
Noise and Delay Uncertainty Studies for oupled R Interconnects Andrew B. Kahng, Sudhakar Muddu and Devendra idhani ULA omputer Science Department, Los Angeles, A 995, abk@cs.ucla.edu Silicon Graphics,
More informationLecture 400 Discrete-Time Comparators (4/8/02) Page 400-1
Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators
More informationELEN 610 Data Converters
Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationAnalysis of MOS Cross-Coupled LC-Tank Oscillators using Short-Channel Device Equations
Analysis of MOS Cross-Coupled C-Tank Oscillators using Short-Channel Device Equations Makram M. Mansour Mohammad M. Mansour Amit Mehrotra Berkeley Design Automation American University of Beirut University
More informationCharacteristics of Active Devices
007/Oct/17 1 haracteristics of Active Devices Review of MOSFET Physics MOS ircuit Applications Review of JT Physics MOS Noise JT Noise MS/RF Technology Roadmap MS MOS 1., 1.0, 0.8µm 0.60, 0.50µm 0.45,
More informationECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution
ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More informationCharacteristic Symbol Value Unit Output Current I out 150 ma
LBNB ma LOAD SWITH FEATURING OMPLEMENTARY BIPOLAR TRANSISTORS NEW PRODUT General Description LMNB is best suited for applications where the load needs to be turned on and off using control circuits like
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current
More informationAnalog and Mixed-Signal Center, TAMU
Analog and MixedSignal enter, TAMU SampleandHold ircuit S/H: S H S H S H S H S t i S/H circuit o o S/H command i Block Diagram Idealized Response t Performances of S & H Realistic Transient Response: Input
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationII III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More information! Inverter Power. ! Dynamic Characteristics. " Delay ! P = I V. ! Tricky part: " Understanding I. " (pairing with correct V) ! Dynamic current flow:
ESE 570: Digital Integrated ircuits and LSI Fundamentals Lecture Outline! Inverter Power! Dynamic haracteristics Lec 10: February 15, 2018 MOS Inverter: Dynamic haracteristics " Delay 3 Power Inverter
More informationDifferential Amplifiers (Ch. 10)
Differential Amplifiers (h. 0) 김영석 충북대학교전자정보대학 0.9. Email: kimys@cbu.ac.kr 0- ontents 0. General onsiderations 0. Bipolar Differential Pair 0.3 MOS Differential Pair 0.4 ascode Differential Amplifiers
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationTechnology Trend of ADCs
Technology Trend of ADs Akira Department of Physical Electronics Tokyo Institute of Technology 008.04.5 LSIDAT A. ontents Issues of pipeline ADs Revolution of SA ADs Fight back of pipelined ADs What determines
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationDigital Microelectronic Circuits ( )
Digital Microelectronic ircuits (361-1-3021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationA 51pW Reference-Free Capacitive-Discharging Oscillator Architecture Operating at 2.8Hz. Sept Hui Wang and Patrick P.
A 51pW Reference-Free apacitive-discharging Oscillator Architecture Operating at 2.8Hz Sept. 28 2015 Hui Wang and Patrick P. Mercier Wireless Sensing Platform Long-Term Health Monitoring - Blood glucose
More informationVLSI Design I; A. Milenkovic 1
Why Power Matters PE/EE 47, PE 57 VLSI Design I L5: Power and Designing for Low Power Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationQ 1 Q 2. Characteristic Symbol Value Units GSS I D. Characteristic Symbol Value Units
BSS8DW OMPLEMENTARY PAIR ENHANEMENT MODE FIELD EFFET TRANSISTOR Features Low On-Resistance Low Gate Threshold oltage Low Input apacitance Fast Switching Speed Low Input/Output Leakage omplementary Pair
More informationECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
More informationStatic CMOS Circuits
Static MOS ircuits l onventional (ratio-less) static MOS» overed so far l Ratio-ed logic (depletion load, pseudo nmos) l ass transistor logic ombinational vs. Sequential Logic In Logic ircuit In Logic
More informationPole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview
Pole-Zero Analysis of Low-Dropout (LDO Regulators: A Tutorial Overview Annajirao Garimella, Punith R. Surkanti and Paul M. Furth VLSI Laboratory, Klipsch School of Electrical and omputer Engineering New
More informationA 74.9 db SNDR 1 MHz Bandwidth 0.9 mw Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC
A 74.9 db SNDR 1 MHz Bandwidth 0.9 mw Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology,
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationPiecewise Curvature-Corrected Bandgap Reference in 90 nm CMOS
IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Piecewise Curvature-Corrected Bandgap Reference in 90 nm CMOS P R Pournima M.Tech
More informationFrequency Detection of CDRs (1)
Frequency Detection of CDs (1) ecall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD): V in V up V up V dn -4 π -2 π +2 π +4 π φ in φ out 2V swing V f V dn K pd =
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationTHE SAR ADC basic structure is shown in Fig. 1.
INTL JOURNAL OF ELETRONIS AND TELEOMMUNIATIONS, 2013, VOL. 59, NO. 2, PP. 161 167 Manuscript received March 4, 2013; revised May, 2013. DOI: 10.2478/eletel-2013-0019 The Impact of Noise and Mismatch on
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationNyquist-Rate D/A Converters. D/A Converter Basics.
Nyquist-Rate D/A Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = 2 1
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationLecture 28 Field-Effect Transistors
Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent
More informationEECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-
EECS40 Spring 010 Lecture 1: Matching Elad Alon Dept. of EECS Offset V i+ V i- To achieve zero offset, comparator devices must be perfectly matched to each other How well-matched can the devices be made?
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationMotivation for Lecture. For digital design we use CMOS transistors. Gate Source. CMOS symboler. MOS transistor. Depletion. A channel is created
Motivation for Lecture igital Integrated ircuits iktor Öwall o see how standard gates are implemented with transistors? How does technology affect the performance, e.g. speed and power consumption? What
More informationBased on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationDESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First
More informationDelay and Power Estimation
EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------
More information2N5545/46/47/JANTX/JANTXV
N//7/JANTX/JANTXV Monolithic N-Channel JFET Duals Product Summary Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv) N. to.. N. to.. N7. to.. Features Benefits Applications
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationECE315 / ECE515 Lecture 11 Date:
ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationStep 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since
Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationSOT-363 Q 1 Q 2 TOP VIEW. Characteristic Symbol Value Unit I D. Characteristic Symbol Value Unit Drain Source Voltage V DSS -20 V
COMPLEMENTARY PAIR ENHANCEMENT MODE FIELD EFFECT TRANSISTOR Features Low On-Resistance Low Gate Threshold Voltage V GS(th) < 1V Low Input Capacitance Fast Switching Speed Low Input/Output Leakage Complementary
More informationInput-Dependent Sampling-Time Error Effects Due to Finite Clock Slope in MOS Samplers
IEICE TRANS. ELECTRON., VOL.E87 C, NO.6 JUNE 004 1015 LETTER Special Section on Analog Circuit and Device Technologies Input-Dependent Sampling-Time Error Effects Due to Finite Clock Slope in MOS Samplers
More informationECEN 610 Mixed-Signal Interfaces
ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1 Sample-and-Hold Spring 014 S. Hoyos-ECEN-610 ZOH vs. Track-and-Hold V(t)
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More information! Dynamic Characteristics. " Delay
EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic
More informationChapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
More informationSOT-563 Q 1 Q 2 BOTTOM VIEW. Characteristic Symbol Value Unit Drain Source Voltage V DSS 20 V Gate-Source Voltage V GSS ±8 V T A = 25 C T A = 85 C
COMPLEMENTARY PAIR ENHANCEMENT MODE FIELD EFFECT TRANSISTOR Features Mechanical Data Low On-Resistance Low Gate Threshold Voltage V GS(th)
More informationMetal-Oxide-Semiconductor Field Effect Transistor (MOSFET)
Metal-Oxide-Semiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n- substrate - SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationPhysics-based compact model for ultimate FinFETs
Physics-based compact model for ultimate FinFETs Ashkhen YESAYAN, Nicolas CHEVILLON, Fabien PREGALDINY, Morgan MADEC, Christophe LALLEMENT, Jean-Michel SALLESE nicolas.chevillon@iness.c-strasbourg.fr Research
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :
More information6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers
6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationLecture 14 - Digital Circuits (III) CMOS. April 1, 2003
6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationCMOS Analog Circuits
CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate
EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is
More informationHigh-to-Low Propagation Delay t PHL
High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to
More information