BSIM: Industry Standard Compact MOSFET Models

Transcription

1 BSIM: Industry Standard Compact MOSFET Models Y. S. Chauhan 1,, S. Venugopalan, M. A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A. Niknejad and C. Hu 1 IIT Kanpur, India UC Berkeley, USA Sept. 19 th, 01 ESSDERC Bordeaux, France

2 SPICE Transistor Modeling Medium of information exchange Simulation Time ~ 10μs per DC data point No complex numerical method allowed Accuracy requirements ~ 1% RMS Error after fitting Excellent Convergence Example: BSIM-CMG 5,000 lines of VA code 50+ parameters Open-source software implemented in major EDA tools

3 Compact MOSFET Modeling Approaches Threshold Voltage based Models (e.g. BSIM3, BSIM4) Fully Analytical solution (easy to implement) Fast Currents expressed as functions of Voltages W ( ) 1 I = µ C Vgs V V V L ds ox th ds ds Different equations for Sub-threshold and above-threshold Linear/saturation regions Use interpolation function to get smooth current 3

4 ompact MOSFET Modeling Approaches Surface Potential based Models (e.g. PSP, HiSim, BSIM-CMG, BSIM-IMG) V G V FB Ψ Implicit equation is solved either iteratively or analytically Might be slower than threshold voltage based models Charge based Models (e.g. BSIM5, BSIM6, EKV) Solve for charge instead of surface potential No iterations S Q = C si ox, Q si = sign( Ψ S ) ΓC Φ F + V V Faster than Surface Potential based approach with similar accuracy in charge/current ox V t e Ψ V S t 1 + Vte t CH e Ψ V S t 1 + Ψ S 4

5 Outline History of BSIM Models BSIM6 Model BSIM-CMG Model BSIM-IMG Model 5

6 BSIM1 Model History of BSIM Models Defined as an engineering model (vs a purely physical model) Focus on the implementation in circuit simulator Only a fast demonstration for DC simulation (no attention on derivatives) BSIM Model A semi-physical (semi-empirical) model Improvement over BSIM1 to include better fitting to output resistance and other first order derivatives Huge attention placed on parameter extraction methodology Still being used in many companies as internal model due to its fitting ability and simple parameter extraction 6

7 BSIM3 Model History of BSIM Models Starts as a simple physical model with very few parameters First time Continuous I-V and derivatives for fast convergence The 3 rd version (BSIM3v3) becomes industry standard Need to fit many technologies from different foundries many new parameters added Example Need to have fitting parameters Due to difficult to describe structural detail Source: Mansun Chan 7

8 BSIM4 model History of BSIM Models Started as model for statistical simulation Priority on physical effects (gate current, mobility models etc.) Added gate and body resistance networks to emphasize accuracy on RF simulation Industry standard in 000 and most widely used model by semiconductor industry Provides better fitting with more number of parameters BSIM-SOI Parallel work went on SOI modeling PD/FD/DD Real device effects same as BSIM3/BSIM4 Industry standard in 00 8

9 BSIM Family of Compact Device Models BSIM1, BSIM3 Bulk MOSFET BSIM4 BSIM5 BSIM6 New BSIMSOI Silicon on Insulator MOSFET BSIM-MG Multi-Gate MOSFET BSIM: Berkeley Short-channel IGFET Model 9

10 BSIM6: Charge based MOSFET model BSIM6 Next BSIM Bulk MOSFET model Charge based core derived from Poisson s solution Real device effects (SCE, CLM etc.) from BSIM4 Parameter names matched to BSIM4 Physical Capacitance model Short channel CV Velocity saturation & CLM Symmetry Currents & derivatives are VDS=0 Capacitances & derivatives are Provide accurate results in Harmonic Distortion simulation Continuous in all regions of operations Better Statistical Modeling using physical parameters 10

11 Gauss Law Physics of BSIM6 Model Poisson s solution for long channel MOSFET Bulk charge density is given by Combining these, we have 11

12 Physics of BSIM6 Model Defining Pinch-off potential Ψ P = Ψ S, when Q i =0 P is evaluated from implicit equation For Ψ S > few V t, we have n q is the slope factor Inversion Charge linearization *Ref.: Tsividis book & J.M. Sallese et al., Solid State Electronics 1

13 Physics of BSIM6 Model Using linearization approach and normalization No approximation to solve the charge equation compared to other models. Solved the charge equation analytically 13 ch f p i p i i q q i v q q q n n q = φ ψ ψ γ γ ln ) ln( ACM/EKV/BSIM5 ignored the circled term

14 Drain current with velocity saturation Drain current Mobility model (ensures symmetry) Using charge linearization & normalization 14 + Ψ = + = dx dq V dx d Q W I I I i T S i diff drift D µ ( ) L v V V C L W n I i V C n Q q n C Q sat t v c t ox v q D d T ox q i S P q ox i µ λ µ,,, = = = Ψ Ψ = + Ψ Ψ + = dx dq V dx d Q W dx d v I i T S i S sat v v D 1 µ µ ( ) ( ) ( ) [ ] = d s c d d s s d q q q q q q i λ

15 Normalized Q i -V G & derivatives q i vs V G 1 st derivative nd derivative Red Numerical Surf. Pot. model Blue BSIM6 model 3 rd derivative 15

16 Normalized I DS -V GS & derivatives I DS vs V G 1 st derivative nd derivative 3 rd derivative Red Numerical Surf. Pot. model Blue BSIM6 model 16

17 Mobility Model Mobility model has been adopted from BSIM4 BSIM4 where µ eff = 1+ U 0 UD EU ( UA + UC Vbsx ) Eeff + UCS q q BSIM6 is bs MV/cm 17

18 Saturation Voltage V dsat V ds to V dsat BSIM4 formulation causes asymmetry New V dsat evaluation: 18 eff t effs c L VSAT V = µ λ ) ( s c s s c dsat q q q KSATIV q = λ λ + = = 1 ln q q dsat q dsat dsat f p t dsat dsat n n q n q q V V v γ γ γ ϕ ψ DELTA DELTA s dsat ds ds dseff V V V V V + = 1/ 1

19 CV Model Physical Capacitance Model Poly-depletion & Quantum Mechanical Effect Channel Length Modulation Velocity Saturation Effect Charge conservation 19

20 Junction capacitance model BSIM4 junction capacitance model gave asymmetry Updated diode junction capacitance model for AC symmetry Transition point is at V j =0 Transition point is at V j =0.9V (pushed to strong forward bias) 0

21 Junction capacitance model BSIM6 BSIM6 BSIM4 BSIM4 BSIM6 BSIM4 Symmetry problem using old Q j New model is infinitely V DS =0 U.C. Berkeley- 1

22 I X vs V X (V D =V X & V S =-V X ) I DS -V X Gummel Symmetry di dv X X I X d 3 X 3 X dv I d X X dv I d 4 X 4 X dv I d 7 X 7 X dv I 6 5 X d I X 6 5 dvx dvx d I All derivatives are continuous at V DS =0

23 AC Symmetry test (C. McAndrew, IEEE TED, 006) Capacitance & derivatives are symmetric Capacitances and derivatives are continuous at V DS =0 3

24 Validation on Measured Data (Large device) I D V V DS =50mV I D V V DS =50mV g m V V DS =50mV I D V G in saturation g m V G in saturation I D V G in saturation I D V D g ds V D I B V G for different V DS 4

25 Validation on Measured Data (Short device) I D V V DS =50mV g m V V DS =50mV I D V V DS =50mV I D V G in saturation I D V G in saturation g m V G in saturation I D V D g ds V D I B V G for different V DS 5

26 Harmonic Balance Simulation BSIM6 gives correct slope for all harmonics Slope=1 Slope= Slope=3 Slope=4 Slope=5 6

27 BSIM6 model summary Rapid development: Released BSIM6.0.0-beta8 in Aug. 01 Charge based physical compact model Physical effects & Parameter names matched to BSIM4 Smooth charge/current/capacitance & derivatives Symmetric and continuous around V DS =0 Fulfills Gummel symmetry and AC symmetry Shows accurate slope for harmonic balance simulation BSIM4 s extraction methodology can be easily used for BSIM6 fast deployment & lower cost Under standardization review in CMC 7

28 Outline History of BSIM Models BSIM6 Model BSIM-CMG Model BSIM-IMG Model 8

29 Why next generation transistors? Gate C g Oxide Source Drain C d MOSFET becomes resistor at small L. C.Hu, Modern Semicon. Devices for ICs 010, Pearson

30 Making Oxide Thin is Not Enough Gate Source Drain Leakage Path Gate cannot control the leakage current paths that are far from the gate. C.Hu, Modern Semicon. Devices for ICs 010, Pearson

31 One Way to Eliminate Si Far from Gate Thin body controlled By multiple gates. Gate Length Gate Length Source Gate Drain Source Gate FinFET body is a thin Fin. Drain Fin Height Fin Width N. Lindert et al., DRC paper II.A.6,

32 New MOSFET Structures: Demonstration FinFET X. Huang et al. IEDM 1999 (UC Berkeley) Y. Choi et al. IEEE EDL 000- (UC Berkeley) UTBSOI C.C. Wu et al. IEDM 010 (TSMC) K. Cheng et al. IEDM (IBM / ST) 3

33 Challenges in developing a new model New Physics Fully depleted channel Quantum confinement etc. When to include them? Support Multiple Device architectures Inertia with BSIM4 Large user base Familiarity with the parameters Convergence Model behavior in extreme cases Balance Physics and Flexibility Balance Speed and Accuracy 33

34 Multi-Gate Compact Model: BSIM-MG BSIM-IMG UTBSOI BG-ETSOI BOX P+ back-gate p-sub Gate Fin BOX Gate 1 Vertical Fin IMG BSIM-CMG FinFETs on Bulk and SOI Substrates 34

35 BSIM-CMG Core Models Four device architectures Double Gate Double Gate / Trigate / FinFET Three core models Intrinsic Double Gate Core (Y. Taur et al., IEEE EDL, 004) Perturbation based DG Core for high-doping Cylindrical Gate Core Bulk and SOI Substrate Quadruple Gate Cylindrical Gate / Nanowire FET 35

36 Surface Potential Core Double Gate Solution of Poisson s equation and Gauss s Law. Poisson s equation inside the body can be written as (V ch is channel potential) N A Body doping complicates the solution of the Poisson s equation. Perturbation approach is used to solve this problem. M. Dunga et al., IEEE TED, Vol. 53, No. 9, 006 M. Dunga et al., VLSI

37 Core Drain Current Model No charge sheet approximation Drain Current (A) Na = 3e18cm -3 1m Vg = 1.5V 500µ Vg = 1.V Vg = 0.9V Drain Voltage (V) Drain Current (A) 1m 500µ Na = 3e18 cm -3 Vd = 0.1 Vd = 0. Vd = 0.4 Vd = Gate Voltage (V) 37

38 Core Capacitance Model Model inherently exhibits symmetry C ij = C V ds = 0 V Model matches TCAD data (No parameter used) Accurate short channel behavior Normalized Capacitance Na = 3e18cm -3 Vds = 1.5V Symbols : TCAD Lines : Model Cgg Csg Cdg Gate Voltage (V) Normalized Capacitance Cgg Model Symmetry Symbols : TCAD Lines : Model Cgs Csg Na = 3e18 Cdg Vg = 1.5V Cgd Drain Voltage (V) Symbols: TCAD Results; Lines: Model 38

39 Short Channel (D) Effects Quasi-D analysis Characteristic Length Symbols: TCAD Results; Lines: Model Analytical expressions model Auth and Plummer, IEEE EDL,

40 Quantum Mechanical Effects Predictive model for confinement induced Vth shift due to band splitting present in the model Effective Width model that accounts for reduction in width for a triple/ quadruple/ surround gate structure Width reduction due to structural confinement of inversion charge. (Dotted lines represent the effective width perimeter) 40

41 FinFET C fr Modeling TCAD Verification C fg : fin gate C cg =C cg1 +C cg +C cg3 : contact gate Ccg3 Tc Epi -Si Ccg Ccg1 Cfg Lext Fin Wg Gate Cfg (ff) Wfin=1um L ext =0nm L ext =5nm L ext =30nm L ext =35nm L ext =40nm Wg (nm) Ccg (ff) Both C fg and C cg agree well with D numerical simulations Ccg1 (ff) Lext = 15nm --> 40nm in steps of 5nm Tc = Wg + Tox Tox = 1nm Increasing Lext Tc (nm) Tc = 0nm --> 40nm in steps of nm Increasing Tc Wg (nm) 41

42 Real Device Effects Channel Length Modulation and DIBL Mobility Degradation Short Channel Effects Quantum Effects Velocity Saturation GIDL Current Impact Ionization current I-V Core SPE C-V Temperature Effects Fringe Capacitances Direct tunneling gate current S/D Resistance/ Parasitic Resistance Noise models Overlap capacitances 4

43 Bulk FinFET Fitting Bulk FinFETs are fabricated by TSMC T FIN =5nm, H FIN =7.5nm, EOT=.4nm Drain Current vs. V gs (Lg = 50nm) Drain Current vs. V ds (Lg = 50 nm) Output Conductance (Lg = 50nm) Drain Current (A) 50µ 40µ 30µ 0µ 10µ 0 Lg = 50nm Vds = 50mV Vds = 1.V Vds = 1.V 1n Vds = 50mV 1m 1µ 1p Drain Current (µa) Lg = 50nm V gs = 1.V V gs = 1.0V V gs = 0.8V V gs = 0.6V V gs = 0.4V Vgs = 1.V --> 0.V (in steps of 0.V) 10n Gate Voltage (V) Drain Voltage (V) Drain Voltage (V) Transconductance (Lg = 0.97μm) Output Conductance (Lg = 0.97 μm) Substrate Current (Lg = 50nm) Transconductance, g m (S) 800n 600n 400n 00n L = 0.97µm Vds = 50mV Vds = 1.V Gate Voltage (V) 10µ 8µ 6µ 4µ µ Output Conductance (S) 1m µ 1n Lg = 0.97µm Vgs = 1.V --> 0.4V (in steps of 0.V) 1p Drain Voltage (V) Output Conductance (S) Substrate Current (A) 100p 10p Lg = 50nm µ Lg = 50nm Vds = 1.V 1p Gate Voltage (V) Symbols: Data Lines: Model 43

44 Asymmetric Vertical Nanowire fittiing Lg=10nm, D=80nm, Tox=3nm Symbols: Data Lines: Model Drain Current vs. V gs Drain Current vs. V ds Transconductance Output Conductance Temperature Dependence 44

45 Symmetry / Continuity Tests Model passes both DC and AC Symmetry Tests Drain Current Capacitances (C gg and C sd ) C.C.McAndrew, IEEE TED, Vol. 53, No. 9,

46 BSIM-CMG Summary BSIM-CMG is industry standard production level model standardized in March 01 Available in major EDA tools Released BSIM-CMG in Sept. 01 Physical, Scalable Core Models for multiple device architectures Supports both SOI and Bulk Substrates Many Real Device Effects captured Validated on Hardware Data from different technologies 46

47 Outline History of BSIM Models BSIM6 Model BSIM-CMG Model BSIM-IMG Model 47

48 Device Structure & BSIM-IMG Asymmetric structure Different Gate Work-functions Allows dissimilar Gate Potentials Different Oxide thickness and Material! Captures important features V th tuning through Back-Gate Multi-V th technology Vfg Front Gate Tox1 Source x y N A Tsi Drain Vs Back Gate Tox Vd Vbg 48

49 Computationally Efficient Core Efficient Non-iterative Surface Potential calculation Surface potential needs to solved at least twice - Source and Drain side Obtain ψ s / Q is and ψ d / Q id FAST S. Khandelwal et al., "BSIM-IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control", IEEE TED, Aug. 01. Cumulative Percentage BSIM-IMG Ψ s Iterative Method A Iterative Method B Computational Time (µs) 49

50 Results: Surface-Potential Comparison with Numerical Solution Absolute Error (<nv) 50

51 Volume Inversion Preserves Important Property like Volume Inversion In sub-threshold (Low field), the charge density Qi is proportional to the body thickness Tsi T oxb = 10μm Charge Density, Q i (coul/m ) E-3 1E-4 1E-5 1E-6 Tsi = 5nm Tsi = 10nm Tsi = 0nm 1E-7 5 1E E-9 1 1E E-11 Ψ sf (V) 1E Q i Ratio Front Surface Potential, Ψ sf (V) T si

52 Drain Current Model I ds W Qinv, s + Qinv, d = µ s1, d s1, s inv, s inv, d L q Drift Diffusion ε sies η = Q + ε E inv si kt ( ψ ψ ) + η ( Q Q ) s Q inv : inversion carrier density E s : back-side electric field s1 : front-side surface potential No Charge-sheet Approximation 15 Very high accuracy Drain Current (µa) Vfg = 0.v, 0.4v, 0.6v, 0.8v, 1.0v Charge sheet This Work TCAD Drain Voltage (V) Error Relative to TCAD (%) Charge-sheet Model This Work Front Gate Voltage (V) 5

53 Length Dependent γ Model Capacitive coupling ratio Front Gate Gamma (γ) Tsi=8nm Tbox=4nm Vds = 1V TCAD Model Gate Length (µm) γ degraded at short channel C ox1 C si C ox Back Gate Drain Current (A) C d1 (L eff ) C d (L eff ) Source / Drain W=50 x 0.5µm L = 50 nm V bg = 10v, 15v, 0v, 5v Cross: Measurements Lines: BSIM-IMG Gate Voltage (V) Captures V bg effect in I-V 53

54 QM Effect: Inv. Charge Centroid Model V dd = 0.9 V ; V fb = 8 mv T BOX = 140nm; T si = 6nm; N sub = 1e16 cm -3 BOX p-sub EOT phys = 0.65nm T inv = 1.13nm EOT eff = 0.95nm V gs Cgtotal (ff/µm^) SCHRED_Clas BSIM-IMG SCHRED_QM 0 BSIM-IMG Fitted Gate Voltage (V) 54

55 Thermal Node: Rth/Cth methodology Self Heating Model T Relies on Accurate physical modeling of Temperature Effects in the model Drain Current (µa) Without Self Heating With Self Heating Vgs=1.0 Vgs= Vgs=0.6 Vgs= Vds (V) M. A. Karim et al., Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs, to appear in IEEE Electron Device Letters,

56 Global Extraction : I d -V gs at different V bg Vbg=0, -0., -0.5, -0.8, -1.1 V; Vds=50mV TBOX=10nm L= 11 um, 1.1 um, 70nm, 60 nm, 40 nm, 30 nm 56

57 Gummel Symmetry Test Drain Current Symmetry 0.0 V fg =0. AC (charge) Symmetry dδ cg / dv x (V -1 ) 0 16 V bg =0 V fg =0. 1 V fg =0.6 8 V fg =0.8 V fg =0.4 4 d 3 I x / dv x 3 (A / V 3 ) dδ csd / dv x (V -1 ) 0.00 V fg = V fg = V fg =0.8 V bg = Vx (V) Analog /RF Ready 10 V bg =0 8 V fg =0. 6 V fg =0.6 V 4 fg =0.8 V fg = Vx (V) C. C. McAndrew, TED Vx 57

58 BSIM-IMG: Current Status & Future Production level UTBSOI Model Physical and Scalable for FDSOI devices Plethora of Real Device Effects model Release of BSIM-IMG 101 (April 011) Available in different EDA tools Already being used by SOI Consortium Under standardization at Compact Model Council Verilog-A code and Well-documented Manual Next BSIM-IMG Release Oct

59 Agilent, Cadence Synopsys, Proplus Mentor Graphics SRC/GRC EPFL Acknowledgement Models users SOITEC EDA Vendors LETI Maria-Anna, Christian Enz IIT Kanpur Global Foundries Pragya Kushwaha Chadan Yadav ST Microelectronics Analog Devices Texas Instruments IBM TSMC All other CMC Members Shantanu Agnihotri 59

60 BSIM6 Publications & References S. Venugopalan, K. Dandu, S. Martin, R. Taylor, C. Cirba, X. Zhang, A. M. Niknejad, and C. Hu; A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6 ; IEEE CICC, Sept. 01. M.-A. Chalkiadaki, A. Mangla, C. C. Enz, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Niknejad, C. Hu, "Evaluation of the BSIM6 Compact MOSFET Model s Scalability in 40nm CMOS Technology", IEEE ESSDERC, Sept. 01. Y. S. Chauhan, M. A. Karim, S. Venugopalan, S. Khandelwal, P. Thakur, N. Paydavosi, A. B. Sachid, A. Niknejad and C. Hu, "BSIM6: Symmetric Bulk MOSFET Model", Workshop on Compact Modeling, June 01. Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, "BSIM Models: From Multi-Gate to the Symmetric BSIM6", MOS-AK Noida, March 01. Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, T. Krakowsky, G. Coram, S. Cherepko, S. Sirohi, A. Dutta, R. Williams, J. Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, W. Grabinski, C. Enz, "Transitioning from BSIM4 to BSIM6", MOS-AK Noida, March 01. Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, G. Coram, S. Cherepko, J. Wang, S. Sirohi, J. Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, F. Krummenacher, W. Grabinski, C. Enz, "BSIM6: Symmetric Bulk MOSFET Model", The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad and C. Hu, "BSIM6: Next generation RF MOSFET Model", MOS-AK Workshop, Washington DC, USA, Dec

61 BSIM-MG Publications & References S. Venugopalan et al. Compact models for real device effects in FinFETs ; IEEE SISPAD, Sept. 01. M. A. Karim et al., "Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs, IEEE Electron Device Letters, 01. S. Khandelwal et al., "BSIM-IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control", IEEE Transactions on Electron Devices, Aug. 01. D. D. Lu et al., A Computationally Efficient Compact Model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates", Solid State Electronics, 011 S. Venugopalan et al., BSIM-CG: A Compact Model of Cylindrical/Surround Gate MOSFETs for Circuit Simulations ; Solid State Electronics, Jan 01. S. Venugopalan et al., Modeling Intrinsic and Extrinsic Asymmetry of 3D Cylindrical Gate/ Gate-All-Around FETs for Circuit Simulations ; IEEE NVMTS, China, Nov.011 D. D. Lu et al., Multi-Gate MOSFET Compact Model BSIM-MG", a chapter in Compact Modeling Principles, Techniques and Applications, Springer 010 D. D. Lu et al. "A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation", IEDM 007. M. V. Dunga et al., BSIM-MG: A Compact Model for Multi-Gate Transistors, a chapter in FinFET and Other Multi-Gate Transistors edited by J. P. Colinge, 005. M. A. Karim et al., "BSIM-IMG: Surface Potential based UTBSOI MOSFET Model", Nano- Terra Workshop, Switzerland, Dec S. Venugopalan et al., "BSIM-CMG: Advanced FinFET Model", Nano-Terra Workshop, Switzerland, Dec Thank You 61