Semiconductor Integrated Process Design (MS 635)
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1 Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee - Office: 응용공학동 #4306, Tel: # keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:00-2:15 #2425 Office hour: Tues & Thur 10:30-12:00 TA: Hee Seung Wang (hswang@kaist.ac.kr) Objective: To present the theoretical and practical background of modern semiconductor process and device design. The students understand the basic theory, terminology and TCAD simulation of advanced electronic devices and process. Course Policies: Attendance: Two uninformed absences are allowed and will not be used for grades 1 Textbook: Mainly Handouts References 1. Physics of Semiconductor Devices, 3rd Edition, Simon M. Sze, 2. Silicon VLSI Technology: Fundamentals, Practice, and Modeling, (2nd Edition) James D. Plummer Grading: Final 40%, Quiz 20%, HW (~4 simple ones)15%, Project 15%, Attendance 10% Project: A project will be assigned to groups (2 people each). Using Silvaco TCAD simulation tool, a short paper should be turned in. The paper should include the contents of the followings: research background, basic device theory, and simulation results. Prerequisite: Introduction to Semiconductor Device
2 Semiconductor Integrated Process Design (MS 635) Course Schedule Week Topic Week Topic 1 Overview of MOSFET theory 2 Device Physics for the Submicron MOSFET: Scaling theory & Short channel effect 3 Emerging Devices: SOI, FINFET, Trigate, GAA, Vertical SGT 4 Introduction to TCAD Device Physics 5 Semiconductor Device Design using TCAD Simulation 6 Semiconductor Device Design using TCAD Simulation 7 Memory Device Design (SGT DRAM) 8 Quiz 9 CMOS Process Integration 10 Unit Process: Diffusion, Doping & Oxidation 11 Introduction to TCAD Process Simulation 12 Semiconductor Process Design using TCAD Simulation 13 Unit Process: Lithography 14 Unit Process: Wet & Dry Etch 15 Unit Process: Thin Film 16 Final exam Home Page: (Passwordà) 2
3 How to Design Semiconductor in Industry Device engineer: Architecture design Integration engineer: Handling entire process - Target performance - Device structures - Material - Doping - Architecture optimization - Process flow chart - Process flow chart - Mask Layout - Lot handling - Optimization of device condition - Split (channel doping, strain engineering, junction technology etc) TCAD engineer: Device and Process Simulation Process engineer: individual process optimization - IV & CV curve estimation - Short channel effects - Doping optimization - Architecture optimization - Plasma etching - Lithography - Electronic materials (thin film, TEM analysis) - Ion implantation - Metallization (Cu, barrier) - Packaging 3 cf) Circuit engineer
4 What is TCAD Simulation? In industry, you can not design the semiconductor device architecture nor process flow by basic theory. à Instead, industry uses expensive and professional simulation program (TCAD) to design semiconductor. Device simulation Process simulation 4
5 Term Project Repeat paper Announcement 5 1. HW: Read Decananometer SGT paper and summarize in one A4 paper. Due date: 20 Sept 18
6 MOSFET I DS Transfer curve Vd=1V VTh V G Id-Vd curve Saturation region 6
7 PN Junction Depletion region dv e = - 0 dx Contact potential Built-in potential Diffusion - + J diff =J drift 7 Electric field builds up to the point where the net current is zero at equilibrium. Concept of Potentialà General physics
8 1) 2) 8
9 3) This electric field causes drift current 4) This electric field also changes band diagram caused by the equation of Poisson s Equation de(x) = q ( p -n+ N ) Fermi energy levels get closer a Î d N dx 9
10 10 p n n N p i A 2 ; = = n n p N n i 2 D ; = = n i n p» = Depletion region 5) PN junction at equilibrium / d N a N q V x x W s p n ú ú û ù ê ê ë é ø ö ç ç è æ + = + = ε d a d p N N WN x + = d a a n N N WN x + =
11 Current Flow at PN Junction Pà+ Nà- Most voltage drop will occur across the depletion region since the depletion region is the most highly resistive. Voltage bias in the direction of reducing the barrier height: FORWARD Voltage bias in the direction of raising the barrier height: REVERSE Notice that the Fermi energy is not continuous any more. Hole diffusion Hole drift Electron diffusion Electron drift 11
12 Forward bias of PN Junction Thermal equilibrium: BD and carrier flux Forward bias 12
13 Reverse bias of PN Junction Thermal equilibrium: BD and carrier flux Reverse bias Reverse bias the barriers becomes so large that no electrons in n side conduction band have enough energy to surmount it. Barrier height is increased to q( V Þ The number of electrons able to jump o + V a ). 13 over the barrier decreases by the factor of e -qv a / kt.
14 MOS Band Diagram i) Real MOS case p- ii) To simplify the case, we assume F m = F s à No difference in work function This is a Flat Band (FB) condition. Although it is not realistic, this assumption will simplify our approach.
15 MOS Band Diagram Under Bias Now if we apply a voltage, voltage drop occurs both across the oxide (linear drop) and near the surface of the Si (bending). p Hole
16 Threshold Voltage If a bias is applied MOS, the voltage drop occurs across oxide and the depletion region of Si. V = g V i + f We define the onset of a strong inversion as follows: S f ( inv) s f : Potential at the surface of f s F :(E = 2f i - F E f = V i 2 = kt q - Q C ln i s N n the Si ) in the neutral region i a Thus, threshold voltage required for strong inversion is V T Q = - C d i + 2f Onset of strong inversion, there are negligible inversion charge (Q s =Q d ) F
17 Realistic Threshold Voltage Work function difference So far, we assume that Ef of Si and metal are equal. But this is not true for the most cases. In addition to work function difference, MOS structure is affected by charges in insulator and interface. So we need to compensate this assumption. Interface charge V = f - FB ms Q C i i V T = f = f ms ms Q - C i i 1 - C i Q - C ( Q i d i + + 2f F 2qN e (2f )) + 2f A si F F (a) (b)
18 MOSFET Operation Mechanism Current flow vs voltage potential is same as water flow vs potential energy. Water flows from high potential energy to low potential energy. When V SB = 0, V DB = 0 and V GB = 0 volt Source Gate Drain Gate Source (n + ) Drain (n + ) p fbi Channel fbi Reference level (bulk) ; assume that V B = ground n + p Water or Electrons 18
19 MOSFET Operation Mechanism Inversion When V SB = 0 V, V DB = 0 V and V GB > V T Source Gate Drain =0 fbi f = 2f + D S f F S fbi Reference level (bulk) ; assume that V B = ground Channel Water or Electrons No current flows. Inversion layer is formed, but no potential difference à no current flow 19
20 MOSFET Operation Mechanism When V SB = 0 V, V DB = V DB1 V and V GB > V T (V DB1 <<V GB ) Source fbi Gate Drain fbi Reference level (bulk) ; assume that V B = ground V DB1 Current flows. o Non-saturation (Linear region) Inversion layer is formed & potential difference is existed. à Current flows 20
21 MOSFET Operation Mechanism When V SB = 0 V, V DB = V DB2 V and V GB > V T (where V DB2 >V DB1 ) Source fbi Gate Drain fbi Reference level (bulk) ; assume that V B = ground V DB2 Current is influenced by drain voltage. Inversion layer is formed & potential difference is existed. àwater channel is narrowed near drain region. 21
22 MOSFET Operation Mechanism When V SB = 0 V, V DB = V DBsat and V GB > V T Source fbi Gate Drain fbi Reference level (bulk) ; assume that V B = ground V DBsat Pinch off. Pinch off. o On-set of Saturation 22
23 MOSFET Operation Mechanism When V SB = 0 V, V DB > V sat and V GB > V T fbi Source Gate Drain fbi Reference level (bulk) ; assume that V B = ground V DBsat V DB Pinch off. 23
24 Flat Band condition, V DS =0 24
25 Inversion condition, V DS =0 25 Under an inversion condition, Si near the surface becomes n-type. So, current path from drain to source will be n + ànàn +.
26 Inversion condition, Small V DS 26
27 Inversion condition, pinch-off with depletion 27
28 No class 30 Aug 1 Nov (Total missing time =150 min) 29 Nov (Undergraduate Entrance Interview) Class time (From 4 Sept) Tues & Thursday : 12: 50 ~ 2:20 Total 10 x 15 min = 150 min (15 min plus) 28
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