Compact Modeling of Semiconductor Devices: MOSFET

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1 Compact Modeling of Semiconductor Devices: MOSFET Yogesh S. Chauhan Assistant Professor and Ramanujan Fellow Nanolab, Department of Electrical Engineering IIT Kanpur Homepage

2 Outline Compact Modeling MOSFET Drain Current in MOSFET Smoothing Functions Terminal Charges Scaling FinFET Yogesh S. Chauhan, IIT Kanpur 2

3 Compact Modeling or SPICE Modeling Good model should be Accurate: Trustworthy simulations. Simple: Parameter extraction is easy. Balance between accuracy and simplicity depends on end application Medium of information exchange Excellent Convergence Simulation Time ~µsec Accuracy requirements ~ 1% RMS error after fitting Example: BSIM6, BSIM- CMG Yogesh S. Chauhan, IIT Kanpur 3

4 Industry Standard Compact Models Standardization Body Compact Model Coalition CMC Members EDA Vendors, Foundries, IDMs, Fabless, Research Institutions/Consortia CMC is by the industry and for the industry Yogesh S. Chauhan, IIT Kanpur 4

5 Drain What is MOSFET? MOSFET is a transistor used for amplifying or switching electronic signals. Gate Source Yogesh S. Chauhan, IIT Kanpur 5

6 Introduction to MOSFET Building block of Gb memory chips, GHz microprocessors, analog, and RF circuits. Basic MOSFET structure and IV characteristics Polysilicon gate & SiO 2 Yogesh S. Chauhan, IIT Kanpur 6

7 How can we simulate MOSFET based We need circuits? Currents II dddd = WW. QQ iiiiii. νν = WW. QQ iiiiii. μμ nnnn EE II dddd = WW. CC oooo VV gggg VV tt. μμ nnnn dddd ccc dddd Charges (for capacitance) Yogesh S. Chauhan, IIT Kanpur 7

8 Energy Band Diagram in Equilibrium Yogesh S. Chauhan, IIT Kanpur 8

9 Depletion and Inversion Surface is depleted of holes Surface is inverted Yogesh S. Chauhan, IIT Kanpur 9

10 Threshold Condition and Threshold Voltage Threshold (of inversion): n s = N a, or (E c E f ) surface = (E f E v ) bulk, or A=B, and C = D ψψ sstt = 2φφ bb = 2 kkkk qq llll V ox = qn a 2ε 2φ C ox s B NN aa nn ii Amount of band bending at surface is called Surface Potential. VV gg = VV ffff + ψψ ss + VV oooo V t = V g at threshold = V Yogesh S. Chauhan, IIT Kanpur 10 fb + 2 φ + B qn a 2ε 2φ C ox s B

11 Inversion Layer Charge Applied Gate Voltage V g = V = V = V t fb + fb Q C + 2φ inv ox B 2φ + B Q C qn dep a ox C ox s Q C 2ε 2φ inv ox B Q C inv ox Inversion Layer Charge ox ( Vg Vt Yogesh S. Chauhan, IIT Kanpur 11 Q inv = C )

12 MOSFET V t and the Body Effect Two capacitors => two charge components C dep = ε s W d max C oxe Q = C ( V V ) + C inv oxe gs t dep V Cdep = C oxe( Vgs ( Vt + Vsb)) C oxe sb C dep Redefine V t as C V ( V ) t sb dep = Vt 0 + Vsb = Vt 0 Coxe + αv sb Yogesh S. Chauhan, IIT Kanpur 12

13 Uniform Body Doping In earlier generations of MOSFETs, the body doping density is more or less uniform and W dmax varies with V sb. In that case, the theory for the body effect is more complicated. V t = V t0 + qn C a oxe 2ε s ( 2φ B + V sb 2φ B ) V t0 + γ ( 2φ B + V sb 2φ B ) γ is the body-effect parameter. Yogesh S. Chauhan, IIT Kanpur 13

14 Threshold Voltage Modeling Long/Wide Channel Model With Uniform Doping V FB =flat band voltage V TH0 =threshold voltage of device at zero substrate bias γ is the body bias coefficient given by Yogesh S. Chauhan, IIT Kanpur 14

15 Threshold Voltage Modeling As channel length gets shorter V th shows a greater dependence on Short-channel effect Higher Off Current Leakage DIBL Higher Off Current Leakage at high V ds Yogesh S. Chauhan, IIT Kanpur 15

16 Threshold Voltage Modeling The complete V th model implemented in SPICE as Yogesh S. Chauhan, IIT Kanpur 16

17 Surface Mobility V g = V dd, V gs = V dd V ds > 0 I ds I ds = W Q v = WQ µ E = WQ inv inv µ ns V ds / L inv ns = WC oxe ( V gs V t ) µ ns V ds / L Scattering mechanisms Phonon scattering Coulomb scattering Interface roughness scattering Yogesh S. Chauhan, IIT Kanpur 17

18 Surface Mobility Mobility is a function of the average of the fields at the bottom and the top of the inversion charge layer, E b and E t. From Gauss s Law, E b = Q dep /ε s V = V + ψ + V g fb s ox V = V + φ Q / C t fb st dep oxe Therefore, E t = ( Q = E b C = ε oxe s dep Q ( V E inv gs b + Q C = ε inv s V oxe s ) / ε / ε = fb ( V V φ st ) s E b t φ ) C + ε st s fb oxe ( V gs V t ) 1 2 ( E b + E t ) = C oxe 2 ε s ( V gs + V C oxe ( V + gs V + t 2 ε s V + V V = t 2 V fb 0. 2 V ) 2 φ ) NMOS with n+ poly-si gate V fb -0.5 and ψ st 0.4 gs t Yogesh S. Chauhan, IIT Kanpur 18 6 T oxe st

19 Universal Surface Mobilities Surface mobility (cm 2 /V-s) Surface roughness scattering is stronger (mobility is lower) at higher V g, higher V t, and thinner T oxe. Empirical fitting Yogesh S. Chauhan, IIT Kanpur 19

20 Mobility Modeling in BSIM4 E E E eff eff eff = = = V V V gs 6T gs gsteff + V oxe 6T t Vt + 2V 6T oxe oxe + 2V t t Yogesh S. Chauhan, IIT Kanpur 20

21 Current in subthreshold region Subthreshold conduction Transistor is in depletion Surface potential is determined by depletion under the gate, which is constant everywhere (ψ S ψ sa ). ψ sa ψ sa = 2 γ γ + + V 2 4 GB VFB 2 Q ' I = 2 2qε N 2φ f s A + V ' CB φte V V nφ GC t M I ( x) = ds µ eff WQ i dv dx CB Yogesh S. Chauhan, IIT Kanpur 21

22 Current in subthreshold region Integrating from source to drain, I I ds ds L 0 I ds I = µ ds L ( x) dx = µ eff W L 0 V V DB SB Q eff i W dv Q CB i dv V V DB GB VCB VTH W 2qε = sn A nφt µ eff φt e dvcb L ' V 2 2φ + SB f VCB V GS VTH VGD VTH VGS VTH VDS nϕt nϕt = I e e 0 = nϕt nϕt I ds I0e 1 e CB Yogesh S. Chauhan, IIT Kanpur 22

23 Current in subthreshold region I ds 1 e VGS VTH VDS = nϕt nϕt I0e Note V TH is a function of body bias. If V B increases in negative direction, V TH increases. V TH V ( φ + V ) = T 0 + γ 0 SB φ0 Yogesh S. Chauhan, IIT Kanpur 23

24 Subthreshold slope It is defined as the amount of gate voltage required to change the gate current by 1-decade. S = d dv GS ( log I ) ds At room temperature C C S dep dep ( 25.85) (2.30) 1 60mV Cox C = ox Yogesh S. Chauhan, IIT Kanpur 24

25 Drain Current and Q inv in MOSFET Channel voltage V c =V s at x = 0 and V c =V d at x = L. Q ' I ' ( V V ) = C ( V V αv ) ' = Cox GC TH ox GC t0 cb Q inv = C ox (V gs V cs V t0 α (V sb +V cs ) = C ox (V gs V cs (V t0 +α V sb ) α V cs ) Q inv = C ox (V gs mv cs V t ) m 1 +α = 1 + 3T oxe /W dmax 1.2 m is called the body-effect factor or bulk-charge factor. Yogesh S. Chauhan, IIT Kanpur 25

26 Drain Current Calculation Now, I ds = WC oxe (V gs mv cs V t )μ ns dv cs /dx Integrating the above equation over the channel length L, gives the current voltage relation as follows: L V ds Idsdx = WCoxeµ ns ( Vgs mvcs 0 0 V t ) dv cs I ds L = WC oxe µ ns (V gs V t mv ds /2)V ds I ds = µ ns C oxe W L V gs V t m 2 V ds V ds Yogesh S. Chauhan, IIT Kanpur 26

27 I-V characteristics di dv W L ds = ds 0 Coxe μns(vgs Vt mvdsat ) = 0 Linear Region Saturation region V dsat = V gs V m t V ds V dsat Linear Region Drain current in saturation regio V ds V dsat Saturation region W 2 Idsat = Coxeµ ns ( Vgs Vt ) 2mL transconductance: g m = di ds /dv gs W gmsat = Coxeµ ns ( Vgs Vt ) ml Yogesh S. Chauhan, IIT Kanpur 27

28 I-V characteristics What happens at V ds =V dsat & why I ds remains constant beyond V dsat At V ds =V dsat, Q inv near the drain end of the channel becomes zero! i.e. Pinch off. I ds = WQ inv µ ns E (Large E and and negligible Q inv ) At V ds >V dsat, A very short region near the drain end where the Q inv = 0, a very high electric field exist due to the drop of the additional V ds - V dsat. Yogesh S. Chauhan, IIT Kanpur 28

29 Velocity Saturation At low E ν = μ ns E The inversion-layer electron velocity saturates at high field ν = µ ns ξ 1+ ξ / ξ sat ν = µ ns ξ sat ns sat, ξ ξ sat is the field at which velocity saturation becomes dominant. Yogesh S. Chauhan, IIT Kanpur 29, ξ << ξsat ν = ν = µ ξ ξ sat

30 Velocity Saturation and I-V Model I ds = WQ inv ν ν = µ ns ξ 1+ ξ / ξ sat I ds = WC oxe ( V mv V ) gs cs t µ 1+ ns dv dv dx cs cs ξ dx sat 0 L I ds dx = 0 V ds WC oxe µ ns (V gs mv cs I V ) t ds ξ sat dv cs Drain current when ν ν sat I ds = W L C sat Yogesh S. Chauhan, IIT Kanpur 30 oxe m µ ns Vgs V 2 Vds 1+ Lξ ds V t V ds

31 Velocity Saturation and I-V Model If L is large then V Lξ W m I ds = Coxeµ s ( Vgs Vt Vds ) V L 2 Effect of velocity saturation on I ds : ds sat will be negligible, then: ds It is called the long channel I-V model I ds = (Long channel I ds )/( In short channel devices 1 V ds + ) Lξsat Vds 1 + >1 Lξ sat Yogesh S. Chauhan, IIT Kanpur 31

32 Velocity Saturation and I-V Model I I Drain current for V ds V dsat 2 ( V V ) I dsat W C 2mL gs t = oxeµ ns =Long channel I Vgs V dsat /( t 1+ Very short channel case: dsat dsat E = Wv sat Wv L << V C sat sat C oxe oxe V mξ gs t ( Vgs Vt mesatl) ( V V ) gs I dsat is proportional to V gs V t rather than (V gs V t ) 2, Not as sensitive to L as than long channel case ( 1/L). t sat L Vgs Vt 1+ ) mξ L sat Long channel case: I dsat E sat L >> V gs W Coxeµ 2mL V ns t ( V V ) 2 gs t Yogesh S. Chauhan, IIT Kanpur 32

33 I-V Characteristics Long Channel Short Channel I ds (V gs -V t ) 2 I ds V gs -V t DITS +CLM+ DIBL Yogesh S. Chauhan, IIT Kanpur 33

34 I-V Characteristics Curves for a particular gate voltage Curves for a different gate voltages Yogesh S. Chauhan, IIT Kanpur 34

35 Compact Modeling is Art based on Science Yogesh S. Chauhan, IIT Kanpur 35

36 Smoothing function and I-V Model Smoothing function is required for a smooth transition between two functions. This stems from the need to have a single equation valid in all regions of operation. BSIM3 introduced use of smoothing functions to get single equation valid in all regions of biases. This gave continuous and smooth I-V and C-V making it popular model for analog design. Yogesh S. Chauhan, IIT Kanpur 36

37 Linear to Saturation transition First generation SPICE models used this kind of equation, WW LL μμcc oooo VV GGGG VV TT VV DDDD mm 2 VV DDDD 2, VV DDDD < VV DDDD,ssssss II DD = WW LL μμcc oooo (VV GGGG VV TT ) 2, VV 2mm DDDD VV DDDD,ssssss II DD and ddii DD ddvv DDDD are continuous at VV DDDD = VV DDDD,ssssss but dd2 II DD ddvv 2 is not. DDDD Yogesh S. Chauhan, IIT Kanpur 37

38 Linear to Saturation transition For numerical robustness, the derivatives of arbitrary order must be continuous at all voltage values of interest. This property is sometimes referred to as -differentiability. Single equation approach used in BSIM3. Define an effective drainsource bias V DSeff, VV DDDD,eeeeee = VV DDDD,ssssss 1 2 VV DDDD,ssssss VV DDDD Δ + (VV DDDD,ssssss VV DDDD Δ) 2 +4ΔVV DDDD,ssssss VV DDDD VV DDDD,ssssss, VV DDDD,eeeeee VV DDDD For VV DDDD VV DDDD,ssssss, VV DDDD,eeeeee VV DDDD,ssssss Drain current equation becomes (V GS >V T ), II DD = WW μμcc LL oooo VV GGGG VV TT VV DDDD,eeeeee mm VV 2 2 DDDD,eeeeee Derivatives are continuous. Increasing Δ Δ determines the degree of smoothness. Yogesh S. Chauhan, IIT Kanpur 38

39 Sub-threshold to strong inversion transition For VV GGGG VV TT, (VV GGGG VV TT VV oooooo ) II DD = II 0 ee nnnnnn/qq 1 ee VV DDDD kkkk/qq This is not valid in strong inversion. It leads to excessively high current for VV GGGG VV TT For VV GGGG VV TT II DD = WW LL μμcc oooo VV GGGG VV TT VV DDDD,eeeeee mm 2 VV 2 DDDD,eeeeee This is not valid in sub-threshold and leads to negative current for VV GGGG < VV TT First method Single equation: II DD = II DD,ssssss + II DD,iiiiii Good enough for Digital applications, but the derivatives are discontinuous making it unsuitable for Analog cases. Yogesh S. Chauhan, IIT Kanpur 39

40 Sub-threshold to strong inversion transition Second method Single equation: Use effective VV GGGG VV TT as 2nnnnnn qq llll 1 + exp VV GGGG VV TT 2nnnnnn/qq VV GGGGGG,eeeeee = 1 + 2nn eeeeee VV GGGG VV TT 2VV oooooo 2nnnnnn/qq nn is the ideality factor and lies between 1 and 2. V off is a parameter for fringing from width side. Assume V off =0 for further analysis. For VV GGGG VV TT, the exponential term inside ln() is larger than 1 making VV GGGGGG,eeeeee = VV GGGG VV TT For VV GGGG VV TT, VV GGGGGG,eeeeee kkkk qq eeeeee VV GGGG VV TT nnnnnn/qq Yogesh S. Chauhan, IIT Kanpur 40

41 Single equation for drain current Use VV DDDD,ssssss = VV GGGGGG,eeeeee+2kkkk/qq, where 2kkkk/qq is added for numerical stability mm when VV GGGGGG,eeeeee 2kkkk/qq. We have written ID as follows valid from linear to saturation- II DD = WW LL μμcc oooo VV GGGG VV TT VV DDDD,eeeeee mm 2 VV 2 DDDD,eeeeee Now drain current becomes, II DD = WW LL μμcc oooo VV GGGGTT,eeeeee mm 2 VV DDDD,eeeeee VV DDDD,eeeeee II DD = WW LL μμcc oooo VV GGGGGG,eeeeee mm 2 VV DDSS,eeeeee II DD = WW LL μμcc oooo VV GGGGGG,eeeeee 1 mm 2 This is valid for all V gs and V ds. VV GGGGGG,eeeeee VV GGGGGG,eeeeee + 2kkkk/qq VV DDDD,eeeeee VV DDDD,eeeeee VV GGGGGG,eeeeee + 2kkkk/qq VV DDDD,eeeeee Yogesh S. Chauhan, IIT Kanpur 41

42 Terminal Charges and Charge Partition AC and Transient simulation need capacitances. Quasi-static approximation The Channel charge is assumed to respond instantaneously to any change in the bias voltage. From QQ ii, we need to find Q G, Q B, Q S and Q D. Yogesh S. Chauhan, IIT Kanpur 42

43 Total inversion charge Before delving into Q G, Q S and Q D. Let us find the total inversion charge in the channel, QQ ii. The charge per unit area, QQ II, is given as QQ II = CC oooo VV GGGG VV TT mmvv CCCC xx We need to know VV CCCC xx =? Define α = 1 VV DDDD,eeeeee which gives, VV DDDD,eeeeee = 1 α, VV DDDD,ssssss VV DDDD,ssssss Thus VV CCCC = VV GGGGGG,eeeeee mm xx LL 11 αα 22 Yogesh S. Chauhan, IIT Kanpur 43

44 Total inversion charge The charge per unit area, QQ II, is given as QQ II = CC oooo VV GGGG VV TT mmvv CCCC xx QQ II = CC oooo VV GGGGGG,eeeeee 1 xx LL 1 αα 2 Thus total inversion charge LL QQ II = WWCC oooo VV GGGGGG,eeeeee 1 xx LL 1 αα2 dddd Total inversion charge 0 QQ II = 2 3 WWWWCC oooo 1 + αα + αα 2 VV GGGGGG,eeeeee 1 + αα Yogesh S. Chauhan, IIT Kanpur 44

45 Source-Drain charge partitioning We know, QQ II = QQ SS + QQ DD but not the exact share of each. The assignment of the channel charge to the source and drain charges is called charge partition. Charge partitioning 50/50 partition: Arbitrarily assign 50% of QQ II to QQ SS and 50% to QQ DD.This is valid only when VV DDDD is small. For VV DDDD ~0, MOSFET is symmetrical and QQ SS ~QQ DD ~QQ II /2. 0/100 partition: This is based on the logic that in saturation, the pinch off region implies that QQ DD = 0, which is actually not correct. 40/60 partition: This is a more physical distribution of charges. One should note that the charge distribution under this scheme is 40/60 only in saturation. However this partition scheme is valid in all regions. Yogesh S. Chauhan, IIT Kanpur 45

46 Source-Drain charge Ward-Dutton partitioning scheme LL QQ DD = WW xx QQ LL II dddd, QQ 0 SS = WW 1 xx QQ LL II dddd 0 Drain charge LL QQ DD = WW xx LL LL QQ II dddd = WWCC oooo VV GGGGGG,eeeeee xx LL 1 xx LL 1 αα2 dddd 0 QQ DD = 2 15 WWWWCC oooo 3αα 3 + 6αα 2 + 4αα + 2 VV GGGGGG,eeeeee (1 + αα) 2 Similarly, LL QQ SS = WW 1 xx QQ LL II dddd = 2 0 WWWWCC 15 oooo 2αα VV 3 +4αα 2 +6αα+3 GGGGGG,eeeeee 1+αα 2 LL 0 Ref.: S.-Y. OH, D. E. WARD and, A. W. DUTTON, Transient Analysis of MOS Transistors, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 4, AUGUST Yogesh S. Chauhan, IIT Kanpur 46

47 Gate and Bulk charge Total gate charge QQ GG = WWWWCC oooo VV GGGGGG,eeeeee mm mm αα + αα2 1 + αα + 2 mm 1 2φφ FF VV BBBB Finally Bulk charge, QQ BB = QQ GG QQ II Capacitance CC mmmm = QQ mm VV nn Yogesh S. Chauhan, IIT Kanpur 47

48 Charge and Capacitance plots Yogesh S. Chauhan, IIT Kanpur 48

49 Real Device Effects Yogesh S. Chauhan, IIT Kanpur 49

50 Parasitic Source-Drain Resistance The main effect of the parasitic resistance is that V gs in the I ds equations is reduced by R s I ds I dsat I I ( V dsat0 dsat0 1 + gs R V s t ) Yogesh S. Chauhan, IIT Kanpur 50

51 High-Frequency performance Rd D High-frequency performance is limited by input R and/or C. G Rin Low Frequency Model Rs S R + in = Rg electrode R ii Gate-electrode resistance Intrinsic input resistance Yogesh S. Chauhan, IIT Kanpur 51

52 Gate-Electrode Resistance Drain Rg-electrode Source Multi-finger layout greatly reduces the gate electrode resistance R = ρw g electrode / 12Tg Lg N f 2 ρ : resistivity of gate material, W f : width of each gate finger, T g : gate thickness, L g : gate length, N f : number of fingers. Yogesh S. Chauhan, IIT Kanpur 52

53 Bulk MOSFET Drain current in MOSFET (ON operation) II OOOO = μμ WW LL CC oooo VV DDDD VV TTHH 2 Drain current in MOSFET (OFF operation) II OOOOOO 10 VV GGGG VV TTHH SS Desired High I ON ( L, Cox, V DD -V TH ) Low I OFF ( V TH, S) C ox =ε ox /t ox =oxide cap. S Subthreshold slope Yogesh S. Chauhan, IIT Kanpur 53

54 Technology Scaling Each time the minimum line width is reduced, we say that a new technology node is introduced. Example: 90 nm, 65 nm, 45 nm Numbers refer to the minimum metal line width. Poly-Si gate length may be even smaller. Yogesh S. Chauhan, IIT Kanpur 54 Figure source - Wikipedia

55 Technology Scaling Scaling At each new node, all geometrical features are reduced in size to 70% of the previous node. Reward Reduction of circuit size by half. (~50% reduction in area, i.e., = 0.49.) Twice number of circuits on each wafer Cost per circuit is reduced significantly. Ultimately Scaling drives down the cost of ICs. Yogesh S. Chauhan, IIT Kanpur 55

56 Scaling and Moore s Law Number of components per IC function will double every two years April 19, 1965 (Electronics Magazine) Shorthand for rapid technological change! Still working! Yogesh S. Chauhan, IIT Kanpur 56 Source:

57 Threshold Voltage Roll-Off Energy band diagram from source to drain when Vgs=0V and Vgs=Vt. A-b long channel; c-d short channel. Vt decreases at very small Lg. It determines the minimum acceptable Lg because Ioff is too large when Vt becomes too low or too sensitive to Lg. Yogesh S. Chauhan, IIT Kanpur 57 Source: Chenming Hu Modern Semiconductor Devices for Integrated Circuits

58 Channel Length Modulation Esat Em Pinch off point moves towards the source as V ds increases V DS V DSsat L V V ds dsat I = I 1 I 1 Dsat Dsat 0 + = + Dsat 0 L V A long channel Short channel C.Hu, Modern Semiconductor Devices for IC, 2009 Prentice Hall A v reduces Yogesh S. Chauhan, IIT Kanpur 58

59 Technology Trend Performance Product Source : Yogesh S. Chauhan, IIT Kanpur 59

60 Wasn t that smooth ride? Where is the bottleneck? II OOOO = μμ WW LL CC oooo VV DDDD VV TTTT 2 V TH can t be decreased why? Subthreshold slope gets worse! Yogesh S. Chauhan, IIT Kanpur 60

61 Thin Depletion Layer - Problem C g Gate Oxide Source Body Drain Q G = Q i +Q b Charge sharing Yogesh S. Chauhan, IIT Kanpur 61

62 Short Channel Big Problem Gate C g Oxide Source Drain C d MOSFET becomes resistor at small L. Chenming Hu, Modern Semiconductor Devices for ICs 2010, Pearson Yogesh S. Chauhan, IIT Kanpur 62

63 Making Oxide Thin is Not Enough Gate Source Drain Leakage Path Gate cannot control the leakage current paths that are far from the gate. Yogesh S. Chauhan, IIT Kanpur 63

64 What can we do? Gate Source Drain Leakage Path Yogesh S. Chauhan, IIT Kanpur 64

65 May 4, 2011 The New York Times Front Page Intel will use 3D FinFET at 22nm Most radical change in decades There is a competing SOI technology Yogesh S. Chauhan, IIT Kanpur 65

66 One Way to Eliminate Si Far from Gate Thin body controlled By multiple gates. Gate Length Gate Length Source Gate Drain Source Gate FinFET body is a thin Fin. Drain Fin Height Fin Width N. Lindert et al., DRC paper II.A.6, 2001 Yogesh S. Chauhan, IIT Kanpur 66

67 40nm FinFET nm Fin allows 2.7nm SiO2 & undoped body ridding random dopant fluctuation. 66mV/dec X. Huang et al., IEDM, p. 67, 1999 Yogesh S. Chauhan, IIT Kanpur 67

68 Introduced New Scaling Rule Leakage is well suppressed if Fin thickness < Lg 10nm Lg AMD 2002 IEDM 5nm Lg TSMC 2004 VLSI 3nm Lg KAIST 2006 VLSI Yogesh S. Chauhan, IIT Kanpur 68

69 Two Improvements Since FinFET with thin oxide on Fin top F.L.Yang et al. (TSMC) 2002 IEDM, p FinFET on bulk substrate T. Park et al. (Samsung) 2003 VLSI Symp. p Yogesh S. Chauhan, IIT Kanpur 69

70 State-of-the-Art 14nm FinFET Taller and Thinner Fins for increased drive current and performance Yogesh S. Chauhan, IIT Kanpur 70 Source: Anandtech

71 BSIM Family of Compact Device Models BSIM3 BSIM4 Conventional MOSFET New BSIM6 BSIMSOI Silicon on Insulator MOSFET BSIM-CMG & BSIM-IMG Multi-Gate MOSFET BSIM: Berkeley Short-channel IGFET Model Yogesh S. Chauhan, IIT Kanpur 71

72 BSIM-CMG and BSIM-IMG Berkeley Short-channel IGFET Model First industry standard SPICE model for IC simulation Used by hundreds of companies for IC design since 1997 BSIM FinFET model became industry standard in March 2012 It s Free Yogesh S. Chauhan, IIT Kanpur 72

73 Common-Multi-Gate Modeling Common Multi-gate (BSIM-CMG): All gates tied together Surface-potential-based core I-V and C-V model Supports double-gate, triple-gate, quadruple-gate, cylindrical-gate; Bulk and SOI substrates Yogesh S. Chauhan, IIT Kanpur 73

74 BSIM-CMG Model Surface potential obtained by solving the 1D Poisson s equation V s V g n+ y x N n+ A V d 2 qψ qφb qvch qφb ψ qn i kt kt kt kt = e e e e 2 + x ε Si Inversion Carriers Body Doping A Perturbation approach is used to handle finite body doping M. V. Dunga et al.,ted 2006 ψ = ψ inv + ψpert Net Surface Potential Inversion Carriers only Perturbation due to finite doping V g Yogesh S. Chauhan, IIT Kanpur 74

75 BSIM-CMG Model Drain current derived from drift-diffusion Drain Current (A) Na = 3e18cm -3 1m Vg = 1.5V 500µ Vg = 1.2V Vg = 0.9V Drain Voltage (V) Drain Current (A) 1m 500µ Na = 3e18 cm -3 Vd = 0.1 Vd = 0.2 Vd = 0.4 Vd = Gate Voltage (V) M. V. Dunga, UCB Ph.D. Thesis Yogesh S. Chauhan, IIT Kanpur 75

76 BSIM-CMG Global fitting with 30nm 10µm FinFETs Yogesh S. Chauhan, IIT Kanpur 76

77 Modeling of Germanium Ge FinFET may be used in 10nm node for better P-FinFET. Industry standard BSIM FinFET model can now model Ge FinFET. Early availability of a unified Si/Ge FinFET model facilitates technology-circuits codevelopment. Yogesh S. Chauhan, IIT Kanpur 77

78 Modeling of Germanium 20nm Due to the lower m* of holes in Ge the charge-centroid is farther away from the oxide interface resulting in a weaker SR scattering. Ge mobility has a weaker dependence on E eff up-to 0.5 MV/cm as the impact of SR scattering is only seen at much higher E eff in Ge as compared to Si. S. Khandelwal et. al., "Modeling 20nm Germanium FinFET with the Industry Standard FinFET Model", IEEE Electron Device Letters, July Yogesh S. Chauhan, IIT Kanpur 78

79 Modeling of InGaAs L = 20 nm, H = 30 nm, W = 20 nm, Nfin = 4. Data from: J. J. Gu et al. IEDM 2012 S. Khandelwal et. al., "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on Compact Modeling, Washington D.C., USA, June Yogesh S. Chauhan, IIT Kanpur 79

80 Transistor Pathway Yogesh S. Chauhan, IIT Kanpur 80 Source: Applied Materials

81 FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard Book Authors Yogesh Singh Chauhan, IITK Darsen D Lu, IBM Navid Payvadosi, Intel Juan Pablo Duarte, UCB Sriramkumar Vanugopalan, Samsung Sourabh Khandelwal, UCB Ai Niknejad, UCB Chenming Hu, UCB Chapters 1. FinFET- from Device Concept to Standard Compact Model 2. Analog/RF behavior of FinFET 3. Core Model for FinFETs 4. Channel Current and Real Device Effects 5. Leakage Currents 6. Charge, Capacitance and Non-Quasi-Static Effect 7. Parasitic Resistances and Capacitances 8. Noise 9. Junction Diode Current and Capacitance 10. Benchmark tests for Compact Models 11. BSIM-CMG Model Parameter Extraction 12. Temperature Effects Yogesh S. Chauhan, IIT Kanpur 81

82 Acknowledgement My students BSIM team CMC members Yogesh S. Chauhan, IIT Kanpur 82

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