The Future of CMOS. David Pulfrey. CHRONOLOGY of the FET. Lecture Lilienfeld s patent (BG FET) 1965 Commercialization (Fairchild)

Transcription

1 The Future of CMOS David Pulfrey 1 CHRONOLOGY of the FET 1933 Lilienfeld s patent (BG FET) 1965 Commercialization (Fairchild) 1991 The most abundant object made by mankind (C.T. Sah) 2003 The 10 nm FET (Intel) 2 1

2 SCALING: WHY DO IT? Increase speed Increase density Reduce cost (?) 3 SCALING: SPEED 10 2 NMOS Gate Delay (ps) CV/I THz 0.85V 2.63 THz V DD =0.75V Published data V DD =0.8V Intel data Gate Length (nm) 4 Morkoc04 2

3 SCALING: DENSITY P4 (130): 55M in 146 mm 2 P4- Prescott (90): 125M in 112 mm 2 P4- Dothan (90): 140M in 87 mm 2 5 Perlmutter04, Raghavan00 SCALING: COST 6 3

4 SCALING: FACTORY COST Intel 300mm Moore s Law for Fabs! 7 MIT02 THE SHRINKING FET ga te So urce n + poly T ide L NCH VDD Lint W n + B n x + j Dr ai n L eff reduced 30X But devices are still well tempered x y NSUB CMOS 3 CMOS P18 CMOS P13 90NM L nm LINT nm XJ nm TOX nm NCH cm E E E E+17 VDD V VTHO V

5 THE SIGNIFICANCE OF E X AND E Y VDD L TOX LD XJ E x < E y = diode NSUB x y E x > E y = transistor Well tempered means: keeping E x > E y and avoiding the short- channel effect 9 SHORT-CHANNEL EFFECT: V T depends on L Charge under gate due to E from G, S and D V T L L = Q C B Geometrical construction to estimate V T drop due to E encroachment Reduce junction depth 10 Pulfrey89 5

6 Raised S and D x j Improves I ON by 20-30% 11 Gargini02a Current and E y ? VDD,V L, nm "E y", mv/nm Z ( V I Dsat = C µ L m = body factor GS V 2m T ) 2 I Dsat = C Z υ i.e. independent of L and f ( V GS sat V ( V T GS ) 1 V T ) 12 6

7 MOBILITY FETs don t operate at high E y all the time, or over all of the channel. High mobility still very desirable to increase drive current Get high µ from strained-silicon channel 13 Si on SiGe: : Tensile strain 14 IBM04 7

8 Strained Si: : breaking the symmetry 6 equivalent directions Intervalley scattering 2 sub- bands lowered in energy Reduced intervalley scattering Decreased effective mass (horizontal) 15 Strained Si: : Relaxed sub-layers 16 IBM04 8

9 Current and V T Power supply (V), Threshold Voltage (V) V DD 10 0 V T Channel length (nm) Decreasing (V DD - V T ) means a loss of gate overdrive Ultimate V T 0.2 V Determined by I D,subt Quantization important E 1 E C E 0 18 Morkoc04 9

10 Control of I D,subt S I G C OX It s done by capacitive control of the source- channel barrier height C B V VGS = C 1+ C IB ψ S = B VGS m B m : the body factor E c SOURCE DEPLETION qv T m OFF THRESHOLD I D, subt ( VGS = 0) = I, D thresh VT exp mvt This sets lower limit to V T, e.g., 0.2V i.e., I ON /I OFF Sub-Threshold Slope It s the V GS needed to reduce I D by 10X S dlog 10 I = dv GS = m V D t 1 = m V at 300 K V t kt = q reduce T Recall : C m = 1+ C B ε s t = 1+ ε W B Need : small t and small N A Gate leakage V T compromise 20 10

11 Cold-Electron Tunneling de Broglie wavelength: λ = h mv = h 2m. KE For an electron in Si at KE=φ /2 : λ = 6.1 nm 21 (b) FN tunneling (c) direct tunneling Taur98 2.3nm Electron could be either side of the barrier! Tunneling Facts A Tunneling probability T = 2 A 2 trans 4 inc πa exp λ = for 180nm = for 130nm = for 90nm What is a tolerable gate current? 22 Taur98 11

12 Ultimate Sub-Threshold Current S D tunneling Gate controlled barrier Gate controlled barrier? <V t <V t Source Source direct Drain Zener Drain 23 Morkoc04 Short channel, moderate drain bias Expected to occur at L 10 nm Short channel, larger drain bias 24 Chau03 12

13 25 Chau03 Power constrained scaling limits It is power dissipation, rather than scaling, that will be the limiting factor e.g., can scale big servers more aggressively than portables and SRAMs 26 Frank02 13

14 C ε = T High-k k dielectrics High T OX needed to reduce gate leakage High C OX needed for I D and S Resolve conflict by increasing ε 27 Wong02 High-k k dielectrics: tunneling A Tunneling probabilit y T = 2 A 2 trans 4 inc πa exp λ Tunneling probabilit y T 4π = exp h a 0 2m [ V ( x) E] dx Need a high φ 28 14

15 High-k k dielectrics: contenders Also: must withstand poly activation (950C) or use metal gate 29 Wong02 Metal gate: self-alignment Poly gates made self- alignment possible Possibilities: Perhaps use sacrificial poly gate, then deposit metal. Co- evaporation of metals (Ti and Ni) to obtain different work functions, i.e., different V T s for NMOS and PMOS or for different blocks on same wafer

16 Metal gate and N SUB If V T controlled by metal, perhaps can use undoped Si substrate. This would remove the problem of dopant fluctuations. 31 Gargini02 Beyond Planar CMOS Planar CMOS: 10 nm prototypes demonstrated raised source and drain strained Si high- k dielectric metal gate limitation is power dissipation Further improvements: Double gate CMOS SOI CMOS 32 16

17 Double-Gate CMOS Design flexibility - different V G s and T s SCE controlled by device geometry, not doping Can use undoped channel - reduces statistical fluctuations and Zener BD Increased C improves I ON and S 33 Wong02 SCE: V T Roll-off off DIBL Note: benefit of shrinking d Si 34 Philips04, MIT02 17

18 DG: Improved ON/OFF ratio kt Re call : S = m m = 1+ q C C B DG doubles without reducing T Tends to zero (small d Si and inversion from top and bottom) For same I OFF, set V T 60mV lower, get more I ON 35 DG example: FINFET DG is a deeply scalable FET, but fabrication is difficult 36 Wong02 18

19 SOI CMOS SIMOX More easily fabricated Ultra thin body No leakage through substrate Very low Cj Good device isolation for RF Technology of choice for SOC Not as deeply scalable as DG 37 Gargini02a SOI: state-of of-the-art Small L, x j, d Si Raised S and D Fully depleted 38 Chau03 19

20 Conclusion CMOS Planar CMOS: 10nm - THz operation - millions of transistors DG CMOS: reduced SCE - best sub- threshold slope - high performance digital SOI CMOS: reduced leakage and parasitic C - RF capable Do we, or our children, need anything more? 39 References Chau03 - ftp://download.intel.com/research/silicon/chau%20drc% %20foils.pdf David04 - ftp://download.intel.com/research/silicon/ken_david_gsf_ pdf Frank02 - Frank D.J, IBM J. R&D, v46, 235, 2002 Gargini02 - ftp://download.intel.com/research/silicon/paoloissus0102.pdf Gargini02a - ftp://download.intel.com/research/silicon/paolo%20m2s2% pdf IBM ibm.com/chips/services/foundry/offerings/sige/5hp/ IBM04 MIT02 /6-720JIntegrated-Microelectronic-DevicesFall2002/4E1C74EA-38FB-41CF-B654-3C5AD913B2E9 /0/lecture33.pd Morkoc04 - Morkoc H., WOCSDICE, Slovakia, 2004 Perlmutter04 - ftp://download.intel.com/research/silicon/perlmutter pdf Pulfrey89 - Pulfrey D.L., N.G.Tarr, Introduction to Microelectronic Devices, Prentice-Hall, 1989 Raghavan00 - Raghavan G. et al., IEEE Spectrum, v37(10), 47, 2000 Rucker03 - Rucker R. et al., IEDM, paper 5.3, 2003 Taur98 - Taur Y., T.H.Ning, Fundamentals of Modern VLSI Devices,Cambridge University Press, 1998 Taur99 - Taur Y., IEEE Spectrum, 25, July 1999 Wong02 - Wong H-S.P., IBM J. R&D, v46, 133, 2002 Yeo02 - Yeo K-S. et al., CMOS/BiCMOS VLSI, Prentice-Hall,