Physics and Modeling of FinFET and UTB-SOI MOSFETs

Transcription

1 2017 Symposium on Nano Device Technology Session 1: Nano Devices and New Materials Physics and Modeling of FinFET and UTB-SOI MOSFETs -- using BSIM-MG as example Speaker: Darsen Lu, Assistant Prof. S

2 Outline Introduction FinFET and UTB Device Physics Short channel effects Quantum confinement Variability benefits Parasitic capacitance Mechanical strain and stressor design Self heating FinFET and UTB Compact Models 2

3 CMOS Scaling Limits Short Channel Effects Capacitance Coupling Perspective Barrier Lowering Perspective V gs V ds source/channel barrier long channel S C g C d D V ds leakage path short channel Drain-induced barrier lowering (DIBL 3

4 Body Doping Limits Disadvantages of body doping Random dopant fluctuation Band-to-band tunneling leakage L W D. Frank et. al. IEEE Proc.,

5 Solution #1: UTBSOI MOSFET Leakage path cut off by thin body Ultra-thin-body (UTB) SOI MOSFET T ox =1.5nm, N sub =1e15cm -3, V dd =1V, V gs =0 Silicon 5

6 Solution #2: FinFET Transistor FinFET / Multiple-Gate Transistor: Gate Control from Multiple Sides of the channel leads to smaller short channel effects Gate 1 V g Gate 1 fin Gate 2 Source Si Drain T Si BOX S T ox Gate 2 Double-gate MOSFET 6

7 FinFET: A Historical Perspective 1999 IEDM: 1 st FinFET Demonstration DARPA project at UC Berkeley 2002: 25nm FinFET Demonstration 2004: 5nm FinFET Demonstration Research at TSMC led by Dr. Hu 2011: FinFET used in production Intel 22nm Technology 7

8 BSIM-MG: Industry Standard Models BSIM-CMG for FinFET Common Multi-gate Model development Selected as industry standard compact model in 2012 BSIM-IMG for UTB-SOI Independent Multi-gate Model development Selected as industry standard compact model in 2015 FinFET UTB-SOI Surroundinggate FET Double-gate FinFET 8

9 Outline Introduction FinFET and UTB Device Physics Short channel effects Quantum confinement Variability benefits Parasitic capacitance Mechanical strain and stressor design Self heating FinFET and UTB Compact Models 9

10 Short Channel Effects (SCE) SCE Improves from Bulk to UTB-SOI / FinFET to GAA 10

11 SCE Modeling Natural length λ characterize SCE λ = ε si 2ε ox ε T ox 4ε T si ε ε fin si ox 1 oxe T T si T fin oxe T oxe + 1 4H eff 2 FinFET UTB SOI H eff H fin ε si = H fin + 2 Toxe 8 ε ox DIBL, SS cosh Leff exp D λ 0.5 ( D L / λ) eff 1 11

12 FDSOI MATLAB BOX DIBL (mv/v) Decreasing Tsi Tsi=6nm to limit DIBL to 80mV at Lg=20nm λ = ε ε si ox t ox t si Gate Length (nm) 12

13 FinFET MATLAB DIBL (mv/v) Gate 1 Gate 2 Decreasing Tsi Tsi=12nm to limit DIBL to 80mV at Lg=20nm λ = 1 ε 2 ε si ox t ox t si S Gate Length (nm) 13

14 Tsi=6nm FDSOI FinFET v.s. FDSOI Source Gate Si V g Drain T Si Tsi=12nm FinFET T ox Gate 1 V g Source Si Drain T Si T ox Gate 2 Source Si Drain T Si T ox Gate V g Tsi=6nm FDSOI 14

15 SCE Benefits of Fin Recess Gate recess achieved by etching into BOX (SOI Fin) Significant SCE Improvement Shown Df in=8 Swing (mv/dec) Dfin=10 Dfin=12 Dfin=8 Gate Rec. Dfin=10 Gate Rec. Dfin=12 Gate Rec. K. Cheng et al., VLSI Fin Tail Height (nm) D. Lu et al., S3S Conf

16 Punchthrough Stopper for Bulk Fin Bulk FinFET SOI FinFET Bulk FinFET gate PTS Terry Hook, IBM SiO2 not shown 16

17 Modeling Fin Shape in BSIM-MG FinFET with various shape are modeled J. Pablo Duarte et al., Unified FinFET Compact Model: Modeling Trapezoidal Triple-Gate FinFET, SISPAD 2013 Intel 14nm 17

18 FinFET Scaling Limit: Quantum Eff. Body thickness (Tsi) allows us to continue scaling of FinFETs Tsi scaling limited by quantum effects 4nm wide Si fins J Chang et al. VLSI

19 Quantum Effects in Thin body 2D Confinement Effects Need to be Considered for FinFET and UTB-SOI Inversion Charge Density (cm -3 ) 1.2x10 19 V =V =0.7V g1 g2 9.0x10 Ψ 18 m1 =Ψ m2 = 4.6eV N body =1e15cm x x X (nm) FinFET C.-H. Lin 19

20 Quantum Effects: Threshold Shift Electrons in FinFET Resembles Particle in a BOX Problem in quantum mechanics 2 q V th E 0 = 2 π * 2 2m Tsi Wikipedia 20

21 Quantum Effect: Effective Cox Inversion layer thickness effect Coxe Effective Oxide Thickness Model The effective charge thickness is a function of Qi Inversion Charge Density (cm -3 ) V g1 =V g2 =0.7V Ψ m1 =Ψ m2 = 4.6eV N body =1e15cm X (nm) Classic QM Ids (H. Lu et al., UCSD) Vgs 21

22 Fully Depleted Body: Low Variability Extremely low variability demonstrated for UTB-SOI with lightly-doped body ETSOI K. Cheng et al., IEDM

23 Variability Modeling using BSIM-MG 6T SRAM Cells Fabricated with FinFET Device variation modeled with BSIM- MG to capture SRAM SNM distribution PD NA PL Count NF=1 189 cells Measured Data Monte Carlo Mismatch: σ TFIN =1.03nm σ LG = 4.2 nm Pull-down nfet Vth (V) NF=2 189 cells D. Lu et al., SISPAD 2009 Measured Data Monte Carlo Mismatch: σ TFIN =1.03nm σ LG = 4.2 nm Read SNM (mv) 23

24 FinFET Parasitic Capacitance Complex 3D structure need to be considered for fringe capacitance D pcca gate drain source F pitch Source Gate Drain Cgs0 (af) D pcca dependence TCAD Model Contact-Gate Distance (nm) Cgs0 (af) Fin pitch dep. Fin Pitch 40nm 50nm 60nm Fin Height (nm) 24

25 Stress Boost FinFET Performance Drain Con. Air Spacer Gate Fin (channel) Air Spacer 1.3GPa average tensile stress Fin (punchthrough stopper) Plotted: Longitudinal Stress Source Contact Local Iso. D. Lu et al., VLSI-TSA 2017 (110) / <110> Lg = 30nm Vdd=0.7v Air spacer Lattice Mismatch assumed: 1% smaller natural lattice constant Longitudinal stress in channel +1.3 GPa (tensile) 37% I dlin Benefit Possible Strain Sources: Carbon incorporation in channel SSDOI FinFET Discussion C incorporation also suppresses P-diffusion 25

26 BSIM-MG Self Heating Sub-circuit Self Heating Important for Bulk and SOI FinFETs T Temperature Node RTH0: normalized thermal resistance CTH0: normalized thermal capacitance WTH0: minimum width for Rth calculation F pitch : Fin-to-fin pitch N fin : Number of fins in total Takahasi et al., IEDM

27 Outline Introduction FinFET and UTB Device Physics Short channel effects Quantum confinement Variability benefits Parasitic capacitance Mechanical strain and stressor design Self heating FinFET and UTB Compact Models 27

28 Framework for BSIM-MG Independent Multi-Gate framework (separate front- and back- gates) BSIM-IMG FG S D BG Back-gated FDSOI FinFET with split gates Common Multi-Gate framework (tied gates) BSIM-CMG BSIM-CMG SOI module BSIM-CMG bulk module BSIM-CMG nanowire Vertical Pillar 28

29 Common Multi-gate Model: BSIM-CMG TCAD Verification: Drain Current (A) 1m Vds = 0.6V 1? Normalized Capacitance Model Symmetry Cgs 1n Csg 0.4 Na = 1e15cm -3 Cdg Na = 1e18cm -3 1p Na = 3e18cm Na = 3e18cm -3 Na = 5e18cm -3 Vgs = 1.5V Cgd Na = 1e19cm f Gate Voltage (V) Drain Voltage (V) FinFET Silicon Data: Drain Current (A) 50µ 40µ 30µ 20µ 10µ 0 Lg = 50nm Vds = 50mV Vds = 1.2V Vds = 1.2V Vds = 50mV 1p Gate Voltage (V) 1m 1µ Drain Current (µa) 1n Cgg Lg = 50nm Symbols : TCAD Lines : Model V gs = 1.2V V gs = 1.0V V gs = 0.8V V gs = 0.6V V gs = 0.4V Drain Voltage (V) Output Conductance (S) 1m 1µ Vth Roll-off (V) M. V. Dunga et al., VLSI 2007 Tox = 2nm, Na = 1e15cm -3 Vds=100mV Channel Length (µm) Lg = 90nm Vgs = 1.0V --> 0.0V (in steps of 0.2V) 1n Drain Voltage (V) Tsi = 10nm Tsi = 15nm Tsi = 20nm Tsi = 25nm Tsi = 30nm Transconductance, g m (S) 800n 600n 400n 200n L = 0.97µm Vds = 50mV Vds = 1.2V Gate Voltage (V) 29 10µ 8µ 6µ 4µ 2µ

30 Vertical GAAFET Fitting to Device Data Symbols: Electrical Test Data Lines: Model Drain Current vs. V gs L=120nm, D=80nm, Tox=3nm Asymmetric!! Transconductance Output Conductance Drain Current vs. V ds S. Venugopalan et al., Solid State Electronics, vol. 67, issue. 1,

31 Summary FinFET & UTB device physics essentially the same as planar, except Superior electrostatics, esp. with gate recess Quantum effects ultimately limits T si scaling 3D FinFET parasitic capacitance complex, but not necessarily larger Strain further boost device performance BSIM-CMG and BSIM-IMG are industry standard compact models Physically derived with good agreement with industry data Variability model captures SRAM statistics 31

32 UC Berkeley Acknowledgments Prof. Chenming Hu, Prof. Ali Niknejad, Prof. Tsu-Jae King, Chung- Hsun Lin, Mohan Dunga, Angada Sachid, Sriram V., Nuo Xu, Xin Sun, Tanvir Morshed, Wenwei Yang, Jodie Zhang, Shijing Yao NCKU K.-H. Kao, M.-H. Chiang, Wallace Lin, W.-C. Hsu, M.-D. Hsieh NAR Labs NDL for nano-fabrication, esp. Dr. Y.-J. Lee and Dr. M.-C. Chen NCHC for providing TCAD support IBM Philip Oldiges, Tze-Chiang Chen, Kangguo Cheng, Andreas Scholze, Josie Chang, Mike Guilleron, Ken Rim, Bruce Doris, Ali Khakifirooz, Pouya Hashemi, Reinaldo Vega, Tenko Yamashita, Pierre Morin, Huiming Bu, Nicolas Loubert, Shogo Mochizuki, Dechao Guo, Chia-Yu Chen, Gen Tsutsui, Robert Dennard, Jeffery Johnson, Terence Hook, Frank Yeh, Andreas Bryant, James Stathis, Bala Haran, Mukesh Khare, Wilfried Haensch, Bomsoo Kim, Bhagawan Sahu, Ghavam Shahidi and ANT/YKT staff 32