The Prospects for III-Vs

Transcription

1 10 nm CMOS: The Prospects for III-Vs J. A. del Alamo, Dae-Hyun Kim 1, Donghyun Jin, and Taewoo Kim Microsystems Technology Laboratories, MIT 1 Presently with Teledyne Scientific 2010 European Materials Research Society Spring Meeting June 7-10, 2010 Sponsors: Intel, FCRP-MSD Acknowledgements: Niamh Waldron, Ling Xia, Dimitri Antoniadis, Robert Chau MTL, NSL, SEBL 1

2 Outline Introduction: Why III-Vs for CMOS? What have we learned from III-V HEMTs? What are the challenges for III-V CMOS? The prospects of 10 nm III-V CMOS Conclusions 2

3 Why III-Vs for CMOS? Si CMOS has entered era of power-constrained scaling : CPU power density saturated at ~100 W/cm 2 CPU clock speed saturated at ~ 4 GHz ca/ nlipkowi/pictures/clo Pop, Nano Res 2010 ckspeeds.gif 3

4 Why III-Vs for CMOS? Under power-constrained scaling: Power = active power + passive power #1 goal ~ fcv DD2 N N N V DD But, V DD scaling very weakly: V DD 4 Chen, IEDM

5 Why III-Vs for CMOS? Need scaling approach that allows V DD reduction Goal of scaling: reduce footprint extract maximum I ON for given I OFF III-Vs: Much higher injection velocity than Si I ON Very tight carrier confinement possible S 5

6 III-V CMOS: What are the challenges? To know where you are going, you first have to know where you are. We are starting from: III-V High Electron Mobility Transistors 6

7 III-V HEMTs State-of-the-art: InAs-channel HEMT - QW channel (t ch = 10 nm) : - InAs core (t InAs = 5 nm) - InGaAs cladding - n,hall = 13,200 cm 2 /V-sec - InAlAs barrier (t ins = 4 nm) - Two-step recess - Pt/Ti/Mo/Au Schottky gate Kim, IEDM L g =30 nm 7

8 III-V HEMTs L g =30 nm InAs-channel HEMT Kim, IEDM V GS = 0.5 V I D [ma/ m m] 0.4 V GS = 04V 0.4 g m [ms/ m] V DS [V] V DS = 0.5 V V GS - V T [V] Large current drive: I on =0.4 ma/µm at V DD =0.5 V Enhancement-mode FET: V T = 0.08 V High transconductance: g mpk = 1.8 ms/um at V DD =0.5 V 8

9 III-V HEMTs L g =30 nm InAs-channel HEMT Kim, IEDM 2008 I D, I G [A/ m] =05V 10-7 V 0.5 DS V DS = 0.05 V I D V GS [V] I G H 21, U g, MAG [d db] H 21 U g MAG f T =601 GHz f max =609 GHz V = 0.5 V, V = 0.3 V DS GS Frequency [GHz] S = 73 mv/dec, DIBL = 85 mv/v, I on /I off =~10 4 First transistor with both f T and f max > 600 GHz 9

10 Scaling of III-V HEMTs: Benchmarking with Si Sub bthreshold sw wing [mv/dec.] 180 Si FETs (IEDM)* Triple recess: IEDM Pt sinking: IEDM iedm Gate Length [nm] iedm06 iedm07 AY [psec] GATE DEL 10 1 Si NMOSFETs iedm Gate Length, L g [nm] iedm06 iedm07 InAs HEMTs (V CC = 0.5V) (V CC = 1.1~1.3V) V DD =0.5 V Superior short-channel effects as compared to Si MOSFETs Lower gate delay than Si MOSFETs at lower V DD 10

11 Scaling of III-V HEMTs: Benchmarking with Si I I OFF =100 na/µm, V DD =0.5 V: FOM that integrates short-channel effects and drive current (scaled to V DD =0.5 V) III-V HEMTs: higher I ON for same I OFF than Si 11

12 What can we learn from III-V HEMTs? 1. Very high electron injection velocity at the virtual source Kim, IEDM 2009 E C v inj 0 L x v in nj v inj electron injection velocity at virtual source v inj (InGaAs) )increases with ithinas fraction in channel v inj (InGaAs) > 2v inj (Si) at less than half V DD 12

13 What can we learn from III-V HEMTs? 2. Quantum-well channel key to outstanding short-channel effects Kim, IPRM 2010 Dramatic improvement in electrostatic t ti integrity it in thin channel devices 13

14 What can we learn from III-V HEMTs? 3. Quantum capacitance less of a bottleneck than commonly believed In 0.7 Ga 0.3 As channel t ch = 13 nm Experiment (C G ) InAs channel t ch = 10 nm Experiment (C G ) Capacitance [ff F/ m 2 ] C ins ( t ins = 4 nm) 30 C Q1 Capacitance [ff F/ m 2 ] 20 CG C cent1 10 C ins ( t ins = 4 nm) C Q1 (m * = 0.026m e ) C cent1 C G ( 0.07 ) C G (005) 0.05 C G (m * = 0.026m e ) V G [V] V G [V] G Biaxial strain + non-parabolicity + strong quantization increase m * C G Jin, IEDM

15 Limit to III-V HEMT Scaling: Gate Leakage age Current InAs HEMT 10-3 t ins = 10 nm L g =30nm t ins =7nm t ins = 4 nm t ch = 10 nm I D, I [A/ m] D G I D t ins =4 nm t ins =7nm t ins I G 10-9 t ins =10 nm DS V DS = 0.5 V V GS [V] t ins I G Further scaling requires high-k gate dielectric 15

16 The Challenges for III-V CMOS: III-V HEMT vs. Si CMOS III-V HEMT Intel s 45 nm CMOS Critical issues: Schottky gate MOS gate Footprint scaling [1000x too big!] Need self-aligned contacts Need p-channel device Need III-V on Si 16

17 The High-K/III-V System by ALD Ex-situ ALD produces high-quality interface on InGaAs: Surface inversion demonstrated Al 2 O 3 /In 0.52 Ga 0.47 As D it in mid ~10 11 cm -2.eV -1 demonstrated Al 2 O 3 /In 0.52 Ga 0.47 As f=100 Hz-1 MHz 2.40E-011 Al 2 O 3 /In 0.65 Ga 0.35 As In 0.65 Ga 0.35 As MOS-Cap C gb on D=75um Lin, SISC 2008 Capacitance (F) 2.00E E E-011 f T ~55.56KHz 8.00E-012 Ye, E Bias (V) 17

18 In 0.7 Ga 0.3 As Quantum-Well MOSFET Direct MBE on Si substrate (1.5 µm buffer thickness) InGaAs buried-channel MOSFET (under 2 nm InP etch stop) 4 nm TaSiO x gate dielectric by ALD, TiN/Pt/Au gate L g =75 nm Radosavljevic, IEDM

19 In 0.7 Ga 0.3 As Quantum-Well MOSFET (scaled to V DD =0.5 V) 2009 Intel InGaAs MOSFET 19

20 What can we expect from ~10 nm III-V NMOS at 0.5 V? With thin InAs channel: Assume R S as in Si (~80 Ω.µm): S Key requirements: I D =1.5 ma/µm Three greatest worries! High-K/III-V interface, thin channel do not degrade v inj Obtaining R s =80 Ω.µm at required footprint Acceptable short-channel effects 20

21 Conclusions III-Vs attractive for CMOS: key for low V DD operation Electron injection velocity in InAs > 2X that of Si at 1/2X V DD Quantum well channel yields outstanding short-channel effects Quantum capacitance less of a limitation than previously believed Impressive recent progress on III-V CMOS Ex-situ ALD and MOCVD on InGaAs yield interfaces with unpinned Fermi level and low defect density Sub-100 nm InGaAs MOSFETs with I ON > than Si at 0.5 V demonstrated Lots of work ahead: Demonstrate 10 nm III-V MOSFET that is better than Si P-channel MOSFET Manufacturability, reliability 21