Analysis of Band-to-band. Tunneling Structures. Title of Talk. Dimitri Antoniadis and Judy Hoyt (PIs) Jamie Teherani and Tao Yu (Students) 8/21/2012

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1 1 Analysis of Band-to-band Title of Talk Tunneling Structures Dimitri Antoniadis and Judy Hoyt (PIs) Jamie Teherani and Tao Yu (Students) 8/21/2012 A Science & Technology Center

2 Vertical Type-II TFET Structure 2 Source Gate Insulating dielectric Material A Material B Drain dielectric Mat. A Mat. B E G,eff Insulating substrate Different material systems can be used (Mat. A/Mat. B) can be InAs/GaSb Type-II Band Alignment SS depends on the electrostatics, D it at the oxide/semiconductor interface, and tunneling mechanism

3 Outline 3 Electrostatics: MOS capacitors Band alignment E G,eff D it Gate Control Quantization Transport: Tunnel Diodes On-current Tunneling mechanism 2D-2D turn-on Structure Theory: Asymmetric-double-gate homojunction TFET

4 4 Contact Gate Contact High-K (4 nm) n-inas (10 nm, varied) n-gasb (10 nm, varied) Insulating layer, AlSb (500 nm) GaSb (Substrate) Contact ELECTROSTATICS: MOS Capacitors

5 1.6x10-6 Experimental CV Results Mo/HfO 2 /InAs MOS-C This Work Mo/Pt/Au HfO 2 (12 nm) n-inas (bulk) Ti/Au Capacitance (F/cm 2 ) 1.4x x x x x x x V g (V) 12 nm HfO 2 EOT = 2.2 nm 300 o C HfO 2 QS-CV 10KHz 1MHz J. Wu, et al., Lund University, Sweden, APL, nm Al 2 O 3 EOT = 3.1 nm

6 D it Modeling Process x CV 6 nm Al 2 O 3 EOT = 3 nm Simulated QSCV fit to Experimental QSCV Capacitance (F/cm 2 ) Experimental QSCV Ideal CV, no D it Ideal CV, no D it, el only V G (V) Capacitance (F/cm 2 ) 1.2 x el+hl+d it el-only 4 x Dit (#/ev.cm 2 ) D it distribution A Science -0.2& Technology 0Center E-Ec (ev) V G (V) The fit provides: D it distribution as fn(e) Energy bands as fn(v G ) Capacitance of el-only as fn(v G ) φ s as fn(v G )

7 7 Extracted D it for InAs MOS Capacitors D it (#/ev/cm 2 ) 10 x s of ozone pre-treatment 30 s of ozone pre-treatment 60 s of ozone pre-treatment E-E c (Volts)

8 8 MOS Capacitor Summary and Future Work High-K/bulk-InAs interface results in high D it for a wide range of experiment conditions InAs surface treatment ALD pre-treatment ALD temp. ALD precursors Anneal time Anneal temp. D it > #/(cm 2 ev) Results for bulk may be different for nanoribbons or QWs Javey group: good success using 1 min., 350 C thermal oxidation of InAs nanoribbons resulting in 1 nm of InAsO x and D it ~ #/(cm 2 ev) Not yet reproduced for bulk InAs?? D it must be reduced even further InAs has a very small electron effective mass low DOS and higher impact of D it

9 9 Reduction of D it Using MOS-HEMT Structure High-K (4 nm) InP (1 nm) InAs (10 nm, varied) GaSb (10 nm, varied) Insulating layer, AlSb (500 nm) M. Radosavljevic, et al., Intel Corp., IEDM In 0.7 Ga 0.3 As on InP GaSb (Substrate) InP cap used to create a good interface on InAs InP shown to significantly reduce D it and SS ~ 70 mv/decade

10 10 p-contact n-contact (non-alloyed) 1e17 n+ InAs (10 nm, varied) 2e19 p+ GaSb (10 nm, varied) p-contact Insulating layer, AlSb (500 nm) GaSb (Substrate) TRANSPORT: Tunnel Diodes

11 Experimental InAs/AlSb/GaSb Backward Diodes 11 J. N. Schulman and D. H. Chow, Sb-heterostructure interband backward diodes, IEEE Electron Device Letters, Previous Work 3D InAs to 3D GaSb Included AlSb barrier This Work 2D InAs to 2D GaSb Excluded AlSb barrier

12 Mesa Etch InAs GaSb Insulating Buffer Diode Process Passivation InAs GaSb Insulating Buffer 12 GaSb Substrate GaSb Substrate InAs GaSb Insulating Buffer GaSb Substrate Metallization InAs GaSb Insulating Buffer GaSb Substrate Via Open

13 Experimental Diode Results 13 Current (A) Device Size 50umX50um 50umX100um 50umX200um 50umX400um 100umX100um 200umX200um Voltage (V) Ohmic behavior regardless of device size Not scaling with area or perimeter Measurements not reproducible

14 Barrier Need for a Lateral Contact 14 5 nm 10 nm Insulating Buffer Metal Contact InAs GaSb Metal Contact InAs InAs GaSb Ins. Buffer GaSb Substrate Tunneling Tunneling from Metal to GaSb Valence Band Vertical Contact with Barrier Vertical Contact Without Barrier Contact spiking Difficulty contacting thin InAs Direct tunneling from metal to GaSb valence band Vertical Contact With Barrier If large barrier, then too much contact resistance If small barrier, then the QW InAs is not actually quantized

15 Ideal Diode Structure with Lateral Contacts 15 Laterally contacted GaSb and InAs InAs QW and GaSb QW unperturbed by contact Thick InAs on drain for better contact

16 Diode Structure with Lateral Contacts 16 More complicated structure to fabricate However, stepping stone to TFET structure Lateral contacts avoid problems of vertical contacts while maintaining desired quantization

17 p+ Source i Channel n+ Drain 17 Small WF Metal (+V G ) Gate Dielectric p+ Source n+ Drain Gate Dielectric Large WF Metal (-V G ) THEORY: Asymmetric-double-gate p-i-n TFET

18 Energy (a) Asymmetric-double-gate homojunction TFET structure (d) 18 p+ Source i Channel n+ Drain E 1 0 Ψ 1 x Position de dx = ef (b) Cut shown in (c) (c) Small WF Metal (+V G ) Gate Dielectric E 1e Bottom Gate p+ Source n+ Drain Top Gate V body E 1h Gate Dielectric Large WF Metal (-V G ) t body Energy band diagram of channel (off-state)

19 V body as a Function of Body Thickness at Eigenstate Alignment 19 Ox Si Ox V total V body V body is potential across the Si body As t body, the quantization energy and V body Since InAs has very small electron mass, 0.023m o, its quantization energy rapidly at small t body

20 Si: Gate Leakage Current as fn t body, EOT 20 Ox Si Ox V total V body V total at Eigenstate Alignment log 10 J gate at Eigenstate Alignment A/μm Leakage current interpolated from Si nfets Metal/HfO 2 /SiO 2 /Si gate stack EOTs: 0.61 to 0.97 nm fn E field, EOT Larger body thickness and EOT required for less gate leakage Assumes 50-nm gate length T. Ando, et al., IBM, IEEE Electron Device Letters, 2011.

21 InAs: Gate Leakage Current as fn t body, EOT 21 V total at Eigenstate Alignment log 10 J gate at Eigenstate Alignment A/μm Ox InAs Ox V total V body Assumes gate leakage for a specific E-field is the same for HfO 2 on InAs as for HfO 2 on Si Similar leakage current for InAs as Si Less body voltage for eigenstate alignment at large t body for InAs compared to Si, BUT: Efield is higher in the dielectric for InAs-case because ε InAs ~1. 3ε Si T. Ando, et al., IBM, IEEE Electron Device Letters, 2011.

22 22 Conclusion Fabricating InAs/GaSb structures to study 2D-2D QW tunneling MOS Capacitor CV Analysis D it > #/(cm 2 ev) on bulk InAs MOS HEMT results with InP cap and High-K are promising Tunnel Diode IV Analysis Suggests need for lateral contacts to study QW/QW structure Steeping stone to TFET structure