Enhanced Mobility CMOS

Transcription

1 Enhanced Mobility CMOS Judy L. Hoyt I. Åberg, C. Ni Chléirigh, O. Olubuyide, J. Jung, S. Yu, E.A. Fitzgerald, and D.A. Antoniadis Microsystems Technology Laboratory MIT, Cambridge, MA Acknowledge support: DARPA, MARCO MSD, SRC 1

2 Outline Introduction Global and local stress techniques for CMOS performance improvement Beyond the first generation Summary 2

3 Introduction to MOSFET Scaling Challenges S/D extension Electrostatics Parasitics: Source/Drain Series resistance Gate dielectric leakage Gate electrode depletion Channel Transport S Channel G halo D 3

4 Electrostatics: Issues and Approaches As L is reduced, gate loses control of channel charge Short channel effects Technology solutions: Thin Si body Double or triple-gate structures (non-planar) G Channel L halo x j, ext S oxide Si D oxide Thin body MOSFET 4

5 Parasitics: S/D Series Resistance Source/drain series resistance is a significant I DS limitation with scaling Dopant solubility limits Lateral profile abruptness R S L x j, ext Technology solutions: Elevated source/drain Contact geometry Schottky barrier source/drain oxide 5

6 Gate Leakage Current Density (A/cm 2 ) Parasitics: Gate Insulator Leakage EOT Oxy-nitride (calc.) J g (limit) Source: 2003 ITRS High performance logic Year Equivalent Oxide Thickness, EOT (nm) I DS = W Q inv vel. Q inv = C ox (V gs V t ) C ox = k ox ε o T ox EOT = 3.9 T physical k Beyond 2007, oxy-nitride not expected to meet gate leakage requirements 6

7 Gate Insulator Leakage: High K TiN/HfO 2 gate stack W. Tsai, IEDM 2003 (IMEC) EOT = 3.9 T physical k Higher K enables sub-1-nm EOT scaling with gate leakage current < 5 A/cm 2 However, numerous issues, including loss of mobility High K not expected until 45 nm node 7

8 Parasitics: Gate Electrode Depletion Gate Electrode Depletion: Lower inversion charge density effectively limits EOT scaling Solution: metal gates (high carrier density) may also assist with high k mobility issues R. Chau, et al., Intel, Nov Metal gate Poly-Si gate Gate stack considered as a complete package: Channel, dielectric, electrode 8

9 MOSFET Scaling Challenges: Channel Transport & Universal Mobility Effective Electron Mobility µ eff (cm 2 /sec V) Universal mobility 7x x x x10 18 cm -3 Strained Si ~ 2X Vertical Effective Field E (MV/cm) eff Mobility decreases as channel doping increases Bulk Si MOSFET mobility data from Takagi, et al., TED, 1994 Solution: Strain enables new universal mobility curve 9

10 Importance of Mobility in Sub-50 nm Silicon MOSFETs I DS = W Q inv v xo Measured Velocity Thermal Velocity Lochtefeld, et al., (MIT), EDL % V ds =V gs =1.5V 25 nm M.C. 40 nm exp. 70 nm exp. Decreasing L eff, T ox V GS = V DS = V dd V S V G V D Q i (x o ) v xo E C 0 x L CH x o State-of-the-art MOSFETS are far from ballistic: improving the channel mobility still matters 10

11 Impact of Enhanced Mobility on Drive Current Mobility Enhancement in Strained Si Channel/Relaxed SiGe n-mosfets v elec. = g mi / C OX (cm/sec) ε OX / C OX = 67 A Strained Si Epi Si Control L poly (µm) Rim, Hoyt, Gibbons IEDM Intrinsic Transconductance, g mi (ms/mm) 67 Å 130 Å 750 Å 6000 Å 1.5 µm LTO Spacer 1800 A n + poly gate oxide p-strained Si n + p + Si 0.8 Ge 0.2 n Punch-through stop + p-relaxed Si 0.8 Ge 0.2 p-si 1-x Ge x Graded Layer p + Si Substrate x = 0.2 x = 0.05 Enhanced-mobility strained Si n-mosfet test structure Biaxial strain increases electron mobility above the universal MOS curve Mobility enhancements! I d and g m improvements at 100 nm channel length 11

12 I D I D Drain Current Increase I Dsat Increase is Correlated to Mobility K L=45nm L=45nm L=100nm Slope = 0.5 intrinsic Electron Mobility Increase µ n µ n I Observe D µ ~ 0.5 n I D µ n Drain current increased for given L and DIBL 12

13 Improving the Performance of Digital and Analog Circuits Impact of I d and g m enhancement, for constant sub-threshold swing: improved logic switching speed: Gate delay τ = CV/I on I D ON V t Swing S assume I on increased by 20% V t reduced leakage power trade 20% I on increase for 20X decrease in I off increased F t for analog MOS OFF I off decreased by 20X V V G 13

14 Outline Introduction Global and local stress techniques for CMOS performance improvement Beyond the first generation Summary 14

15 Number of Strained Si papers R&D in Strained Si Technology: Global Stress Techniques Å 1 µm 1993 Source n+ poly 1996 SiO Drain n+ Strained Si n+ Relaxed Si0.7 Ge0.3 Relaxed Graded Si1-yGe y layer y = 0 to µm ~ ~ Si substrate IEDM Conference Year (Dec.) 2003 Strained Si/SiGe Equilibrium Si 1-x Ge x Si Pseudomorphically Grown Tensile-Strained Si on Si 1-x Ge x Si Relaxed Si 1-x Ge x Breakthroughs in growth/materials/physics ~ 1990 ITRS Roadmap, 2001, Emerging Devices: Band-engineered transistor 15

16 Conduction Bands for Unstrained Si MOS SiO 2 Unstrained Si MOS 2 E c Unstrained Si MOS 4 2 [001] [010] 4 [100] Bulk Si 16

17 Effects of Strain on Conduction Bands Unstrained Si MOS 2 E C Strained Si MOS 2 Unstrained Si MOS 4 Strained Si MOS 4 1 E 3 s 2 E 3 s E tot Additional band splitting E s ~ 67 mev/10% Ge More electrons in lowest valley 2 (smaller m c *) Reduced intervalley scattering (larger E tot ) " Enhanced in-plane mobility (phonon-limited) 17

18 Mobility Measurements on Strained Si CMOS Rim, et al., VLSI Symp., 2002 (IBM) (STI, CMOS wells, halo implants, raised S/D, 2.2 nm t ox ) NMOS PMOS 13% Ge 28% Ge Peak mobility enhancements ~ 2X (electrons) and ~1.6X (holes) Hole mobility enhancement decreases with increasing vertical field 18

19 Valence Band: Oversimplified Strained Si Relaxed SiGe Unstrained Si E Γ k HH LH in-plane Strained Si E out-ofplane k Valence band degeneracy lifted ( E s ~ 40 mev/10% Ge) Reduced inter-band scattering and band deformation 19

20 High K Dielectrics with Strained Si Surface Channels Rim, et al., VLSI Symp., 2002 (T inv = 2.8 nm, 15% Ge substrate, poly-si gate) Strained Si can be used to recover mobility degradation associated with HfO 2 20

21 Continued EOT Scaling: HfO 2 + Metal Gate with Strained Si/Relaxed SiGe Datta, et al., IEDM, 2003 (Intel) (T inv = 1.4 nm, 10% Ge substrate, TiN gate) Metal gate improves mobility for thin HfO 2 dielectrics (screening effect) Mobility recovered to unstrained Si universal curve value with 10% Ge substrate at 1.4 nm EOT with HfO 2 dielectric 21

22 Number of Strained Si papers Global stress Local stress R&D in Strained Si Technology IEDM Conference Year (Dec.) two major categories: global stress (e.g. strained Si/SiGe, biaxial tensile stress) local stress control or process-induced stress STI, Cap layer, Silicide Schematic after C.-H. Ge, IEDM 2003 increase in IEDM papers in both categories in last three years 22

23 Local Stress: Optimizing Existing Processes for 3D Stress Control C.-H. Ge, et al., IEDM 03 (TSMC) Direction of stress with respect to current flow is important Tensile strain along y (W) believed to be beneficial for N- and P-MOS Effects increase as device is scaled in L and W 23

24 Example of Local Stress Technique T. Ghani, et al., IEDM 2003 (Intel) Intel demonstrated large I d (700 to 800 µa/µm) at 90 nm node for p-mosfets with selective SiGe in the source/drain regions n-mos I d enhancement ~ 10% PMOS NMOS 50% µ p enhancement at 1 MV/cm 24

25 Outline Introduction Global and local stress techniques for CMOS performance improvement Beyond the first generation of global and local stress techniques SSDOI Dual-channel MOSFETs Summary 25

26 Strained Si-Directly-on-Insulator Technology Potential advantages: better performance (as for SOI) eliminates processing and manufacturing issues associated with the thick SiGe layer T. Drake, et al., J. Elec. Mat., Sept Oxide suitable for ultra-thin body transistors that may replace the bulk MOSFET 10 nm-thick strained Si Poly-Si 10 nm strained Si directly on insulator (SSDOI): biaxial tensile stress SiO 2 Strained Si 3.7 nm Defected region BOX 30% SSDOI, I. Aberg, et al., VLSI

27 Fabrication of SSDOI Using Bond and Etch-Back Handle Wafer Strained Si LPCVD SiO 2 Strained Si LPCVD SiO 2 Strained Si Etch stops Relaxed Si 1-y Ge y Strained Si Relaxed Si 1-y Ge y Relaxed Si 1-y Ge y Strained Si Relaxed Si 1-y Ge y Relaxed Si 1-y Ge y Strained Si Relaxed Si 1-y Ge y Si 1-x Ge x grade Si 1-x Ge x grade Si 1-x Ge x grade CZ Silicon (p-) CZ Silicon (p-) CZ Silicon (p-) Si 1-x Ge x grade x ~ 22% Final SSDOI structure Relaxed Si 1-y Ge y Strained Si Relaxed Si 1-y Ge y Strained Si Strained Si Relaxed Si 1-y Ge y Strained Si LPCVD SiO 2 Handle Wafer Relaxed Si 1-y Ge y Strained Si LPCVD SiO 2 Handle Wafer LPCVD SiO 2 Handle Wafer 27

28 Enhanced Thermal Stability of SSDOI Unstrained Si Raman Intensity No RTA 600C 10 sec 800C 10 sec 950C 1 sec Silicon SSDOI T.S. Drake et al., ICSI3, Santa Fe, Mar See also: T. Langdo, et al., 2002 IEEE SOI Conf., p. 211 K. Rim, et al. IEEE IEDM, p. 49, Wavenumber (cm-1) Raman shift consistent with stain level for Si/SiGe (29%) No change in strain upon thermal annealing of SSDOI 28

29 Electron Mobility in SSDOI I. Aberg, et al., VLSI 2004 Effective Mobility (cm 2 /Vs) NMOS 96% 100% 30% SSDOI, ~15 nm 24% SSDOI, ~18 nm % SOI * Effective Electric Field (MV/cm) * Universal Mobility S. Takagi et al., IEEE TED 41, p. 2357, 1994 Electron mobility enhanced by 80% compared to Universal Mobility 29

30 Effective Mobility (cm 2 /Vs) Hole Mobility in SSDOI PMOS 127% * 40% SSDOI, 6 nm 30% SSDOI, 8 nm 54% 15% SOI, 12 nm Effective Electric Field (MV/cm) Large enhancements, even for thin silicon films * Universal Mobility S. Takagi et al., IEEE TED 41, p. 2357,

31 Hole Mobility in 40% SSDOI Effective Mobility (cm 2 /Vs) "universal" SOI 40% SSDOI 14 nm thick Hole Density (x10 13 cm -2 ) I. Aberg, et al., IEDM 2004 Strained Si Thickest 40% SSDOI to date: 14 nm (26 nm as grown) Enhancement at high inversion charge density Si 17 31

32 Hole Mobility vs. SSDOI Thickness Peak Field Effect Mobility (cm 2 /Vs) % SSDOI SOI PMOS 30% SSDOI 100 N D ~ 5x10 16 cm Silicon Thickness T (nm) Si µ FE µ eff equal at max point Film thickness suitable for PDSOI (today s technology) - process integration for SSDOI is similar to SOI 32

33 Dual-Channel Heterostructures Fitzgerald, Antoniadis, et al. Goal: nearly symmetric n- and p-mosfets Leverage high hole mobility in high Ge content compressively strained SiGe V T tunable by varying strain/ge fraction SS and charge control can be an issue for p-mosfets Strained Si (Tsi) Strained Si 0.4 Ge 0.6 (12nm) Relaxed Si 0.7 Ge 0.3 buffer Graded SiGe Si substrate E v E c Drain Current (ma) Si N/PMOS SiGe NMOS (Tsi=4.6nm) SiGe PMOS(Ttsi=1.6nm) Vg-Vt=1,2V Drain Voltage (V) J. Jung el al., EDL

34 Mobility Enhancement in Dual-Channel MOSFETs Mobility Enhancement Factor 11 nm NMOS Si 0.4 Ge 0.6 (strained) Si = 10 nm Strained Si cap = 3 nm NMOS Si 0.7 Ge 0.3 (relaxed) Si = 5 nm Strained Si Vertical Effective Field (10 5 V/cm) Mobility Enhancement factor E v E c PMOS PMOS J. Jung, et al., EDL, Aug Strained Si cap = 3 nm Si = 5 nm Si = 10 nm Vertical Effective Field (10 5 V/cm) large mobility enhancements for BOTH n- and p-mosfets 34

35 High Hole Mobility in Strained SiGe-Channel MOSFETs 1200 Effective Mobility (cm 2 /Vs) %SSDOI Dual-Channel PMOS 60/30 100% Ge strained to 50% Substrate (M.L. Lee, et al.) 80/50 Unstrained universal NMOS: 20% Ge Strained Si Si-channel PMOS Intel Vertical Effective Field (MV/cm) dual-channel hole mobilities much larger than for other technologies largest gain for strained Si/strained Ge on 50% (2X electron, 10x hole) 35

36 Evolution of Engineered Substrates Bulk Strained Si Strained Si 0.4 Ge 0.6 Si Si Relaxed Si 0.7 Ge Si bulk 2. strain-si/sige bulk 3. Dual channel high mobility, degraded SS and thick relaxed SiGe Si SOI Strained Si Strained Si 0.5 Ge 0.5 Si oxide Si 4. SOI 5. SSOI and SSDOI Si oxide HOI 60 on 30 (combines benefits of dual-channel with FDSOI) 36

37 Novel Silicon Heterostructures on Insulator (HOI) XTEM 25 nm NMOS I. Aberg, et al., IEEE SOI Conf., Oct nm gate oxide 20 nm 12 nm Poly-Si 10 nm Strained Si Strained SiGe (50% Ge) Buried Oxide 3 nm gate oxide 3 nm Strained Si (original substrate was 24% Ge) PMOS p+ + p+ BOX NMOS - n+ n+ BOX HOI combines benefits of dual-channel and fully-depleted SOI: high mobility for electrons & holes with ideal sub-threshold swing 37

38 Device Fabrication on HOI Isolation Dry etched mesas Gate oxide Wet oxidation, 650ºC 3.5 nm N+ poly gate for both NMOS and PMOS HOI S/D anneal 850ºC, 10 s SSDOI and SOI reference annealed at 1000ºC, 10 s S N+ poly BOX D 38

39 PMOS Subthreshold Characteristics I. Aberg, et al., IEDM 2004 I D (A) FD-HOI PMOS: SS = 66 mv/dec. V DS = -50mV, -1V gate: N+ poly W/L= 160 / 0.5 ε-si cap ~ 7 nm V (V) GS Subthreshold Swing (mv/dec) PMOS bulk dual-channel (Jung, et al.) HOI (Aberg) SOI Si cap thickness (nm) Subthreshold characteristics improved over bulk dual-channel: 66 mv/dec. 39

40 Electron Mobility: HOI vs. SSDOI Effective Mobility (cm 2 /Vs) univ. mob 75% SOI 30% SSDOI 24% SSDOI I. Aberg, VLSI '04 Lines: SSDOI Symbols: HOI B: 46/30 A: 46/ Effective Electric Field (MV/cm) Strained Si (y) Strained Si 1-z Ge z Strained Si (y) BOX Split: z/y A: 46/24 B: 35/30 HOI electron mobility enhancement 75 % similar to SSDOI 40

41 HOI Hole Mobility Effective Mobility (cm 2 /Vs) nm t cap = 2 nm I. Aberg, et al., IEDM 2004 PMOS A: 46/ C: 35/24 120% 107% 100 ~4 nm SOI Hole Density (x10 13 cm -2 ) t cap Strained Si (y) Strained Si 1-z Ge z Strained Si (y) BOX Split: z/y A: 46/24 C: 35/24 Mobility enhancement >100% for all N inv 41

42 Simulated Hole distribution Hole Density (cm -3 ) nm strained Si (y = 0.24) N inv = 1x10 13 cm nm 1.7 nm Si 0.54 Ge Distance (nm) t ox = 3.5 nm 2D Simulation: DESSIS, density gradient model t cap Thick cap: mobility degraded, inversion in cap Thin cap: inversion in SiGe buried channel Strained Si (y) Strained Si 1-z Ge z Strained Si (y) BOX 42

43 HOI and SSDOI vs. SOI I. Aberg, et al., IEDM 2004 Mobility Enhancement Factor* HOI A: 46/ nm 7.1 nm t cap = 2 nm PMOS Hole Density (x10 13 cm -2 ) t cap 14 nm SSDOI ε-si (y) ε-si 1-z Ge z ε-si (y) BOX * Reference is universal mobility derived from S. Takagi et al. 15 nm Enhancement > 2X possible at all N inv 43

44 Challenge: Thermal Budget (SIMS: impact of 10 s RTA) [Ge] in SiGe (%) I. Aberg, SOI Conf., 2004 HOI initial 865ºC 965ºC Ge diffusion coefficient (cm 2/ s) Si 0.5 Ge 0.5 Si Temperature ( º C) Si SiGe Depth (nm) Si N.R. Zangenberg, et al. Phys Rev. Lett. 87 (12), p , s RTA at 965ºC peak Ge decreases by 10 atomic % poorer hole confinement and inability to make thin Si caps Need ultra-low thermal budget annealing 44

45 Other Challenges Activation of n-type dopants: more difficult as Ge content increases Thin Si cap (~ 1 nm): eliminate Si cap if gate insulator is SiGe-compatible Band-to-band tunneling will increase with Ge content in channel (may limit scalability of pure Ge, but on-insulator helps) Keeping an open mind: difficult to change channel materials, but that is key to higher transport Si! SiGe (p-fet)! Ge! III-V on Si 45

46 Summary Number of challenges for maintaining CMOS performance trends Strain is a critical path to enhance transport: Local, global and perhaps combined techniques Higher Ge content structures are promising: strained SiGe or Ge channel for p-mos strained Si channel for n-mos feasible in a single epi layer stack Heterostructure on insulator: Transfer of strained heterostructures to insulator Provides new opportunities and challenges 46