Physics an performance of III-V nanowire heterojunction TFETs including phonon and impurity band tails:

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1 Physics an performance of III-V nanowire heterojunction TFETs including phonon and impurity band tails: An atomistic mode space NEGF quantum transport study. A. Afzalian TSMC, Leuven, Belgium (Invited) A. Afzalian 1

2 Outline Motivations Mode Space approach for full band atomistic simulation Scaling perspective for ideal III-V broken gap nanowire TFETs Impact of phonon scattering and impurity band tails Conclusions A. Afzalian 2

3 Concept Availability of carrier filtering through BTBT Benefits Why III-V NW GAA Heterojunction TFETs (HTFETs)? Homojunction TFET Steep swing for low power (LP) operation (V DD < 0.5V) S ON-state Long L tunneling Low I ON D Broken gap III-V heterojunction TFET (HTFET): High I ON S InAs/GaSb ON-state Short L tunneling High I ON D Challenges Low I ON due to BTBT in the path of the current) High Quality material, interface, and d scaling for SS < 60 and low leakage IEDM 2016 Scaled d: Key for improved electrostatic control and SS 3

4 Experimental III-V NW HTFETs On-Current I on ( A/ m) InAs/GaSb V DD = 0.3 V [3] [4] n-tfet I off = 100 na/ m [1] InGaAs/InAs V DD = 0.5 V InA s/ Si V DD = 1 V GaAsSb/InGaAs V DD = 0.2 V [2] InAs/GaSb V DD = 0.3 V Junction Size (nm) [5] [1] Memisevic, IEEE EDL 2016 [2] Dey, IEEE EDL, 2013 [3] Tomioka, VLSI Symp, 2012 [4] Fujimatsu, IPRM, 2012 [5] Zhao, IEDM, 2014 trends of improved I ON with d scaling sub 10 nm wires? III-V ptfet? 4

Computational challenge to assess performances of sub 10 nm III-V NW HTFETs d 6 scaling d 4 scaling BTBT + quantum confinement + heterojunction : Most

5 Computational challenge to assess performances of sub 10 nm III-V NW HTFETs d 6 scaling d 4 scaling BTBT + quantum confinement + heterojunction : Most expansive full band (e.g. Tight binding) quantum transport (e.g. NEGF) models NW: Full 3D simulation (3D geometry) (NW GAA (3D) time/iv 100 planar DG (2D) 5

6 Mode Space approach for full band atomistic simulation A. Afzalian et al. IEDM speedup <<d 6 scaling <RAM/10 <<d 4 scaling BTBT: Most expansive full band (e.g. Tight binding) quantum transport (e.g. NEGF) models Full 3D simulation (3D geometry) We have developed an efficient, accurate and innovative full-band mode space (MS) NEGF technique 6

7 Accuracy of Atomistic Mode Space (MS) technique A. Afzalian et al. VLSI-TSA 2016 (invited) 10 orbitals/atom MS vs. RS GaSb source InAs channel d = 5.45 nm InAs drain RS MS InAs / GaSb NW TFET [100] InAs/GaSb NW HTFET with > atoms MS Speed up >150 Error <1% A. Afzalian 7

MS principle: Hamiltonian (H) size reduction by an incomplete basis transformation Reducing H size means loss of information Equivalent in a desired (smaller) energy range E-k points sampling to

8 MS principle: Hamiltonian (H) size reduction by an incomplete basis transformation Reducing H size means loss of information Equivalent in a desired (smaller) energy range E-k points sampling to construct the MS basis (o) BS obtained using optimized MS basis ( ) vs. RS basis [100] InAs NW slab, d = 5.45 nm, sp 3 s * _so) MS H size is 5% of RS one Blue: Full Model (Real space (RS)) Red: reduced rank Model (Mode space (MS)) A. Afzalian et al. IWCE

9 Unphysical branches Problem with MS Tight-binding (TB) Traditional effective masslike MS basis Optimized MS basis ok (A. Afzalian et al. IWCE 2015) Tailor extra basis vectors* MS Speed up >150 Error <1% Blue: Full Model (Real space (RS)) Red: reduced rank Model (Mode space (MS)) This study: >50 MS bases, speedup up to 10,000 *Mil nikov et al.,prb 85, (2012), A. Afzalian et al. arxiv: [cond-mat.mes-hall] (2017) 9

Reduction ratio (r) vs d Initial InAs MS

d InAs/GaSb NW ntfet sp 3 s * SO Optimized

2 nm N atoms d 2 n modes << d 2 r=5% r= 1%

10 Reduction ratio (r) vs d Initial InAs MS bases d = 5.45 nm d = 18.2 nm Averaged r vs. d InAs/GaSb NW ntfet sp 3 s * SO Optimized InAs MS bases d = 5.45 nm d = 18.2 nm N atoms d 2 n modes << d 2 r=5% r= 1% # of UM s and challenge to clean MS bases: d r and speed up improves with d (A. Afzalian et al. arxiv: [cond-mat.mes-hall] (2017))

MS performances vs. d (A. Afzalian et al. SSDM 2017, invited, A. Afzalian et al. arxiv:1705.00909 [cond-mat.mes-hall] (2017)) InAs-GaSb NW ntfet 10.000 speedup d = 18.

11 MS performances vs. d (A. Afzalian et al. SSDM 2017, invited, A. Afzalian et al. arxiv: [cond-mat.mes-hall] (2017)) InAs-GaSb NW ntfet speedup d = 18.2 nm atoms!! <<d 6 scaling sp 3 s * _so d = 5.5 nm atoms RAM/100 <<d 4 scaling r and MS performances d MS enabled d, #atoms NW ever atomistically simulated.

Validation to fabricated III-V InAs NW MOSFET: (A. Afzalian et al. SSDM 2017, invited, A. Afzalian et al. arxiv:1705.00909 [cond-mat.mes-hall] (2017)) [100] d = 5.

12 Validation to fabricated III-V InAs NW MOSFET: (A. Afzalian et al. SSDM 2017, invited, A. Afzalian et al. arxiv: [cond-mat.mes-hall] (2017)) [100] d = 5.5 nm. L = 15 nm. [111] d =12 nm. L = 300 nm. sp 3 s*_so basis MOCVD grown InAs wire (T. Vasen et al. VLSI 2016) (a) (b) S InAs NW Gate D V D = 0.5V InAs NWs InAs Sub. (c) SiO 2 Back-Gate GAA Flow NW Growth High-k ALD Gate Metal Sputter NW Transfer to SiO 2 sub S/D Litho Gate Metal Wet Etch High-k Etch S/D Deposition + Liftoff Gate Pad Litho+Dep.+Liftoff Post Metallization Anneal Good Match with measured BTBT current Ballistic ratio (d) of 75% Support experimental program development

13 Scaling perspective for III-V broken gap nanowire TFETs 13

Simulated ideal (n)tfet devices: For each L, optimization on d, channel orientation, doping profiles, pockets, drain underlap Channel orientation:[100], [110], [111] d = 4 7 nm InAs I - channel InAs

14 Simulated ideal (n)tfet devices: For each L, optimization on d, channel orientation, doping profiles, pockets, drain underlap Channel orientation:[100], [110], [111] d = 4 7 nm InAs I - channel InAs N + Drain N D ~1-10x10 18 cm -3 P GaSb P + Source N S N I Underlap (I) L UND N InAs N+ Pocket N P, L P Perf. boost: 2-3 Gate length L = nm Gate oxide nm of Al 2 O 3 EOT planar 0.7 nm, Dit=0 Tight Binding basis = sp 3 s* with SO (SO: spin orbit coupling, 10 orbitals /atom) 14

15 Optimized LP GAA NW InAs/GaSb TFETs vs. Si nmosfet ntfet TFET: V DD =0.3V MOSFET: V DD =0.45V ptfet Si nmos For each L, optimization on d, channel orientation, doping profiles, pockets, drain underlap. TFET performance degrades quickly for L < 20 nm A. Afzalian et al. IEDM

16 Strong TFET performance degradation with L: Short channel effects: ntfet TFET: V DD =0.3V MOSFET: V DD =0.45V ptfet Si nmos For each L, full optimization 1) Increased Source-to-drain tunneling (SDT) at shorter L reduces design window (channel orientation,drain doping) 16

17 E (ev) Source to drain tunneling (SDT) Optimized [100] ntfets ntfet, L = 12 G = 70 mv SDT degrades SS I ON E V-GaSb J(E) [A/eV] SS x (nm) SDT degrades TFET performances (SS -> I ON ) for L 20 nm Mitigation: L eff ( N D, underlap) 17

18 SDT vs. channel orientation: ntfet L = 20 nm: less SDT L = 12 nm: more SDT SDT [111]/[110]: T ON (Smaller E geff, lower m*) +50% I ON at L=20nm [100] : less SDT, but T ON : best at L = 12 nm A. Afzalian 18

19 SDT vs. channel orientation: ptfet L = 20 nm L = 12 nm [111]: best performance (+ 30% I ON ) at L = 20 nm [100] : best at L = 12 nm A. Afzalian 19

20 Drain engineering: trade-off *A. Afzalian et al. VLSI-TSA 2016 (invited), A. Afzalian et al. arxiv: [cond-mat.mes-hall] (2017) Balanced N D and optimized drain underlap for maximizing I ON at a given V D (V DD ) and I OFF spec. OFF leakage improves with N D ON current improves with N D Physical limiting mechanisms: Ambipolar current, SDT Physical limiting mechanism: on-current saturation A. Afzalian 20

21 E (ev) E (ev) Drain engineering: on-current saturation* *A. Afzalian et al. VLSI-TSA 2016 (invited), A. Afzalian et al. arxiv: [cond-mat.mes-hall] (2017) N D = 5x10 18 V G = 0.45 V N D = 1x10 18 E Fs E Cch DV G N D = 1x10 18 E Cd E Fd V D = 0.35 V E Cs x (nm) V G = 0.35 V 21 I ON saturates as Tunneling windows does not increase with V G : Max. windows is E Fs E Fd = V D (ev) smaller if S or D band edges are non-degenerated (e.g. N D is too low) E Fs E Vs E Cch E Vch x (nm) N D = 1x10 18 E Fd 5x10 18

22 Optimal doping vs. DD = 0.3V n, L =20 [100] n, L =12 p, L =20 SDT/I ON sat p, L =12 Increased SDT at L = 12 nm reduces optimal drain doping penalty on I ON : Ptfet is most affected: VB-DoS D I ON saturation 22

23 Strong TFET performance degradation with L: Short channel effects: d = 5.5 d = 6.5 Si nmos d = 5.5 d = 5.5 d = 5.5 Optimal d [nm] 2) d scaling below ~5.5 nm is not effective for TFET (especially for ptfet) 23

24 ptfet Optimally balanced InAs/GaSb TFET transport ~5.5 nm L = 20 nm L = 12 nm [100], [111] d : SS ( Electrostatic control, m*, DoS, E geff ) d : on-regime : Area, T ON ( m*, E Geff ), I ON saturation (DoS D ) Optimal performances at d ~ 5.5 nm both for L = 20 and 12 nm 24

25 Energy delay LP benchmark I OFF = 50 pa/ m p n p L = 20Si V DD = 0.5 V V DD = 0.3 V L = 20 L = 12 Si Including extrinsic of an unloaded inverter cell with 3 NW/device 25

26 Impact of Fundamental sources of non-idealities: A. Afzalian 26

Inelastic collisions may strongly degrade TFET BTBT filtering action What is the impact on SS

27 TFET: Electron-Phonon scattering: e-ph scattering is an intrinsic/ fundamental source of non ideality. Inelastic collisions may strongly degrade TFET BTBT filtering action What is the impact on SS and I ON? Strong inelastic coupling ( 5) Ballistic (close to onset) J(E) [A/eV] E C-InAs J(E) E V-GaSb E C-InAs? n + pocket Weak inelastic coupling ( 1) J(E) E C-InAs A. Afzalian 27

28 InAs/GaSb TFET: Electron-Phonon scattering (A. Afzalian et al. SSDM 2017, invited) SS and performance not strongly degraded (< 10 %) for low power CMOS application (weak inelastic coupling ( 1)) Using efficient Mode Space Form Factor Method*: Use equivalent MS expression directly. Efficient in case of local scattering. in dq iq x ( x x ) n v', kl v, mm' ( x1, x2, E) e M q Nq 1 2 Gv' kl ( x1, x2, E q ) Fv, mm' ( x1, x2, q 3 t ) (2. ) 2 2 v', k, l q ballistic --o-- e-ph Acoustic, optical and polar optical (local) phonons Local Form factor*: simplifies as product of MS basis vectors F v', kl v, mm' v, m v, m' v', k v', l ( y, z; x ). ( y, z; x ). ( y, z; x ). ( y, z; x ) dydz ( x1 ) *A. Afzalian JAP 110, (2011)

Discrete Impurity (DI) Band tails: (DI = main source of band tails in doped

64 (1992) 755 p+ ~ 5 DI Smooth DI center DI star5 GaSb S p+ ~ 5 DI InAs Pocket n+ ~ 5

29 Discrete Impurity (DI) Band tails: (DI = main source of band tails in doped crystalline semiconductor*) Band tails* DI s create non-uniform spatial potential profile Spatially varying onset of tunneling What is the impact on SS and I ON? *P. Van Mieghem, Rev. Mod. Phys. 64 (1992) 755 p+ ~ 5 DI Smooth DI center DI star5 GaSb S p+ ~ 5 DI InAs Pocket n+ ~ 5 DI E VGaSb E C-InAs n+ ~ 5 DI DI DI DI center star5 diagonal DI s simulated in an atomistic fashion on atomic sites** 29 **A. Afzalian et al., EDL (2012) 33 (9) 1228

30 Energy delay LP benchmark I OFF = 50 pa/ m Si V DD = 0.5 V Including e-ph + DI: TFET Performance advantage for LP is not fundamentally lost ( EDP 20%) TFET ideal e-ph+di V DD = 0.3 V Si V DD = 0.3 V Including extrinsic of an unloaded inverter cell with 3 NW/device 30

31 Conclusions Capability to simulate in an atomistic fashion million atoms III-V NWs using an innovative and efficient TB mode space (MS) NEGF technique. In-depth atomistic study of scaling potential of III-V GAA NW HTFET. n- and ptfet performance best above L =20 nm (d= 5.5 nm, [111] orientation). L =20 nm, V DD = 0.3 V can deliver same speed as DD = 0.5V but with ~3 power =12 nm (LP ITRS 2.0 HGAA beyond 5 nm node), [100] orientation best but 3 I ON and 2.4 EDP performance degradation vs. the 20 nm GAA design. Scattering and DI band tails do not fundamentally degrade steep slope and LP performance advantage of III-V NW HTFET. A. Afzalian 31

32 Acknowledgements Experimental III-V NW device: P. Ramvall, T. Vasen, M. Holland and M. Passlack (TSMC), C. Thelander, K.A. Dick, L.-E. Wernersson (Lund University). Support with NEMO5 coding: D. Lemus and T. Kubis (Purdue University). Thank you for your attention! (Invited) 32

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