Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire MOSFETs

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42nd ESSDERC, Bordeaux, France, 17-21 Sept. 2012 A2L-E, High Mobility Devices, 18 Sept. Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire MOSFETs M.

1 42nd ESSDERC, Bordeaux, France, Sept A2L-E, High Mobility Devices, 18 Sept. Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire MOSFETs M. Koyama 1,4, M. Cassé 1, R. Coquand 1,2,3, S. Barraud 1, H. Iwai 4, G. Ghibaudo 2, and G. Reimbold 1 1 CEA LETI, 2 IMEP-LAHC INPG-MINATEC, 3 STMicroelectronics, 4 FRC, Tokyo Institute of Technology

2 Introduction - Si nanowire MOSFETs FD-SOI/high-k/mid-gap MG (Undoped channel) Higher mobility Reduction of random dopant fluctuation (RDF) No poly-depletion Almost symmetrical Id-Vg curve for N- and PMOS Source Gate Gate Mid-gap MG High-k Undoped Si FD-SOI FET Drain Drain BOX Application Si nanowire MOSFETs High immunity to short channel effect (SCE) and drain induced barrier lowering (DIBL) Better electrostatic control Lower off-current (I OFF ) Steeper subthreshold slope (SS) Gate Source BOX Si Tri-gate NWFET Source BOX Si Drain Omega-gate NWFET Advantages in downscaling and power consumption 2

3 Issues and challenges Quantum confinement of carriers Downscaled cross-section of NW below 20nm 20nm Contributions of different crystallographic orientation Tri-gate: top surface and side-walls Ω-gate, GAA: rounded (omega-shaped, cylindrical) surface Stress engineering Improvement of device performance Promising solution to further scaling of CMOS technology Combination of NW architecture and stress 3

4 Purpose Understanding of carrier transport in SOI and ssoi Tri-gate and Omega-gate SiNW MOSFETs Influence on carrier transport - Channel shape Tri-gate vs Omega-gate - Width dimensions NW down to 10nm - Uniaxial tensile strain H Gate W Si Source BOX Si Drain Gate Si Source BOX Si Drain Measurement Carrier mobility on N- and PMOS NW FETs down to low temperature 4

5 Measured Si nanowires Gate stack: HfSiON(2nm)/ALD-TiN(5nm)/poly-Si(50nm) SOI and ssoi wafer Unstrained and strained NW - 50 channels NWs - Long channel transistors with Lg=10µm R.Coquand et al., Symp. VLSI Tech., p.13 (2012). Effective mobility extraction by conventional split C-V technique 5

6 Basic characteristics: Id-Vg curves I d /W tot (µa/µm) Vd=0.9V Vd=40mV W=10nm H=11nm Tri-gate Vd=40mV Vd=0.9V Ω gate Vd=40mV Vd=0.9V V g (V) No I ON difference Vd=0.9V Vd=40mV W=23nm H=10nm Unstrained TG vs ΩG NWs Vd=0.9V Vd=40mV ssoi-tg Vd=40mV Vd=0.9V SOI-TG Vd=40mV Vd=0.9V V g (V) Vd=0.9V Vd=40mV Vt shift Strained TG W=16nm H=10.5nm Unstrained vs strained TGNWs NMOS: I ON enhancement Vt shift ~ 40mV PMOS: I ON deterioration Subthreshold slope (SS) ~ 70mV/dec: Well behaved characteristics 6

7 Scattering-limited mobility in MOSFET Effective mobility, µ eff Coulomb scattering Low Surface roughness Phonon scattering scattering High Temperature Total mobility S.Takagi et al., Trans. Electron Dev., 41, 2357 (1994). Inversion charge density, Phonon scattering (PS) depends on temperature (T) Coulomb scattering (CS) Surface roughness scattering (SRS) T independent Carrier transport is limited by 3 scattering mechanisms 7

8 Temperature dependent mobility <TGNW vs Wide FET> Effective Mobility (cm²/vs) NMOS TGNW: W=10nm T=20K T=300K ( cm -2 ) TGNW Wide FET Wide FET Effective Mobility (cm²/vs) Wide FET: W=10µm PMOS K 300K ( cm -2 ) TGNW Wide FET High T=50K T=300K Tri-gate NW NMOS: Mobility high PMOS: Small mobility high Maximum peak position shift to lower 8

9 Contribution of surface orientation to effective mobility Maximum mobility in unstrained wide FET Si surface orientation Top surface () Side-walls (110) µ eff_max (cm 2 /Vs) in SOI Electron (NMOS) Hole (PMOS) Gate [110] Source BOX Si Drain Top Si() Side-wall Si(110) Advantage Si()//[110] (top surface): electron transport Si(110)//[110] (side-walls): hole transport H.Irie et al., IEDM Tech. Dig., 225 (4). Electron mobility degradation Hole mobility enhancement as the width decreases Nanowire: Increasing the contribution of (110)-oriented side-walls 9

10 Extracted top and surface mobility in Tri-gate NW Effective Mobility (cm²/vs) ~µ C TGNW: W=10nm µ top µ side-wall Tri-gate NW ( cm -2 ) NMOS ~µ SR_top T=K µ ~µ SR_side-wall total eff Effective Mobility (cm²/vs) = W top() 2H µ eff + W + 2H W + 2H µ µ top µ side-wall ( cm -2 ) Larger contribution of (110) side-wall PMOS ~µ SR_side-wall ~µ SR_top side wall(110) eff T=K Maximum mobility (Coulomb and Phonon) Surface roughness-limited mobility 10

11 Temperature dependent mobility <TGNW vs ΩGNW> TGNW: W=30nm ΩGNW: W=23nm Effective Mobility (cm²/vs) NMOS ΩGNW TGNW T=20K T=300K Effective Mobility (cm²/vs) T=20K T=300K N 13-2 inv ( cm -2 ) ( cm -2 ) PMOS ΩGNW TGNW ΩG N- and PMOS Maximum mobility low T Lower Coulomb scattering due to H 2 anneal process 11

12 Stress effect on carrier transport along [110] (b) lateral strain relaxation s-si [110] [110] BOX BoX Biaxial vs uniaxial stress (~1.4GPa) - Biaxial tensile stress (in () plane) - Uniaxial stress along channel direction (Lateral strain relaxation) Mobility enhancement (degradation) from strain effect - Repopulation of Si conduction valleys - Reduction of intervalley phonon scattering Strain NMOS PMOS (transport //[110]) () (110) () (110) no strain biaxial tensile + - / = uniaxial tensile // [110] Uniaxial tensile stress along [110] direction: Improving electron mobility 12

13 Top width (W top ) dependent effective mobility <TG vs WG> µ eff (cm 2 High Tri-gate +55% = cm % NW Wide W top (µm) ssoi SOI NMOS µ eff (cm 2 High Ω-gate +50% +65% NW Wide W top (µm) Electron mobility degradation as the width narrowing = cm -2 ssoi SOI Uniaxial strained NW with ~50% gain in µ eff Still enhanced TG and ΩG devices exhibit almost the same mobility improvement - Strain relaxation - Piezoresistive properties Same in both geometries 13

14 Top width (W top ) dependent effective mobility <TG vs WG> µ eff (cm 2 High Tri-gate -30% = cm -2 ssoi SOI W top (µm) PMOS Ω-gate TG and ΩGNW represent roughly the same mobility Strained NWs; No mobility improvement as W top decreases µ eff (cm 2 High -25% = cm -2 ssoi SOI W top (µm) Uniaxial tensile strain for PMOS Counterbalance of better mobility in unstrained Si(110) Large mobility degradation for Si() top surface Agreement with NMOS 14

15 Temperature dependent mobility <SOI vs strained-soi> µ eff (cm 2 High NMOS ~µ SR_wide Unstrained = cm -2 Strained Tri-gate Ω-gate Tri-gate Ω-gate W=10nm W=10µm W=23nm W=10µm W=16nm W=10µm W=33nm W=10µm Temperature (K) Wide FET ~µ SR_wide ~µ SR_NW ~µ SR_NW Temperature (K) T>K T<K Phonon-limited mobility: Improvement from strain effect Mobility saturation from surface roughness scattering (SRS) SR-limited mobility: Small enhancement by strain effect Roughly same properties in both TG and ΩG geometries 15

16 Temperature dependent mobility <SOI vs strained SOI> µ eff (cm 2 High PMOS ~µ SR_NW ~µ SR_wide Unstrained Wide FET 500 = cm -2 Strained Tri-gate Ω-gate Tri-gate Ω-gate W=30nm W=10µm W=23nm W=10µm W=36nm W=10µm W=33nm W=10µm Temperature (K) ~µ SR_wide ~µ SR_NW Temperature (K) Whole T range Stress influence to mobility (Phonon- and SR-limited) Enhancement: Wide FETs Degradation: TG and ΩG NWs Same in both NWs Biaxial stress (wide FET): Improvement Uniaxial stress (both NWs): Deterioration 16

17 Temperature dependent maximum mobility Influence of phonon scattering µ max ~ µ phonon T γ Values of power law exponent γ Tri-gate Wide (10µm) NMOS SOI ssoi PMOS SOI ssoi w/o H 2 anneal NW Ω-gate Wide (10µm) with H 2 anneal NW Larger stress influence for NMOS Phonon-limited mobility Dependent on the strain effect Independent on channel shape width dimension 17

18 Conclusions Carrier transport in strained and unstrained TG and ΩG NWs i) Transport properties in TGNWs (down to 10nm 10nm section) Agreement with the contribution of different orientation Larger Si(110) side-wall contribution ii) ΩGNWs (down to W top-view of 23 nm) Roughly same mobility behavior as TGNWs Lower Coulomb scattering iii) Uniaxial strain in both nanowire geometries Enhancing NMOS performance Diminishing PMOS performance Phonon-limited and SR-limited mobility No significant difference from the channel shape 18

19 Modifiez les styles du texte du masque Deuxième niveau > Troisième niveau Thank you for Merci de votre your kind attention attention 19

20 Backup slides 20

21 Temperature dependent mobility <TGNW vs ΩGNW> TGNW: W=10nm W=30nm ΩGNW: W=23nm Effective Mobility (cm²/vs) NMOS ΩGNW TGNW (30nm) T=20K T=300K Effective Mobility (cm²/vs) N 13-2 inv ( cm -2 ) ( cm -2 ) NMOS ΩGNW TGNW (10nm) T=20K T=300K ΩG NMOS Maximum mobility low T Lower Coulomb scattering due to H 2 anneal process 21

22 Temperature dependent mobility <TGNW> TGNW: W=10nm vs W=30nm Effective Mobility (cm²/vs) NMOS T=20K T=300K ( cm -2 ) W=10nm W=30nm Larger contribution of (110) side-wall 300K 250K K 150K K 50K 20K Maximum mobility (Coulomb and Phonon) Surface roughness-limited mobility 22

23 Temperature dependent mobility <SOI vs strained SOI> µ eff (cm 2 High NMOS Tri-gate W=10nm W=30nm W=10µm Unstrained Ω-gate W=23nm W=10µm Wide FET ~µ SR_NW ~µ SR_NW = cm -2 Tri-gate W=16nm W=36nm W=10µm Strained Ω-gate W=33nm W=10µm Difference between W top =10nm & 30nm TGNWs Contribution of (110) side-walls 23

24 Extraction of µ top and µ side-wall contribution for Tri-gate NW Contribution of surface orientation to effective mobility µ µ total eff = W top() 2H µ eff + W + 2H W + 2H µ side wall(110) eff = α µ total eff W µ 2H top() eff side wall(110) eff W + 2H α = 2H J. Chen et al., Symp., VLSI Tech., p.32 (8). R. Coquand et al., Proc., ULIS conf. (2012). Si surface orientation Top surface () Side-walls (110) Electron (NMOS) + - µ eff (cm 2 /Vs) Hole (PMOS) - + H Gate [110] W Source BOX Si Drain Top Si() Side-wall Si(110) Scattering behavior on µ top and µ side-wall? 24

25 Scattering influence in µ top and µ side-wall of Tri-gate NW Effective Mobility (cm²/vs) ~µ C NMOS T=K T=300K ( cm -2 ) ~µ SR_top ~µ SR_side-wall µ top µ side-wall µ Si(110) TGNW: W=10nm µ side-wall ~ referential µ Si(110) Mobility limit Scattering mechanism Coulomb (µ C ) Surface roughness (µ SR ) µ top () Strong Weak µ side-wall (110) Weak Strong 25

26 Scattering influence in µ top and µ side-wall of Tri-gate NW Effective Mobility (cm²/vs) ~µ C ~µ SR_side-wall ~µ SR_top ( cm -2 ) PMOS T=K T=300K µ top µ side-wall µ Si(110) TGNW: W=30nm µ side-wall ~ µ high Mobility limit Scattering mechanism Coulomb (µ C ) Surface roughness (µ SR ) µ top () No difference µ side-wall (110) Similar slope 26

H 2 anneal impact in wide device Effective Mobility (cm²/vs) 1600 1400 1 0 800 600 400 Wide FET NMOS Wide FET: W=10µm 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.

27 H 2 anneal impact in wide device Effective Mobility (cm²/vs) Wide FET NMOS Wide FET: W=10µm ( cm -2 ) 300K 250K K 150K K 50K 20K Enhancement Coulomb-limited mobility SR-limited mobility ΩG_with H 2 (W=10µm) TG_w/o H 2 (W=10µm) PMOS ( cm -2 ) 300K 250K K 150K K 50K 20K Enhancement Coulomb-limited mobility 27

28 Mobility improvement from strain effect Mobility gain in Strained-Si nmosfet (tensile) Increase of the 2-fold valley occupancy (population) with lower conductivity mass Decrease the phonon scattering rate between the 2-fold and the 4-fold valleys (intervalley scattering) Strain effect for hole (tensile) Breking of the valence band degeneracy Reduction of conductivity mass 28

Fablication process Undoped FD-SOI wafer (Mesa isolation)

4 GPa NW patterning (DUV lithography) - with or w/o H 2

Gate patterning Spacer 1 formation S/D epitaxy (T Si

29 Fablication process Undoped FD-SOI wafer (Mesa isolation) - with or w/o biaxial tensile stress of ~1.4 GPa NW patterning (DUV lithography) - with or w/o H 2 anneal HfSiON(2nm)/ALD TiN(5nm)/poly-Si(50nm) gate stack Gate patterning Spacer 1 formation S/D epitaxy (T Si =18nm) LDD implantation Spacer 2 formation HDD implantation Silicidation Back-end 29

30 Basic characteristics: Id-Vg curves I d /W tot (µa/µm) Vd=40mV NMOS Vd=-40mV PMOS Tri-gate Omega-gate strained-tg strained-ωg I d /W tot (µa/µm) Vd=0.9V d tot Vd=-0.9V 6 4 Tri-gate Omega-gate strained-tg strained-ωg V g (V) V g (V) 0 30

Enhanced Mobility CMOS

Enhanced Mobility CMOS Judy L. Hoyt I. Åberg, C. Ni Chléirigh, O. Olubuyide, J. Jung, S. Yu, E.A. Fitzgerald, and D.A. Antoniadis Microsystems Technology Laboratory MIT, Cambridge, MA 02139 Acknowledge