FLCC Seminar. Spacer Lithography for Reduced Variability in MOSFET Performance

Transcription

1 1 Seminar Spacer Lithography for Reduced Variability in MOSFET Performance Prof. Tsu-Jae King Liu Electrical Engineering & Computer Sciences Dept. University of California at Berkeley Graduate Student: Ms. Xin Sun

2 2 Introduction Outline MOSFET scaling Lithography challenges Spacer Lithography Device Simulation Study Summary and Future Work

3 3 IC Technology Advancement Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistor Investment Transistor Scaling SMIC s Fab 4 (Beijing, China) Photo by L.R. Huang, DigiTimes Better Performance/Cost 100 International Technology Roadmap for Semiconductors Market Growth PITCH YEAR: HALF-PITCH: 90nm 65nm 45nm 32nm 22nm GATE LENGTH (nm) 10 LOW POWER HIGH PERFORMANCE YEAR

4 4 Metal-Oxide-Semiconductor Field-Effect Transistor: Desired characteristics: High ON current Low OFF current The Bulk-Si MOSFET Source Substrate GATE LENGTH, L g Gate Drain JUNCTION DEPTH, X j OXIDE THICKNESS, Tox M. Bohr, Intel Developer Forum, September 2004 Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode N-channel & P-channel MOSFETs operate in a complementary manner CMOS = Complementary MOS CURRENT V T GATE VOLTAGE

5 5 V T Roll-Off M. Okuno et al., 2005 IEDM p. 52 V T decreases with L g Effect is exacerbated by high values of V DS Qualitative explanation: The source & drain p-n junctions assist in depleting the Si underneath the gate. The smaller the L g, the greater the percentage of charge balanced by the S/D p-n junctions: V G n+ n+ x j Large L g : S D p depletion region Small L g : S D

6 6 Sub-Threshold Leakage log I D I ON, low VT I ON, high VT I OFF, low VT S 0 V DD I OFF, high VT V G Leakage current varies exponentially with V T S 60mV/dec at room temperature, due to thermal distribution of carriers within energy bands typically mv/dec for a bulk-si MOSFET

7 7 Parametric Yield smaller L gate High-performance processors TOO SLOW TOO LEAKY are speed-binned Faster chips = more $$$ (These parts have smaller L g ) Leakage is exponentially dependent on V T = f(l g ) Since leakage is now appreciable, parametric yield is being squeezed on both sides Tighter control of L g will be needed with scaling!

8 8 The Sub-Wavelength Gap

9 9 Achieving Sub-Wavelength Resolution 250nm 180nm 90nm and below Design OPC PSM Mask OPC Wafer courtesy M. Rieger (Synopsys, Inc.)

10 10 Geometrical Regularity for Improved Yield Configurable logic block layout A geometrically regular layout should be used to improve the fidelity of printed sub-wavelength features. All MOSFETs are oriented along the same direction Gate lines are placed at regular spacings L. Pillegi et al., 2003 DAC p. 782

11 11 Mask Cost Considerations Mask cost escalates with technology advancement! <λ (minimum half-pitch) It will eventually be more cost effective to use multiple lower-cost masks to define the most critical layer (gate)

12 12 Outline Introduction Spacer Lithography Process flow Application to gate patterning Device Simulation Study Summary and Future Work

13 13 Spacer Lithography Process 1. Deposit & pattern sacrificial layer 2. Deposit mask layer (e.g. Si 3 N 4 ) a-si hard mask (SiO 2 ) poly-si gate layer gate dielectric Si a-si hard mask (SiO 2 ) poly-si gate layer gate dielectric Si 3. Anisotropically etch mask layer spacers a-si hard mask (SiO 2 ) poly-si gate layer gate dielectric 4. Remove sacrificial material; Etch hardmask and poly-si L g,min gates gate dielectric Si Si Note that pitch is 2 that of patterned layer!

14 14 High-Density Feature Formation Photo-lithographically defined sacrificial structures 1st Spacers 2nd Spacers 3rd Spacers 2 n lines after n iterations of spacer lithography!

15 15 Spacer vs. Resist Lithography Spacer lithography yields superior CD uniformity Y.-K. Choi et al., IEEE Trans. Electron Devices, Vol. 49, p. 436, 2002

16 16 Gate Patterning using Spacer Lithography 1. Define fine-line features in a hard-mask layer using spacer lithography regular geometry (lines and spaces) L g < λ ; pitch P λ 2. Pattern fine-line features (to remove hard-mask where gate lines are not desired) minimum feature size > P alignment tolerance = P L g 3. Define large features in a resist layer using photolithography minimum feature size P alignment tolerance >L g

17 17 Spacer Gate Patterning Benefits Provides fine-line gate electrodes oriented in parallel and laid out on a regular grid Minimizes feature variations for improved yield Facilitates RET to achieve smallest possible feature sizes tight control of L g high parametric yield Note that the geometrically regular mask (Step 1) can be used for multiple chip designs, to save cost

18 18 Achieving Uniform Gate Length L g Gate formation by spacer lithography uniform L g L g Fin formation by conventional lithography non-uniform L g Y.-K. Choi et al., IEDM Technical Digest, pp , 2002

19 19 Outline Introduction Spacer Lithography Device Simulation Study Approach Initial results Summary and Future Work

20 20 Approach Use 3-D device simulations (Sentaurus Device) to investigate the benefits of spacer gate lithography nominal L g < 40nm Sources of variation include: L g variations line-edge roughness (LER) statistical dopant fluctuations (SDF)

21 21 EUV Resist LER Data from AMD Average CD = 37.9nm Standard Deviation = 1.7nm Filtered LWR (nm) Line Position (nm)

22 22 Impact of S/D Implant Anneal Conditions RTA: 1000 C 10s Spike: 1100 C 1s Flash: 1300 C 1ms S/D ext. implant: 3E14 As + cm 3keV Trend toward diffusion-less anneal increased junction roughness

23 23 Device Simulation: Methodology LER Generation Structure Generation Device Simulation W channel = 50nm L g = 37nm X j = 20.4nm T ox = 1.2nm N body = 2.2E18cm -3 Assume S/D junction follows LER profile. Sentaurus 3D Device simulation Collect statistical distributions of I ON and I OFF

24 24 Simulated MOSFET Structures Resist Lithography Spacer Lithography Plan View (gate electrode) Isometric View Plan View (gate electrode) Isometric View

25 25 Initial Results 0.05 I OFF (ua/um) Conventional Spacer Litho. Smaller spread in I OFF vs. I ON is seen for spacer gate lithography I ON (ma/um)

26 26 Introduction Outline Spacer Lithography Device Simulation Study Summary and Future Work

27 27 Summary Tighter control of L g will be needed with transistor scaling; however, this becomes more difficult as the sub-wavelength gap increases Spacer lithography provides for better CD control, and will eventually be a more cost-effective approach than conventional resist lithography for patterning gate electrodes LER effects on MOSFET performance can be mitigated by spacer gate lithography Future Work Assess the relative impacts of various sources of variability (line-width variations, LER, SDF)