A Multi-Gate CMOS Compact Model BSIMMG
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1 A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley
2 Acknowledgments Support Semiconductor Research Corporation IMPACT, UC Discovery and its industrial sponsors SOITEC Test Chip Fabrication Texas Instrument and ATDF TSMC Technical Discussions Wade Xiong (TI) 2
3 Difficult to suppress leakage in scaled transistors Source L Gate Oxide Path of I off Drain Need thinner oxide to suppress leakage in scaled CMOS Gate leakage is an issue! 3
4 Solution: Multi-gate MOSFETs Source L Gate Oxide Oxide Gate Drain Leakage is suppressed by multiple-gates Scale body thickness instead of oxide thickness 4
5 Multi-gate Examples FinFET UT2B T si =7nm T box =10nm L g = 5 nm X Huang et al., IEDM 1999 (UC Berkeley) F.-L. Yang et al., VLSI 2004 (TSMC) F. Andrieu et al. VLSI 2010 (LETI / ST / IBM / SOITEC) 5
6 65nm 45nm 32nm 22nm CMOS Solutions ENHANCED MOBILITY (Strained Si) HIGH -k / METAL GATE Multi-gate MG-FET Multi-gate FETs can extend CMOS scaling. BSIM-MG compact model has been developed. 6
7 Outline BSIM-CMG: Common Multi-gate MOSFET Model BSIM-IMG: Independent Multi-gate MOSFET Model Modeling of Real Device Effects Experimental Verification Summary 7
8 Common-Multi-Gate Modeling Common Multi-gate (BSIM-CMG): All gates tied together Surface-potential-based core I-V and C-V model Supports double-gate, triple-gate, quadruple-gate, cylindrical-gate; Bulk and SOI substrates Physics-based model verified against TCAD and measurements 8
9 Surface Potential Calculation (DG) Surface potential obtained by solving the 1D Poisson s equation V s V g n+ y x N n+ A V d 2 qψ qφb qvch qφb ψ qn i kt kt kt kt = e e e e 2 + x ε { Si Inversion Carriers Body Doping A Perturbation approach is used to handle finite body doping M. V. Dunga et al.,ted 2006 ψ { = ψ { inv + ψ { Net Surface Potential Inversion Carriers only Perturbation due to finite doping pert V g 9
10 Surface Potential Calculation Surface Potential (V) Symbols : TCAD Lines : Model Gate Voltage (V) Na = 1x10 15 Na = 1x10 18 Na = 3x10 18 Na = 5x10 18 Model matches 2D TCAD very well without fitting parameters in both fully-depleted and partially- depleted regimes. 10
11 I-V Model & Verification Drain current derived from drift diffusion Drain Current (A) Na = 3e18cm -3 1m Vg = 1.5V 500µ Vg = 1.2V Vg = 0.9V Drain Voltage (V) Drain Current (A) 1m 500µ Na = 3e18 cm -3 Vd = 0.1 Vd = 0.2 Vd = 0.4 Vd = Gate Voltage (V) M. V. Dunga, UCB Ph.D. Thesis 11
12 Drain Current in Volume Inversion Drain Current (A) 10µ Vds = 0.2V 10µ 10n 10p Na = 1e15 cm -3 Tsi = 5nm Tsi = 10nm Tsi = 20nm 10f Gate Voltage (V) Lines: Model Symbols: TCAD In volume inversion I d T Si in sub-threshold. M. V. Dunga, VLSI
13 Normalized Capacitance Na = 3e18cm -3 Vds = 1.5V C-V Model Verification Symbols : TCAD Lines : Model Cgg Csg Cdg Gate Voltage (V) Na = 3e18 Cdg Vg = 1.5V Cgd C-V model agrees well with TCAD without any fitting parameters. The transcapacitances exhibit the correct symmetry behaviors. Normalized Capacitance Cgg Model Symmetry Symbols : TCAD Lines : Model Cgs Drain Voltage (V) Csg 13
14 Independent Multi-Gate Modeling Independent Multi-gate (BSIM-IMG): Separate Front- and Back-Gates Asymmetric gate stacks: workfunction, T ox, BOX P+ back-gate p-sub Target device: BG-ETSOI or UTBB Physical surface-potential-based core I-V and C-V model agrees with TCAD without fitting parameters. 14
15 Surface Potential Analytical Solution for Ψs is known T OX1 V FG Φ M1 Y. Taur, TED 2001 H. Lu et al., TED 2006 S D T OX2 Newton iteration needed for Ψ s calculation V BG Φ M2 Approximation for front-, back-surface potential and charge developed Better computational efficiency D. Lu, UCB Master s Report 15
16 Surface Potential Verification Surface Potential (V) Vch = 0.0V Vch = 0.3V Vch = 0.6V Front Gate Voltage (V) Symbols: Exact Poisson Lines: Model Charge Density (C/m 2 ) Surface Potential (V) Tox1=Tox2=1.2nm Tsi=10nm Vbg=0 Tsi = 5 nm Tsi = 10 nm Tsi = 15 nm Tsi = 20 nm Front Gate Voltage (V) Symbols: TCAD Lines: Model Analytical Q S, Ψ SF agrees with Exact Poisson Solution & TCAD without fitting parameters. Scalability of the model is demonstrated. 16
17 Core I-V and C-V Model Physical I-V and C-V model agrees well with TCAD Transcapacitances exhibit correct symmetry Drain Current (A) 1E-4 1E-6 1E-8 1E-10 1E-12 Symbols: TCAD Lines: Model Vds = 50mV Tox2 = 40nm Tox2 = 20nm Tox2 = 10nm Tox2 = 5nm Tox2 = 2.5nm Front Gate Voltage (V) Capacitance (ff) D. Lu et al., IEDM 2007 Cfg,d Cfg,s Cfg,fg Vfg = 0.5V Symbols: TCAD Lines: Model Drain Voltage (V) Tox1=1.2nm Tsi=15nm Tox2=40nm Vbg=0 Model Symmetry 17
18 Real-Device Effects Modeled Quantum effects (charge centroid model) Short Channel Effects -- V th roll-off, Sub-threshold swing degradation, DIBL, CLM Mobility Degradation Velocity Saturation GIDL, GISL and Junction Leakage Gate Tunneling Current Temperature effects Parasitic Capacitance Series Resistance Etc. 18
19 Short Channel Effects Symbols: Measurements Lines: Model Threshold Voltage (V) Z. Liu et al., TED 1993 V d s = -5 0 m V V d s = -1.0 V G a te L e n g th ( µ m ) V th Definition: I th = 300nA * W / L SS (mv/dec) SS (mv/dec) SS: Subthreshold Swing Vds = -50mV Gate Length (µm) Vds = -1.0V Gate Length (µm) 19
20 Scale Length for Various Modes Double-gate Triple-gate - K. Suzuki et al., TED 1993 Cylindrical-gate Independent-gate Leakage path at front surface Leakage path in the center 20
21 Temperature Effects Temperature dependence are well-modeled Mobility temperature dependence: U0(T), UA(T) Saturation Velocity temperature dependence: VSAT(T) Subthreshold Swing = nkt/q GIDL Leakage: BGIDL(T) A few others Drain Current (µa) C --> 200C in steps of 5 0C Increasing T L G =60nm 20 fins G a te V o lta g e (V ) 1E-3 1E-6 1E-9 1E-12 Symbols: SOI FinFET data Lines: Model -50C --> 200C in steps of 50C Increasing T L G =60nm 20 fins Gate Voltage (V) Vds=1.0 21
22 Length Dependent γ Model for Independent-gate Gamma definition: Capacitance network analysis: C ox1 C si C ox2 Front Gate Back Gate C d1 (L eff ) C d2 (L eff ) Source / Drain γ degradation for short channel: Gamma (γ) Threshold Voltage (V) V DS = 50mV Symbols: TCAD Lines: Model L FG = 45 nm L FG = 22 nm L FG = 13nm Back Gate Bias (V) Vds = 1V TCAD Model Gate Length (µm) Tsi=8nm Tbox=4nm 22
23 SOI FinFET Global Parameter Extraction Drain Current (ma) Vds = -50mV Decreasing L Gate Voltage (V) Drain Current (ma) Vds = 50mV Decreasing L Gate Voltage (V) Drain Current (ma) Vds = -1.0 V Decreasing L Gate Voltage (V) FinFET with L G = 1µm, 235nm, 95nm, 85nm, 75nm H fin =60, T fin =22, 20 lightly-doped fins D. Lu et al., SISPAD Drain Current (ma) Vds = 1.0 V Decreasing L Gate Voltage (V)
24 Analog metrics (SOI FinFETs) Analog metrics (g m /I d and g ds ) for the long channel are also captured well. g m Efficiency (g m /I d ) Output Conductance g m Efficiency, g m /I d (V -1 ) Lg = 1µm Vd = 1 V Vd = 50mV Gate Voltage (V) Dunga et al., VLSI 2007 Output Conductance (S) 1m 1µ 1n L g = 1 µm V g = V 1p D rain V o ltage (V ) 24
25 Short Channel Bulk FinFETs Model is used to describe bulk FinFET technology also. Substrate Current: Impact Ionization Drain Current (A) 50µ 25µ Id-Vg Lg = 50nm Vd = 50mV Vd = 1.2V 0 1p Gate Voltage (V) 1m 1µ 1n Drain Current (µa) 50 Lg = 50nm Vg = V 25 Dunga et al., VLSI 2007 Id-Vd Drain Voltage (V) 25 Bulk Current (A) 100p 10p Ib-Vg Lg = 50nm Vd = 1.2V 1p G ate Voltage (V)
26 Validation of BSIM-IMG Model Global parameter extraction 22nm ETSOI technology (IBM) I ds for NMOS and PMOS L g = 24.5nm 66nm Model extracted using ICCAP Parasitic capacitances calibrated to mixed-mode TCAD ETSOI K. Cheng et al. IEDM 2009 (IBM / ST) 26
27 Gummel Symmetry Test I ds continuity at V ds =0 is verified through the Gummel symmetry test. Both BSIM-CMG and BSIM-IMG passes this test di d / dv x (ms) Vfg = 0.0 Vfg = 0.2 Vfg = 0.4 Vfg = 0.6 Vfg = 0.8 Vfg = Gummel Test Voltage Vx (V) Results shown here are 1 st & 3 rd order derivatives of I ds for BSIM-IMG d 3 I d / dv x 3 (A / V 3 ) Vfg = 0.0 Vfg = 0.2 Vfg = 0.4 Vfg = 0.6 Vfg = 0.8 Vfg = Gummel Test Voltage Vx (V) 27
28 Summary Core I-V and C-V models for common and independent multi-gate FETs are developed and verified with TCAD without using fitting parameters Volume inversion and the effect of finite body doping are captured. BSIM-like real device effects are implemented. BSIM-CMG is calibrated to an SOI FinFET technology and a bulk FinFET technology. Short channel effects, temperature dependence, GIDL leakage, substrate current and analog metrics agree well with data. BSIM-IMG is also calibrated to an ETSOI technology with good agreements. 28
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