SOI/SOTB Compact Models

Transcription

1 MOS-AK 2017 An Overview of the HiSIM SOI/SOTB Compact Models Marek Mierzwinski*, Dondee Navarro**, and Mitiko Miura-Mattausch** *Keysight Technologies **Hiroshima University

2 Agenda Introduction Model overview Model theory Model applications CMC standard implementation 2

3 Silicon On Insulator technology SOI technology provides key advantages for high performance devices Reduced junction capacitances Improved subthreshold voltage swing Improved isolation Similar performance gains but less complex than FinFET Disadvantages Substrate cost Some process issues (stress) 3

4 Silicon On Insulator (SOI) MOSFET Bulk-MOSFET SOI-MOSFET Buried oxide 4

5 HiSIM HIR O S H I M A - U N I V E R S I T Y S TA R C I G F E T M O D E L HiSIM2: Bulk MOSFET HiSIM-Varactor HiSIM_HV: HV-MOSFET, extension of HiSIM2 HiSIM-IGBT: HiSIM2 + Bipolar + Diode HiSIM-SOI/SOTB HiSIM-TFT HiSIM-DG 5

6 HiSIM-SOI Compact Model Key Features Considers all possible induced charges in the Poisson equation Derives accurate analytical solution as initial values Solves the Poisson equation iteratively Self heating accounted for History effect modeled Many other phenomenon Standardized by CMC on 2012 July 6

7 Applicability of HiSIM-SOI compact model Partially Depleted (PD) as well as ultra-thin-body Fully Depleted (FD) SOI Voltage dependent Dynamic Depleted (DD) SOI Low voltage circuit application RF circuit simulation with noise prediction 7

8 HiSIM-SOI Model Implementation Steps Device physical characteristics such as thickness of the SOI layer, thickness of the buried oxide layer, and impurity concentration in the bulk must be able to be extracted. 3 surface potentials have to be accurately calculated Charges must be computed such that charge conservation is not violated Short channel effects must be accounted for 8

9 Extracted physical values Certain model parameters must be determined Typically these values would be extracted via measurement under proper conditions to make certain values more sensitive 9

10 Model parameter extractions from V BS BOX accumulation inversion BOX inversion accumulation 10

11 Three surface potentials induced in SOI-MOSFET Conventional bulk MOSFETs need only solve for the surface potential at the front oxide layer (FOX) The SOI MOSFET must also solve for the potential at each side of the buried oxide (BOX) 11

12 Surface potential-based modeling Provides self-consistent current and capacitance characteristics 12

13 Potential and Charge Basic Equations Derived from Poisson Equation and Gauss s Law 13

14 Implicit Relations 14

15 Newton-Raphson technique Developed circa 1700! Make guess F φ n Test answer φ i+1 = φ i F(φ i) F (φ i ) Compute new guess using tangent. Close enough to 0? Converged φ i+1 φ i φ n 15

16 Equation to solve φ i+1 -φ i = J 1 f 16

17 Verilog-A Implementation 17

18 Iterations to calculate surface potential Newton-Raphson s algorithm converges very quickly. Number of iterations steps needed to calculated the surface potentials at source and drain as function of V gs shown. 18

19 SOI MOSFET operation mode The device geometry, physical parameters, and operating temperature can all affect the operation mode that the device is in 19

20 Many Possible Structure Types For SOI T SOI T BOX Condition Device PD Device DD Device DD Device FD resulting in different potential distributions Lines = 2D-TCAD Circles = HiSIM causing different bias dependencies 20

21 Smooth Transition among Conditions Gate bias varied T SOI T BOX Condition Device PD Device DD Device DD Device FD 21

22 Floating-Body Effect in HiSIM-SOI bulk-mosfet SOI-MOSFET impact ionization hole storage Holes generated by Impact Ionization accumulate in SOI layer 22

23 potential [V] Influence of Stored Charge Stored holes cause potential redistribution TSOI TBOX w/o impact ionization 1.0 with impact ionization 1.5 2D-device simulation depth [mm] 23

24 I d [10-5 A] Floating-Body Effect in HiSIM-SOI Accumulated holes affect bias potential and drain current This manifests itself as an increase in drain current, or kink Also causes history effect since prior biases have an influence SOI-MOSFET bulk-mosfet Kink effect observed in SOI-MOSFET I-V V ds [V]

25 Modeling of Stored Charge: Q h Q h is included in the Poisson equation. The floating-body effect is automatically included. Q h =f(i sub : measured with BT device) 25

26 HiSIM-SOI Results symbol: 2D-Sim. line: HiSIM-SOI SOI bulk f s.bulk f b.soi f s.soi FOX BOX f b.soi reduction change from FD to PD 26

27 History Effect T d : Time constant of Q h storage Transient Characteristics of the Floating-Body Effect Implemented into HiSIM-SOI in similar way as the NQS effect T d T d 1/I sub 27

28 History Effect Implementation Calculate Contribute 28

29 Silicon On Thin Buried oxide MOSFET The potential distribution must be considered from the surface to the bottom of the substrate explicitly All 4 potential values must be solved simultaneously FOX BOX 29

30 Model Concept SOTB Similar Model Framework as HiSIM-SOI Complete Surface-Potential-Based Model Physically Consistent Modeling Approach Scalability with Device-Structure Changes T ox T BOX N SOI T SOI N sub More than HiSIM-SOI Applicable for Thin TSOI with high impurity concentration of Nsub Extendable for DG-MOSFET (inclusion of inversion condition at the back side of TSOI) 30

31 Various potential distributions and results Back gate control of the front gate charge Ves=+0.6V Ves=0 Ves=-0.6V 31

32 Phenomena Considered in HiSIM-SOI floating-body effect history effect valence-band tunneling noise characteristics self-heating body contact NQS effect impact ionization gate tunneling currents GIDL currents non-uniform doping effects channel length modulation velocity saturation, including overshoot short-channel effects width scaling effects bulk charge effect universal mobility field-dependent mobility finite inversion layer thickness parasitic bipolar diode junction currents / capacitances 32

33 Summary Silicon-on-insulator (SOI)-MOSFETs provide next generation of mainstream integrated circuits with a technology that reduces junction capacitances and improves subthreshold swing, critical for a high-speed device operation. The HiSIM SOI and SOTB device models, developed at Hiroshima University are Compact Model Coalition standards give device modeling engineers the capability to model complex device behavior in all SOI structures and bias conditions a physical model good convergence capabilities Verilog-A source code allows easy access to all the implementation details self-documented code reference values under any conditions 33