MOSFET SCALING ECE 663

Transcription

1 MOSFET SCALING

2 Scaling of switches

3 Moore s Law economics Moore s Law - #DRAM Bits per chip doubles every 18 months ~5% bigger chips/wafers ~5% design improvements ~50 % Lithography ability to print smaller features Exponentials!! (461 B tonnes)

4 Exponential growth: Natural law of economics vs self-fulfilling prophecy? Solid State Lighting Kryder s Law for energy storage Malthus Law

5 More natural curves Hubbert Curve

6 When the chip s down With feature size shrink of (typical generation) x #transistors/unit area X Higher speed (f ) Fixed cost per wafer Smaller (x), Faster (x), cheaper strong economic driving force 30% improvement in cost per function per year

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8 CMOS Device Scaling Parameters Variables Scaling Factor Dimensions W,L,x ox,x 1/ Potentials V ds,v gs 1/k Doping Concentration N /k Electric Field E /k Current I ds /k Gate Delay T k/ =dimensional scaling factor k=supply voltage scaling factor

9 Constant Field Scaling: keep E constant in channel k= Constant Voltage Scaling: keep supply voltage constant k=1(used for submicron scaling) Parameters Const Field Const Volt Dimensions 1/ 1/ Potentials 1/ 1 Doping Concentration Electric Field 1 Current 1/ Gate Delay 1/ 1/

10 Short Channel Effects punch through

11 Threshold Voltage Roll-off/DIBL

12 Scaling Rule of Thumb L min minimum gate length for long channel behavior Computer simulations, experiments: L r x W W 1 3 min 0. 4 o s D X o gate oxide thickness (Å) L min,w s,w D,r (S/D unction depth) in microns S/D unctions, depletion depths (doping), oxide thickness must scale with minimum gate length x o r W s L r W D

13 Short Channel MOSFET Geometry How much channel charge does the gate control?

14 Threshold Voltage Shift Threshold Voltage V T V T Long Channel transistor: s V V T i B ( short) V Q C T B i ( long) ( Q BS Q C i BL ) Q BL qn A ZLW ZL qn A W Q BL qn A ZLW ZL qn A W

15 Charge control region Short Channel transistor: charge in trapezoidal region Q BS qn A L L' ZW ZL qn A W L L' L V T ( QBS QBL ) qn AW C C i i 1 L L' L

16 A little geometry W r W r D W D W r W r W D r r ( r r W r ) W W r W W

17 A little algebra r W r r W r r r W r r W W r W r r r W W r r ) (

18 Threshold shift ' ' r W L r L L L L L L L L 1 1 ' 1 i A i A T r W C L r W qn L L L C W qn V Shallow unctions, low doping

19 But this increases the contact resistances Thus, raised Source-Drain

20 Charge sharing creates DIBL V V T D

21 Charge sharing creates DIBL V V T D 3D Simulation of Nanowire FETs using Quantum Models Viay Sai Patnaik, Ankit Gheedia and M. Jagadesh Kumar The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Huaz Khas, New Delhi , India ( viaysai.patnaik@gmail.com)

22 Narrow Gate Width Effect Volume of depletion region gets bigger due to end caps Takes more gate voltage to invert the channel W i W BL BN T T T i B B i s T C Q Q wide long V narrow V V C Q V V ) ( ) ( ) ( Z

23 Narrow Gate Effect Q BLW qn A ZLW ZL V T Q ( Q endcaps BN Q C i qn BLW ) A Q W 4 ZL C i endcaps L qn A W ZLC i L V T qn A W C Z i Threshold voltage gets bigger with decreasing Z

24 Punch-Through x o r W s L r W D +V D n-p-n BJT x o r W s L e - r W D ++V D S&D depletions touch punch through

25 Punch Through Electrons can flow from source to drain (no more back to back unctions) (n-channel enhancement mode) I D V D Drain current no longer controlled by gate Transistors won t turn off General Cure high dose implant in sub-gate region to make narrower depletion widths Higher substrate doping increases parasitic capacitances

26 Oxide Charging Carriers accelerated toward Drain/depletion can have sufficient energy to escape into the oxide Neutral traps (defects) in the oxide trap charge Leads to long term shift in characteristics in long-channel Short-channel more of the gate oxide is near the drain big effect big V T and g m effects - device failure N gradient

27 Lightly Doped Drain Structure - LDD Reduced N gradient smaller electric field near drain fewer hot electrons into oxide n - to avoid large fields and hot electrons, n + to get Ohmic contacts (still need to avoid punch-through) n - n+

28 Lightly Doped LDD Drain from Structure Fuitsu - LDD Reduced N gradient smaller electric field near drain fewer hot electrons into oxide n - to avoid large fields and hot electrons, n + to get Ohmic contacts n - n+

29 Vanilla CMOS -level metal 16-masks

30 LDD Structure

31 Halo Implants Local heavy substrate doping for punch-through control leaving channel lightly doped for threshold control

32 Velocity Saturation E

33 Velocity Saturation Effect supressed drain current g msat I V D G sat ZC i sat const. Measurement Calculation w/ Calculation w/o Velocity Saturation Velocity Saturation

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35 Strained Si

36 Strained Si

37 Ge Mosfets

38 CMOS Inverter Latch-up p-well technology

39 SOI No body effect parameter (depletion width fixed) Junction to substance parasitic capacitance small (faster switch!) No latch-up between NMOS and PMOS (no substrate)

40 Band diagram in SOIs

41 SOI S = (MkT/q)ln(10), M = 1+ C p /C ox

42 Kink effect in PDSOI Saraya et al At high drain bias, holes accelerated at reverse biased drain-body unction through impact ionization. Floating body gets charged up, and suddenly reduces gate threshold voltage

43 Gate Depletion Solution: Metal Gates

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46 Gordon Moore Intel as ISCC 003 Multi-Gates

47 Gordon Moore Intel as ISCC 003

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