Keywords MOSFET, FinFET, Silicon, Germanium, InGaAs, Monte Carlo, Drift Diffusion.

Transcription

1 Predicting Future Technology Performance Asen Asenov and Craig Alexander Gold Standard Simulations The Rankine Building, Oakfield Avenue Glasgow G12 8LT +44 () Craig Riddet and Ewan Towie Device Modelling Group University of Glasgow, Oakfield Avenue Glasgow G12 8LT +44 () ABSTRACT In this paper we highlight the important role of full-scale 3D Ensemble Monte Carlo (E) transport simulations in the performance analysis of contemporary and future decananometer MOSFETs. Considering both electron and hole transport in alternative device structures and materials we demonstrate that conventional drift diffusion () simulations using standard mobility models fail to capture the non-equilibrium transport effects present in these devices, limiting their effectiveness in terms of performing predictive simulation of Si based FinFETs. We clearly demonstrate the capabilities and the power of E in evaluating the scaling potential and performance of FinFETs and quantum well transistors employing high mobility materials and the impact that additional scattering sources has on their performance. Keywords MOSFET, FinFET, Silicon, Germanium, InGaAs, Monte Carlo, Drift Diffusion. 1. INTRODUCTION Low performance, intolerable levels of random dopant induced statistical variability, and corresponding increased leakage and SRAM yield and reliability problems has shifted the attention away from bulk MOSFETs that have been the workhorse of the semiconductor industry for decades. Fully depleted SOI and multi-gate MOSFETs, both with superior electrostatic integrity and tolerance to low channel doping, are the competing successors [11]. In particular, Intel s adoption of FinFET technology at the 2 CMOS technology node [12] has invigorated the interest in their optimization and scaling. In addition to this, the use of high-mobility channel materials such as III-Vs and germanium (Ge) as an alternative to conventional silicon (Si) is a promising technology option that has gained recognition in the 211 edition of the International Roadmap for Semiconductors (ITRS) [13]. In this regard, TCAD based device simulation, analysis and optimization of such new transistor architectures plays an important role. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC 13, May 29 - June 7 213, Austin, TX, USA. Copyright 213 ACM /13/5...$15. However, the drift diffusion () approach, commonly used in commercial TCAD tools, can not deliver predictive simulations of these advanced devices with decananometer channel lengths due to non-equilibrium, quasiballistic transport [25]. This is further exacerbated by the use of strain and channel orientation to enhance transport and drive current. Fully quantum simulations, such as the non-equilibrium Green s functions (NEGF), are more suited to simulating future devices in terms of properly capturing the complicated transport, but are computationally demanding and therefore there use has been limited to low dimensional transport or to the simulation of small structures such as nanowire transistors [8]. This limits their applicability to practical transistors design, especially when full 3D transport is required as is the case for the FinFET structure. In contrast, ensemble Monte Carlo (E) device simulations are capable of resolving non-equilibrium transport effects in addition to the impact of orientation and strain on the bandstructure, transport and device performance [14], [23]. This provides the means to reliably investigate device behaviour early in the design stage making E more predictive than while less computationally intensive than NEGF. The E approach can be extended by the use of complicated bandstructure models, quantum corrections, degenerate statistics and a full suite of scattering mechanisms allowing scaled devices using alternative channel materials and architectures to be accurately assessed. In this paper we describe the full 3D E simulation module that is part of the GSS 3D device simulator GARAND [2] which is capable of accurately characterizing the transport in advanced device structures employing conventional and high mobility channel materials. The models at the heart of this approach are described in Section 2. The capabilities are than demonstrated in Section 3 by the simulation of FinFET and implant free quantum well (IFQW) transistors in comparison to simulation to highlight the predictive power of E. 2. SIMULATOR DESCRIPTION The 3D E module of GARAND is self-consistently coupled to the solution of Poisson s equation coupling the carrier transport to the field and is essential to accurately describe transport and transistor performance, particularly at high fields [19]. 2.1 Bandstructure Model For electron transport a multi-band analytical ellipsoidal, nonparabolic description is employed, while for hole transport a full 6-band k p approach is used that includes the effects of spin orbit coupling [6], [1]. The energy surfaces for Si and Ge calculated using this approach are shown in Figure 1. Both methods allow

2 the impact of crystallographic orientation and applied strain to be easily accounted for. Carrier statistics can be evaluated using either a non-degenerate Maxwell-Boltzmann or a fully degenerate Fermi-Dirac model, the latter of which includes the Pauli-Exclusion principle and is vital for the simulation of III-V materials with low density of states. Figure 1 Energy surfaces of the heavy hole valence band at 5meV for Si (left) and Ge (right). Energy contours on the (1) surface are shown out to 1eV. 2.2 Quantum Corrections The continued scaling of CMOS devices makes the inclusion of quantum effects absolutely essential for accurate predictive simulations [25]. Numerous approaches have been proposed to include quantum effects in E, ranging from a crude modification of the workfunction and oxide capacitance [5], to the effective potential method [7] and up to self-consistent coupling to the solution of the Schrodinger equation. All of these approaches have strengths and weaknesses in terms of accuracy, stability and efficiency and their impact on the other models used within the simulator. In the E module of GARAND, an approach based on the Density Gradient formalism [1] is used that captures the essential quantum mechanical effects while having little effect on the computational efficiency of the simulator as a whole [19]. Here, the total driving force applied to the particles is based on the sum of classical potential from the solution of Poisson s equation and a quantum correction term [4]: ( ) F q = ψ cl +ψ qc The quantum correction term is taken from an initial simulation as the difference between the classical and quantum potentials and is stored at the beginning of the E simulation. The Density Gradient solver is calibrated to 1D Poisson- Schrodinger simulations in order to match the carrier distribution normal to the gate. 2.3 Scattering Mechanisms A full range of scattering mechanisms is included within the E module for both electron and hole transport. Acoustic phonon scattering (IAP) is modeled using an inelastic approach [14], [2] that includes a full dispersion [17]. For n- channel simulations this is an intravalley process, while for hole transport interband transitions are included, which is necessary due to the degenerate heavy and light hole valence bands. Inelastic optical phonon scattering is modeled without dispersion [14], with intra- and inter-valley transitions included. Both polar (IPOP) and non-polar (INPOP) modes are included and are used where applicable. The phonon scattering parameters are carefully calibrated to match measured low field mobility and velocity-field characteristics in undoped samples. Ionized impurity scattering (II) is treated using Ridley s Third Body Exclusion [21] with an empirical correction to match experimental data applied for each material and carrier type. Due to the use of quantum corrections, the use of a specular/diffusive interface roughness scattering (IR) is not appropriate [16], [22]. Therefore we follow Ando s approach [18] for this mechanism, where a conventional scattering rate is used. Alloy scattering (AL) is included using the approach discussed in [9], with the alloy potential calibrated to match experimentally observed mobilities. This is applied to alloy materials such as InGaAs, InAlAs and SiGe. When Fermi-Dirac statistics is used, a suitable modification is made to the rates of the inelastic processes only [24]. 3. RESULTS AND DISCUSSION 3.1 Si FinFET The simulated Si FinFET is a gate length SOI FinFET, illustrated in Figure 2. The fin width and fin height are 1 nm and 25 nm respectively. The equivalent oxide thickness of the highk/metal gate stack is.8 nm. The top of the conducting fin is insulated from the gate by a thicker layer of silicon nitride. As these devices were designed for SRAM applications the simulations are carried at the worst temperature corner of 358K. The same structure is employed for n- and p-channel simulations, and IAP, INPOP and II scattering is included, with IR scattering neglected to give an indication of the peak achievable performance assuming an ideal interface. A substrate orientation of (1) is used, with a channel of 1 for the n-channel and 11 for the p-channel transistors, giving sidewall surfaces of (1) and (11) respectively. Figure 2 Device structure of the FinFET simulated in this study Comparison with simulation yields a greater on-current as a result of nonequilibrium transport leading to a greater injection velocity compared to the corresponding velocity that cannot exceed the default silicon saturation velocity. Figure 3 shows the average carrier velocity profiles, from source to drain, from both E and simulation at V DS =.9V for the n-channel Si FinFET. At the virtual source (marked by the dashed line in the figure) the difference in velocity between E simulations and the simulations with default mobility is significant. While the E injection velocity exceeds cms -1, the velocity is below cms -1. By increasing the value of the saturation velocity in the field dependent mobility model, it should be possible to better reproduce the magnitude of the injection velocity within simulations and hence to match the E on-current.

3 Using the E simulated transfer characteristics as a target the mobility model was calibrated. First the low field mobility and its vertical field dependence was adjusted to reproduce the low field E simulated - characteristics. Then the saturation velocity was adjusted to match the E simulated oncurrent at high drain bias. The procedure was iterated until selfconsistent values of the low field mobility and the saturation velocity were obtained. 2.5 Velocity [ 1 7 cm/s] Calibrated Default X Position [nm] Figure 3 Electron velocity from source to drain from E (solid lines) and (dashed lines) in the n-channel FinFET at V D = =.9V. results are shown using default mobility model parameters and after calibration to E results. Figure 4 shows the calibrated transfer characteristics compared with the target from E simulation. Excellent agreement is achieved for the drain current at both low and high drain bias. simulation results using default mobility parameters are also shown for comparison. The sub-threshold slope determined by the device electrostatics is largely unaffected by the calibration maintaining a good agreement between and E. This highlights the benefits of using E as a predictive simulation tool over, which cannot reliably estimate the oncurrent performance of a given device without calibration of mobility models to either measured transistors or to E simulations. [ma/μm] L G = (calibrated) (default) Figure 4 - characteristics for gate length n-channel FinFET from and E simulation. results are shown using default mobility model parameters and after calibration. A similar procedure was followed for the p-channel FinFET, at the same operating conditions. Since no strain is used in this simulations, as can be seen from Figure 5 the underestimation of the carrier velocity at the source is less severe when using the default mobility model parameters at high drain bias compared to the n-channel case. However, as shown in Figure 6 careful calibration is required for properly predictive simulations Velocity [ 1 7 cm/s] (1)/(11)/<11> Calibrated Default X Position [nm] Figure 5 Hole velocity from source to drain from E (solid lines) and (dashed lines) simulation in the p-channel FinFET at V D = =.9V. results are shown using default mobility model parameters and after calibration to E results. [ma/μm] (1)/(11)/<11> (default) (calibrated) Figure 6 - characteristics for gate length p-channel FinFET from and E simulation. results are shown using default mobility model parameters and after calibration Impact of Crystallographic Orientation A further complication arises when the impact of surface and channel orientation is taken into account for the p-channel transistor. In Figure 7 simulations have been calibrated to match E simulations with two different surface/channel orientations at low drain bias using only the low field mobility. As the E simulations demonstrate, at high drain bias the simulations firstly underestimate the performance and secondly fail to capture the change in the preferential orientation as carriers access different areas of the bandstructure. These effects are not captured in the simulations due to the absence of nonequilibrium effects in this simulation model. This is a further limitation of as a method for predicting device performance in future technology options, and further demonstrates the benefits of using E as these effects are captured via the calculated bandstructure

4 [ma/μm] (μ,<-1> ) (11)/(11)/<-1> (μ,<11> ) (1)/(11)/<11> Figure 7 - characteristics for the p-channel FinFET showing two different substrate/sidewall/channel orientations. In both cases the low field mobility is calibrated to match the low drain bias characteristic from E. 3.2 IFQW The structure of the 1 gate length Implant Free Quantum Well (IFQW) transistors is illustrated in Figure 8 targeting the 1nm technology generation and has been designed following the ITRS guidelines [13]. For the n-channel case, the channel is In.53 Ga.47 As with an In.52 Al.48 As substrate, while the p-channel device employs Ge for the channel with a Si substrate. The transistor utilizes a 3.7 thick QW channel with epitaxial insitu doped raised source and drain regions. The source and drain regions are doped to cm -3, the channel doping is cm -3 and the substrate cm -3. A common gate oxide of Al 2 O 3 is used with an EOT=.51nm, and the lateral spacers are Si 3 N 4 with a width ranging from 1 to. The IFQW transistor also includes the diffusion of dopants from the source/drain regions into the channel layer [15], which is referred to as sub-diffusion. For the n-channel simulations, IAP, INPOP, IPOP and II scattering are included, while for the p-channel simulation the IAP, INPOP and II mechanisms are employed. (a) The impact of the spacer scaling on the nifqw transistor is demonstrated in Figure 9, with an overall increase of 35% in the drive current as the spacer is scaled from to 1nm. It is also clear that the difference between the and 1nm cases is small compared to the other incremental changes, though SS and DIBL increase leading to the conclusion that the spacer is optimal nm 3nm 1nm Figure 9 Transfer characteristics for I OFF =.1μA/μm at V D =1V against lateral spacer width for the nifqw device. For the p-channel transistor (Figure 1), the impact of the spacer scaling is greater, with an increase of 118% as the spacer is scaled from down to 1nm. The stronger impact of degeneracy and the differences in confinement in the III-V material are the causes of this difference nm 3nm 1nm Sub-Diffusion X Figure 1 Transfer characteristics for I OFF =.1μA/μm at V D =1V against lateral spacer width for the pifqw device. (b) Ge Z Ge In both cases the use of sub diffusion doping reduces the impact of the barrier between the contact regions and the channel by introducing doping into the channel layer and under the lateral spacer, improving the overall on current as well as reducing the impact of variations in the lateral spacer thickness on device performance. Sub-Diffusion Ge Si Figure 8 Structure of the IFQW device showing the (a) n- channel InGaAs and (b) p-channel Ge transistors Spacer Scaling The impact of the width of the lateral Si 3 N 4 spacer between the raised source/drain regions and the gate is known to be a critical factor in defining device performance [3], and here E simulations are used to demonstrate its impact on the on-current in both the n- and p-channel transistors. In both cases I OFF =.1µA/µm and V D = 1V Comparison with The transfer characteristics for the n- and p-channel IFQW devices are shown in Figure 11 and Figure 12 respectively for a device with a lateral spacer. In both cases the simulations use default mobility models, and hence significantly underestimate the drive current. Indeed, the current for the high drain bias simulations is less than half that predicted by the E simulations.

5 ( -V T ) Figure 11 Comparison of the transfer characteristics at V D =.5V and V D =1V between E and for the nifqw device ( -V T ) Figure 12 Comparison of the transfer characteristics at V D =.5V and V D =1V between E and for the pifqw device Impact of Surface Roughness on IFQW Performance Further simulations of the IFQW devices with IR scattering applied to the interface between the Al 2 O 3 gate dielectric and the channel have been carried out for devices with a range of lateral spacer widths. Figure 13 shows the - characteristics for the n- and pifqw transistors with and without this additional scattering mechanism. While the impact is greater in the nifqw device, in both cases the impact increases as the spacer width reduces, though the scaling of the spacer width still results in an improvement in device performance. (a) [µa/µm] V T.8 (b) 175 [µa/µm] V T Figure 13 - characteristics of (a) the nifqw and (b) the pifqw transistor without (solid symbols) and with (hollow symbols) IR scattering at V D =1V. In the n-channel case, the high electron velocity dictates the drive current and the additional scattering from IR reduces the channel velocity, and in turn reduces the drive current. For the pifqw device the larger inversion density is responsible for the drive current, and again the additional scattering influences this, in particular at the source end of the channel leading to the reduction in the drive current when IR scattering is introduced. 3.3 III-V FinFET To compare the two device concepts introduced in the previous sections, and to consider the impact of using a high mobility channel material in place of Si, a 1 gate length FinFET shown in Figure 14 using In.53 Ga.47 As as a channel material has been simulated using the 3D E module. These simulations employ scattering from IAP, INPOP, IPOP and II. H fin SOURCE W fin t spc GATE tox DRAIN L G SUBSTRATE Si 3 N 4 Al 2 O 3 Gate W fin Fin H fin Substrate Figure 14 Device structure of the III-V n-type FinFET device showing a perspective and mid-gate cross-section. 125 nifqw nfinfet Figure 15 - characteristics of the III-V nmosfets for I OFF =.1μA/μm. The - characteristics for the two devices are presented in Figure 15 and show the relationship of drive current per unit width between device architectures. The SS is vastly improved from 88mV/decade in the IFQW to 68mV/dec in the FinFET, and DIBL improves from 85mV/V to 29mV/V. Due to the low density of states of InGaAs, the larger electron density in the FinFET channel increases the impact of degeneracy and forces the electrons into the heavier effective mass L-valleys impacting on the channel velocity. Coupled with increased access resistance from the raised source/drain regions results in a reduced drive current per unit width. Though the increased effective gate area of this device leads to an increase in the drive current (the effective channel width of the IFQW device is 1, while for the FinFET it is 6nm). With further improvements to the source/drain design, combined with the better electrostatics suggests that the FinFET remains a promising candidate for this generation of device.

6 4. CONCLUSIONS In this paper we have clearly demonstrated that accurate 3D E simulations are needed in order to reliably predict the performance of contemporary decananometer scale MOSFETs. simulations fail to accurately predict device performance using default mobility models, but via careful calibration to E transport simulations can reproduce the predicted performance. However, this calibration will not necessarily hold for a given device using, for instance, an alternative surface/channel orientation. We have also shown the usefulness of 3D E in the analysis of alternative architectures and channel materials, where non-equilibrium effects can be stronger due to the lower carrier mass. As these effects are well represented by the E simulation model, the impact of scaling and scattering on performance can be fully evaluated, giving a full indication of performance potential of a given device. 5. REFERENCES [1] Ancona, M. G., and Iafrate, G. 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