Advanced Flash and Nano-Floating Gate Memories

Transcription

1 Advanced Flash and Nano-Floating Gate Memories

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3 Mater. Res. Soc. Symp. Proc. Vol Materials Research Society DOI: /opl Scaling Challenges for NAND and Replacement Memory Technology Kirk Prall Micron Technology, 8000 S. Federal Way, Boise, ID ABSTRACT Planar NAND technology is rapidly approaching its fundamental limits and will likely transition to a three dimensional structure. The scaling challenges facing NAND will be reviewed. Emerging memory technologies, such as the cross-point, will be discussed. The materials challenges facing emerging memories will be reviewed. INTRODUCTION NAND is currently the dominant semiconductor non-volatile storage technology used in solid state discs, USB flash cards, camera cards, etc. NAND technology has been rapidly scaling, faithfully following Moore s law since its invention circa 1987 by Toshiba [25]. NAND is facing severe scaling challenges which will likely result in the end of planar silicon scaling at around the 15nm generation. NAND may survive by adopting a 3-D structure, continuing to increase density, and reducing cost by adding layers in the third dimension. A possible alternative path may be that NAND will be replaced by a technology operating on a new mechanism that departs from silicon based electron storage. Large materials challenges exist and major breakthroughs will be required to successfully commercialize a NAND successor. NAND SCALING Currently, NAND manufacturers are shipping high volumes of product in the 20-25nm range [1][26]. There is a large research effort to push planar NAND technology to its ultimate limit. The amount of money expended on NAND research and development yearly is in the range of $750M-$1B; giving the technology a huge amount of technical momentum and enabling NAND to outrun other potential technologies. The technical challenges facing NAND are daunting and will ultimately lead to the demise of planar NAND as we know it. The technical challenges facing NAND scaling are summarized in Table I. There are several categories to consider: fundamental capacitance limits caused by scaling, scaling issues caused by the inability to reduce voltages or dielectric thickness, and reliability challenges. 3

4 Table I NAND Scaling Challenges Capacitance Issues Ref # Floating gate capacitance trending to zero [1][2] Electrons per cell trending to zero [1][2] Interference (parasitic capacitance trending to 100%) [3][4][5] Scaling Issues Tunnel oxide thickness stuck at ~7nm [6] Interpoly dielectric thickness stuck at ~10nm [7] Cell operating voltages stuck at ~25V (MLC) [1][2] Isolation stuck at ~6-8V, high aspect ratio isolation [1][2] Inhibit stuck at ~10V [8] Wordline to Wordline field trending to >10 MV/cm [1] Variation increasing [9][10][11] Noise increasing [12][13] Quantum mechanical tunneling noise [14] Parasitic electron trapping [1] Reliability Challenges Program disturb [15][16] Trapping / detrapping [17] Quick electron detrapping [18] Stress induced related charge loss [6] Retention is degrading [19],[20] Read disturb [21] Cycling is degrading [22] Random telegraph signal noise [23] Increasing ECC requirements [1][24] Several of these scaling challenges will be discussed in the following sections in order to highlight the difficulty of the problems that NAND is facing. The topics covered will include the few electron problem, parasitic electron trapping, giant random telegraph signal (RTS) noise, and quantum mechanical tunneling variation. Few Electron Problem The number of electrons on the floating gate is given by the equation Q=CV, where C is the inter-poly capacitance and V is the floating gate voltage. The inter-poly dielectric has been relatively constant over many generations, consisting of an oxide/nitride/oxide sandwich. The dielectric thickness and composition is limited by charge loss through the dielectric causing retention failures, and charge leakage during programming limiting the maximum threshold voltage of the transistor. Attempts to use high dielectric constant materials to increase the interpoly capacitance have not been successful to date. The capacitor area of the floating gate scales 4

5 with the area of the memory cell decreasing by the square of the shrink in feature size. The third dimension of the floating gate is the height and is limited by the practical limits of the aspect ratio and toppling of the floating gate stack. In practice, the floating gate capacitor area shrinks with scaling and the number of electrons stored on the floating gate decreases with scaling, as shown in Fig. 1. In 25nm MLC NAND technology, mv (30-50 electrons) of signal separate the states stored on the cell as a transistor threshold voltage, which increases the difficulty of maintaining state separation. The small number of electrons stored on the floating gate of highly scaled devices impacts many aspects of the cell, as many mechanisms are degraded by the lack of electrons. Fig. 1. The floating gate interpoly dielectric capacitance is shown as a function of the feature size highlighting the reduction in the capacitance with scaling (right axis). The left axis of the graph shows the number of electrons required to shift the threshold voltage of the cell by 100mV. The right picture shows a cell cross-section identifying the interpoly capacitance. Parasitic Electron Trapping The electric fields of a cell dielectric during operation are very high, typically reaching levels as high as 10 MV/cm. The high field gives the electrons high energy and can cause the electrons to be trapped at parasitic locations in the cell instead of the intended location in the floating gate, where the trapped electrons give a controlled shift in the floating gate potential in order to store the state of the cell. Fig. 2 shows the possible locations in the cell where the parasitic charge can be trapped. The table in Fig. 2 shows the number of electrons needed to shift the threshold of the floating gate voltage by 100mV. The impact of parasitic charge trapping can be obtained by comparing the number of electrons in the parasitic locations with the number of electrons on the floating gate (Q fg in green). The numbers shown in red require a smaller number of electrons to shift the cell threshold voltage than the charge placed on the floating gate. Therefore the red locations can dominate and degrade the cell operation. Note that the number of dominant trapping locations increases with scaling. For the cell to operate properly, the trapping ability of the parasitic locations has to be minimized by careful optimization of the tunnel, interpoly, sidewall oxides, and junctions. 5

6 Fig. 2. The left sketch shows potential parasitic electron trapping locations in a NAND cell. The right table shows the number of electrons required at each parasitic location for a 100mV shift in threshold voltage based on TCAD electro-static simulations. Giant Random Telegraph Signal Noise As can be seen in the previous section, a smaller number of electrons can have a large impact on a scaled NAND cell. In fact, a single electron can shift the threshold voltage and cell current, resulting in significant noise that can disrupt the sensing and operation of the cell. RTS is typically caused by an electron trap modifying the channel conduction and mobility, due to the charge impact of trapped electrons on the movement of the channel electrons. However, in reality, the channel current can be observed as filamentary in small devices. The filamentary current flow is governed by several competing mechanisms. First, the dopant boron atoms in the channel reduce the mobility and the filamentary current tends to flow where the boron atoms are nonexistent. Secondly, electron traps and interface states at the surface degrade the mobility and the filamentary current flow tends to avoid the filled traps and interface states. In a scaled device the channel electron flow forms a filament as the charge flow avoids these defects and a majority of the current flow can be through the filament. When a trap above the conducting filament fills or empties, a large change in the current occurs and creates the giant RTS effect causing a disproportionately large impact on the channel current. Giant RTS creates time varying current noise in the cell current, which causes very detrimental effects on the cell operation. The large variation in the threshold voltage is shown in Fig. 3, which is typically recovered by error correction used in NAND operation. 6

7 Fig. 3. The graph shows the variation in Vt of a distribution of cells measured 10 times to show the time varying giant RTS effect. Note the degradation in RTS with scaling. The image on the right shows a filamentary conducting channel in a scaled device. Asenov [10][11]. Quantum Mechanical Tunneling Variation NAND cells program and erase via quantum mechanical (Fowler-Nordheim) tunneling across the tunnel oxide. The few electron problem requires careful control of the number of electrons that tunnel during each programming voltage pulse. For a scaled cell, the variation in the number of electrons injected with each programming pulse is observed as noise, which widens the threshold voltage distribution of the cells resulting in a degradation of usable threshold voltage (signal) in the cell. Essentially, each time a cell is programmed it behaves differently, making it difficult to hit a targeted threshold voltage. Fig. 4. The degradation in cell function due to program noise is shown in the plot as an increase in the +/- 3 distribution with scaling. The y-axis shows the threshold voltage shift of a distribution of cells with a constant 400mV programming pulse step. The programmed distribution of the cell increases with scaling due to variation in the Fowler-Nordheim tunneling, caused by the few electron problem. The image on the right shows a representation of electrons tunneling through the tunnel oxide. 7

8 POST NAND TECHNOLOGY NAND technology is mainly driven by the lowest cost per bit. In order to achieve the lowest cost per bit, NAND technology sacrifices in many areas, such as: page addressing, large block sizes, complex controller technology requirements, poor latency, etc. Any NAND replacement technology will require a lower cost per bit, which is difficult to achieve given the current, highly-optimized position of state of the art NAND. The ability of NAND technology to store multiple bits per cell creates a large cost benefit that must be matched by any potential successor. There are potential paths where a future NAND replacement could have a different feature set, which is more valuable and could potentially reduce the cost pressure. Fig. 5 shows the likely future scaling paths for NAND [28]. Fig. 5. Future scaling paths for NAND and potential replacement technologies. As planar NAND reaches its limit, at around 15nm, its long run following Moore s law will come to an end, unless major breakthroughs in the problems shown in Table I are achieved. The most popular potential successor to planar NAND is 3-D NAND, where classical scaling will be replaced by stacking cells in the vertical direction in order to continue increasing density and reducing cost [27][29]. Instead of reducing the feature size, additional layers are stacked for cost reduction. Dozens of potential cell structures have been proposed. This is a logical path for NAND since the cell function and operation are very similar to planar NAND. Cross-Point Memory An alternative architecture to 3-D NAND is cross-point memory, which is also a 3-D structure. This type of memory is being heavily researched by many organizations. A sketch of cross-point memory is shown in Fig. 6. 8

9 Fig. 6. Cross-section of cross-point memory [34]. Cross-point memory consists of two electronic elements and a metal interconnect (bitlines and wordlines). The electronic elements are a diode and resistive memory element (RRAM). The technical requirements of each of these elements are very stringent and difficult to achieve. There has been no commercially successful, rewriteable, cross-point memory as of this date. RRAM Element The RRAM memory element typically functions by a resistance change due to an applied voltage or current, which is used to define the logic states of the memory. Many different physical mechanisms are being investigated as potential RRAM elements. The more popular ones are shown in Table II. The CMOS silicon based technology, which has been the mainstream technology for non-volatile memory for decades, is very well understood and can be easily modeled from first principles. Floating gate operation is very simple and is governed by the addition or removal of electrons from the floating gate. The replacement technologies shown in Table II operate on far more complex physical mechanisms, which tend to be poorly understood. Magnetic and phasechange based technologies have been researched for many years and are reasonably well understood. Most of the other resistive change based memories are poorly understood and it is not unusual to see multiple mechanisms described for identical materials systems in the literature. The situation is further complicated by differences in processing between different researchers. 9

10 Table II Mechanisms for RRAM Memory Element RRAM Element Mechanism Ref # Barrier Modulation Modification of Schottky barrier interface [31] Conductive Bridge RAM Metal filament formation through a dielectric [31] Ferroelectric tunneling Polarization change modifies barrier height [30] Magnetic Spin torque [33] Metal Oxide Stochiometric change results in resistance change [41] Multi-valence Oxide Ion motion changes resistance [32] Phase Change Amorphous to crystalline transition [34] Case Study Phase Change Materials Some of the phase change mechanisms and properties will be reviewed in order to highlight the complexities of the new memory systems and to demonstrate the great deal of work required to reduce the technology to practice and to understand the material system well enough to make it commercially viable. Phase change materials have been heavily researched because of their applications in CDs/DVDs and, recently, in memory systems. Phase change materials are a good case study for understanding the complexity of emerging memory material systems because it is the most mature material system. More than a decade of intensive research has gone into enabling phase change as a memory technology [36]. As a result, the important material properties that require optimization are understood. Phase change is the only emerging memory system currently in low volume production. Table III shows a partial list of the specific material parameters that must be optimized for successful phase change memory. The 23+ material properties and parameters must be optimized simultaneously to meet the demanding specifications for a memory cell. Clearly this is a daunting task. 10