Author : Fabrice BERNARD-GRANGER September 18 th, 2014

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1 Author : September 18 th, 2014

2 Spintronic Introduction Spintronic Design Flow and Compact Modelling Process Variation and Design Impact Semiconductor Devices Characterisation Seminar 2

3 Spintronic Introduction Spintronic Design Flow and Compact Modelling Process Variation and Design Impact Semiconductor Devices Characterisation Seminar 3

4 Electron spin Electronic information is conveyed using electron charge (e - ). Generation, manipulation, detection of charge currents: flow of electrons The most used material is semiconductor (Si) Spintronic information is conveyed through electron spin (e or e ). Generation, manipulation, detection of spin currents: flow of magnetic moments. The material of choice is ferromagnetic alloy (Fe, Co, Mg) Spin polarized current Current I Magneto resistance effect in multi layer stack electron flux 50% e 50% e X% e Y% e with X << Y Electron flux spin polarized M magnetization vector of a ferromagnetic layer Albert Fert, French physicist, was awarded the 2007 Nobel Prize Semiconductor Devices Characterisation Seminar 4

5 A Magnetic Tunnel Junction is the basic device used for storing information in a MRAM MTJ resistive states P state = 0 AP state = 1 Free layer magnetization dynamic during writing process r Free layer Oxide layer Reference Layer R r low resistance R large resistance M magnetization vector of a ferromagnetic layer MTJ stack Semiconductor Devices Characterisation Seminar 5

6 Field Induce Magnetic Switching (FIMS, Toggle) Thermally Assisted Switching (TAS) Spin Torque Transfer (STT) Spin Orbit Torque (SOT) Spin-Based Logic? Standalone MRAM, TMR (early 00 s) Embedded MRAM & Distribute non-volatility within logic (development) HDD, GMR (early 80 s) Use electron spin added to its electric charge Semiconductor Devices Characterisation Seminar 6

7 MRAM an emergent and credible candidate for SRAM and flash replacement Semiconductor Devices Characterisation Seminar 7

8 Q3, 2014 Q4, Japanese & US Cies joined their efforts on MRAM development Altera has taken the lead in enabling ST-MRAM within memory and storage markets supported by high performance, low power FPGAs Semiconductor Devices Characterisation Seminar 8

9 Q3, 2014 Q1, 2014 XMC a Chineese foundry, plan to developp MRAM process in The mobile chip giant Qualcomm has also been working on STT-MRAM, and in a recent test of TDK-Headway s chips, it found no errors in data retention after 528 hours at 150 C. Semiconductor Devices Characterisation Seminar 9

10 Spintronic Introduction Spintronic Design Flow and Compact Modelling Process Variation and Design Impact Semiconductor Devices Characterisation Seminar 10

11 Dynamic Cell Switching Circuit simulation IP flow Static cell hysteresis Monte Carlo simulation ANALOG flow Layout entry DRC/LVS/xRC Runset Simulations DIGITAL flow Schematic design entry *SPITT = Spintec spin Torque Transfert Tape out Semiconductor Devices Characterisation Seminar 11

12 Extraction/fit module (in progress with LETI) Dedicated fitting algorithm ICCAP tool plugin SPICE model SPITT (Spintec spin Torque Transfert) Modes (accuracy vs. speed) Physical phenomenon SPITT* core SPICE simulator Physics TCAD STTRAM Raw data Model card parameters corners and statistic Semiconductor Devices Characterisation Seminar 12

13 State - V I-V R-V SPITT Model Merits figures Semiconductor Devices Characterisation Seminar 13

14 Spintronic Introduction Spintronic Design Flow and Compact Modelling Process Variation and Design Impact Semiconductor Devices Characterisation Seminar 14

15 5 corners set to catch process variation in a MTJ based on the following parameters: RA (sheet resistance) [Ω.um²] (+/- 3 σ*) TMR (Tunneling Mangeto Resistance = R/R) [%] (+/- 3 σ*) I SW (Switching Current) [ua] (+/- 3 σ*) * σ = Gaussian distribution width RESISTANCE SWITCHING CURRENT Semiconductor Devices Characterisation Seminar 15

16 MRAM Cell = MTJ + Nmos transistor Full MRAM = MRAM Cell + all CMOS logic / analogic P V T # MRAM Process corners = 25 = 5 MTJ corners * 5 MOS corners # MRAM Voltage corners = 3 {Vdd x%, Vdd, Vdd +x%} # MRAM Temprature corners = 3 {Tmin, 27 C, Tmax} 225 corners 25 P 3 T 3 V Reduction to speed up the development phase Semiconductor Devices Characterisation Seminar 16

17 225 corners 5 functionals nominal conditions around 10 times less Electrical simulations across all PVT σ MTJ small σ MTJ large Design functionality loss due to inaccurate MTJ characterization Semiconductor Devices Characterisation Seminar 17

18 Logic FPGA Arithmetic Logic Unit Standard cell library (latch, flip flop, register..) Nano processor (based on spintronics cells) Look Up Table (silicon proven) Standard Cell Circuit Memory Memory, IC Design Test chip circuit (test device oriented) STT-RAM Full 256kb, 1 Mb and 4Mb single port compiler oriented (design on going) 8x8b SOT-RAM + peripheries (tape out ongoing) Fabless Design analog-numeric-system Control processors data centric Semiconductor Devices Characterisation Seminar 18

19 Spintronic technology Non volatility key for power reduction Ready for MRAM production New technology = new flow to set-up Silicon characterization PDK and Full Design plateform developement Spintronic system level Architecture tremendously modified New functionality arising Semiconductor Devices Characterisation Seminar 19

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