MRAM: Device Basics and Emerging Technologies

Transcription

1 MRAM: Device Basics and Emerging Technologies Matthew R. Pufall National Institute of Standards and Technology 325 Broadway, Boulder CO Phone: FAX: Presented at the THIC Meeting at the National Center for Atmospheric Research, 1850 Table Mesa Drive, Boulder CO July 19-20, 2005 Pufall, THIC 05: 1

2 Collaborators: NIST: Bill Rippard Shehzu Kaka Steve Russek Tom Silva Hitachi Global Storage: Jordan Katine Freescale: Fred Mancoff Nick Rizzo Pufall, THIC 05: 2

3 Outline What is MRAM? What are its advantages? When will we see MRAM? How does MRAM work? Spintronics basics: Electron spin and Magnetoresistance Anatomy of an MRAM bit Magnetic Switching Engineering Challenges: Consistency and Thermal Stability Freescale s MRAM solution: Toggle MRAM Big Problems in the Nano-Future: Scaling of bits Emerging Solutions to Scaling: Spin Torque Switching Pufall, THIC 05: 3

4 What is MRAM? Magnetic-based Random Access Memory: Uses small magnetic element to store {1,0} rather than electric charge (Some) Other types of RAM: Storage Method Virtues DRAM Charge on capacitor speed, size, cost SRAM Multiple transistors speed, size, no refresh FRAM Ferroelectric capacitor nonvolatile, speed Flash Transistor w/ extra nonvolatile, cost, size isolated gate All have advantages/tradeoffs: No universal solution Pufall, THIC 05: 4

5 MRAM advantages: Nonvolatile Fast Unlimited cycling Viability Data don t need refreshing instant on, low power Data retention >10 yrs Read/write symmetric 25 ns (10 ns in demo) byte writeable No fatigue after >10 16 cycles Integrated into CMOS process If made (very) inexpensive and scalable, a potential universal solution Pufall, THIC 05: 5

6 When (and where) will we see MRAM? Freescale:Demos out to vendors Shipping product end of 2005/early 2006 Uses: Replace battery-backed SRAM Cell phone/embedded memory 4 Mb chip, 180 nm process Others: IBM In development Toshiba/NEC Cypress, Honeywell:? Pufall, THIC 05: 6

7 How does MRAM work? x z y M 1 Hysteresis Loop 1 Field H Ferromagnets have hysteresis: Information stored in = 0 Hard disks, tape storage M y Magnetic Field H Magnetic fields used to change direction (state) of M Pufall, THIC 05: 7

8 How do you sense state of M? Magnetoresistance (MR): Resistance depends on direction of M current I M free M fixed Low Resistance High Resistance How? Electrons also have magnetic moments: Spin Spintronics Pufall, THIC 05: 8

9 Magnetization Filters e - Spin: Electron spins become spin-polarized in direction of M: Spin filter Magnetization M 1 Transmitted spins Incident e - current Nonparallel spins scatter more: Higher resistance R ~ cos(θ M ) Pufall, THIC 05: 9

10 Sense M by Resistance: Current I M free x1.2µm bit at 300mV bias M fixed RA (kω µm 2 ) MR=37% Magnetic Field H Field H State of M determined by electrical measurement: Magnetic Tunnel Junction (MTJ) Pufall, THIC 05: 10

11 Anatomy of an MRAM bit Digit Line Bit Line BL Program Line Hard axis field decreases H c Tunnel Barrier Pinned Ferromagnet Pinning Layer H hard Bit Line Line M H easy Free Ferromagnetic Layer MR (%) RA = 10 kωµm H easy (Oe) H hard = 0 Oe H hard = 40 Oe Pufall, THIC 05: 11

12 Bit Selection Energetics Unselected E 0 1 E b (a) H easy = 0 ½-Selected Lower barrier 0 π E b H easy 0 θ E b H hard 0 (b) H easy > 0 or H hard > 0 Selected (c) H easy > 0 and H hard > 0 Pufall, THIC 05: 12

13 Bit Addressing Challenges MRAM bit Programming Probability from 256k chip X H easy Min. Fail bits Operating point I hard H hard I hard i bit Ieasy i digit Bits switched/addressed by two fields Challenge: Bit-to-bit variations make choosing proper currents difficult/impractical Data courtesy Freescale Pufall, THIC 05: 13

14 Freescale s Solution: Toggle MRAM Bit Line BL Program Line Line 2 Free Tri-Layer Tunnel Barrier Pinned Ferromagnet Pinning Layer Program Line Line 1 Ferromagnetic layer Coupling Layer Ferromagnetic layer Coupled tri-layer programs more repeatably Pufall, THIC 05: 14

15 How does Toggle work? Timing Anti-parallel-coupled layers respond differently to fields: H Y H Y H X H X Low Resistance State High Resistance State H Y H X Figure courtesy Freescale Pufall, THIC 05: 15

16 What does Toggle do? Moves 1/2 select error horizon: H 2 4Mb, March 6N Toggle Map IV No disturb No disturb I toggling No disturb H 1 Operating region toggling III No disturb II i bit 0% switching region (no disturbs) Also increases bit volume (& thermal stability) i digit Data courtesy Freescale Pufall, THIC 05: 16

17 Freescale 4Mb MRAM Layer structure Program Path: Dashed green line Sense Path: Red line (isolated) Chip process at 180 nm node: Design ported to 90 nm (May 05) Pufall, THIC 05: 17

18 Future Difficulties: Scaling DRAM ½ pitch (nm) MPU Physical Gate Length (nm) From ITRS roadmap, 2003 MRAM must compete with this (aggressive!) scaling to be viable Pufall, THIC 05: 18

19 Scaling Problem: Thermal Stability As bits get smaller: more susceptible to thermal fluctuations Energy barrier proportional to volume, anisotropy: Must increase anisotropy to keep constant E 0 1 E b 0 π θ But, bigger anisotropy Need bigger fields to switch bit! Engineering problem Thermal fluctuations: Problem in hard disk media, read heads General concern in nanoscale devices! Pufall, THIC 05: 19

20 Possible Solution: Spin Transfer Electron spins become spin-polarized in direction of M: M exerts torque Incident e - current Magnetization M 1 Transmitted spins Torque Reverse also happens: polarized spins exert torque on M Pufall, THIC 05: 20

21 Spin-Transfer-Driven Switching Sign of torque depends on direction of current: Causes magnetization motion Current-driven hysteretic switching 7.65 Free layer Polarizer dv/di (Ω) Electron current Current (ma) Bistable device: Current through device drives switching Pufall, THIC 05: 21

22 High Speed ST-Switching 30 nm Katine HGST Switching Probability Pulse Amplitude Current (ma) µ 0 H = 66.7 mt Pulse Duration (ps) dv/di (Ω) /τ 95 (ns -1 ) Quasi-static sw itch ing current <300 ps switching time! I (ma) I (m A ) Pufall, THIC 05: 22

23 Spin Transfer Advantages Removes X-point field lines simpler lithography, two terminal devices X MTJ bit H easy Becomes more efficient as devices shrink: Scalable I hard H hard Fields: ~1/d Spin Transfer: ~1/d 2 d d d Pufall, THIC 05: 23

24 Spin-Transfer-Driven Oscillators Electron current µ 0 H = 0.9 T Power (pw) Current (ma) applied field H Frequency (GHz) Monostable device (high fields): Currenttunable, Coherent, microwave magnetization precession Pufall, THIC 05: 24

25 Summary MRAM is possible universal memory solution Spintronic device: Uses e - charge and spin Fast (3-10 ns switching times) Nonvolatile (magnetic storage) Low power (no refresh) Rad-hard (though supporting electronics aren t!) Toggle MRAM solves ½-select problem Problem: Must scale competitively with Si technology Nanomagnetic elements sensitive to temperature Complicated lithography Emerging technology solution: Switching with Spinpolarized electron currents Pufall, THIC 05: 25

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27 A Brief History of MRAM BIWB Core memory, first disk drive, flat film, bubble, plated wire A. V. Pohm and Honeywell investigating radiation hard memory based on anisotropic magnetoresistance (AMR) 1987 GMR Discovered: Binash, Grunberg et al, PRB B 39, 4828 (1989); Baibich, Fert et al. PRL 61, 2472 (1988) NVE formed to develop AMR based MRAM 1990 IBM Spin Valve (B. Dieny, V Speriosou, S. S. Parkin, B Gurney et al.) 1994 IBM Spin valve MRAM patent (D. D. Tang et al. IBM) 1995 Magnetic Tunnel Junctions (MTJ) (Modera et al PRL 74, 3273, 1995) 1996 DARPA MRAM program: Honeywell (PSV), Motorola (PSV MTJ) IBM (MTJ) 1999 IBM, Motorola MRAM working demos?? 2002 Motorola goes to cladded write lines & ttoggle write 2004 Motorola samples 4M MRAM chip 2004/ % TMR in MgO MTJs; Spin transfer switched MRAM 1984 IBM first tape MR head 1991 IBM first hard-disk MR head 1998 IBM introduces first GMR head Pufall, THIC 05: 27