New Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient writing (Voltage-Control) Spintronics Memory (VoCSM)

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1 New Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient writing (Voltage-Control) Spintronics Memory (VoCSM) Hiroaki Yoda Corporate Research & Development Center, Toshiba Corporation Supported by The ImPACT Program of the Council for Science, Technology and Innovation (Cabinet Office, Government of Japan).

2 Outline 1. Motivation of this study, to solve Historical Dilemma 2. Challenge by New approach Spin-Hall, VoCSM 3. How far can we go? 4. Proposal of new architectures 5. Future work

3 Motivation MRAM Dev. Day 2018 Leakage current Non NVM Frequent refresh Non Save energy consumption

4 The historical dilemma of non-volatile as working memories MRAM Dev. Day 2018 All Volatile ALU Power Q w =I w x t w SRAM SRAM SRAM Active Cache Standby Power Gating Busy applications MRAM LLC=NV ALU SRAM SRAM NV Power Active Non-volatility Cache Standby crystal Power Gating FeRAM PCRAM ReRAM Amorphous As a total, wasted more energy

5 Reduction Trend of Switching Energy per bit Field writing STT writing MRAM Dev. Day 2018 Switching energy per bit (fj/bit) 1E+7 1E+6 1E+5 1E+4 1E+3 1E+2 1E+1 1E I.Huai,et al., Hosomi, et. al. SRAM & DRAM Year H.Yoda,et al., 7 th IMFIPT2007 tp<5ns. H.Yoda,et al., IEDM2012 Sacrificed endurance Wasted huge energy

6 A big concern of endurance Iw TEM image of a tunnel-barrier

7 We have been working on to solve. MRAM Dev. Day 2018 H.YODA, et al., SPIE2014 H.Sukegawa, et al., APL to be published Ic (ua) Writing pulse-width (nsec.)

8 Outline 1. Motivation of this study, to solve Historical Dilemma 2. Challenge by New approach Spin-Hall, VoCSM 3. How far can we go? 4. Proposal of new architectures 5. Future work

9 Voltage-Control Spintronics Memory Element In addition to TMR-effect 1. VCMA-effect :Voltage-control magnetic anisotropy MTJ 5nm Reference -Layer TEM of the VoCSM Element Spin-Hall Electrode Tunnel- Barrier Storage-Layer 20nm Bottom-electrode(Ta) L. Liu, et al., Cornell Univ., 2012 H.Yoda, et al., Toshiba, Spin-Hall effect Wasted huge energy I csw (VoCSM) = 4eα * eff / ħθ SH { E r + E dmag } t n / w

10 The 1 nd Spintronics, Spin Hall-effect Current flow can polarize spins as we will at the surfaces Electrode 5d transition metal :Ta, W,,, (Write) Current z y x Electrode 5d transition metal :Ta, W,,,

11 The 2nd Spintronics, VCMA-effect (Voltage-Control Magnetic Anisotropy) Electrode e - Precession grows Easy axis Precession decays Electrode Storagelayer Electrode Storagelayer Electrode e - z y MTJ V= 0 V= V a V= V da ー + ー + x Electrode Wasted huge energy I csw (VoCSM) = 4eα * eff / ħθ SH { E r + E dmag } t n / w

12 How VoCSM works (VCMA-effect spin-hall effect) MRAM Dev. Day 2018 V= 0 -I Csw R I (write) current V= V a ー I Csw R I (write) current V= V da -1.5I Csw R + ー I (write) current

13 Fundamental Property of VoCSM elements MRAM Dev. Day 2018 H.Yoda,et al., IEDM2016 I w J Csw (MA/cm 2 ) MgO(~1.4nm)/CoFeB(1.1nm)/Ta(10nm) VCMA coefficient: 60fJ/(V/m)/m 2 >2.0J Csw J Csw 0J Csw Voltage(V) Lower the I w Speed up the writing Select the bit to write Calculation(Logic)

14 Efficient writing of VoCSM(theory) STT-writing VoCSM writing with 0V applied MTJ w f t n V=0V If the polarization & damping are the same, VoCSM with 0V applied has w f /t n times higher efficiency We can expect much better efficiency

15 R I=0 I=Iw MRAM Dev. Day 2018 Experimental Proof of the efficiency H I w (STT) RA=100Ωμm 2 I w (Spin-Hall) Self-Aligned structure S.Shirotori et al., Intermag2017 VoCSM with V=0 & θ SH = H.Yoda,et al., E-NVM2017 STT with MR=150% Size:50-60nm with AR of 3 Spin-Hall(V=0): about 3-4 times higher (compared with STT) (VoCSM(V=Va) : can be 6 times higher)

16 Proof of the high-efficiency of VoCSM 200 *in house data t p =20ns. 150 Self-Aligned structure I SW [μa] 100 p-stt MTJs * 30nmΦ VoCSM 50 The latest data MTJ area-s [nm 2 ]

17 The issue of STT, endurance at short pulse-width Endurance of VoCSM MRAM Dev. Day 2018 VoCSM, 3 terminals Ir Iw Ta,W,,(High melting temp.) MTJ Resisance (Ohm) Endurance 1E E+5 Write pulsewidth: 5nsec. Data 1 1.0E+5 Data 0 0.0E+0 1.0E+0 1.0E+3 1.0E+6 1.0E+91.0E+12 Pulse cycle

18 N.Shimomura, et al., 1E+50

19 Outline 1. Motivation of this study, to solve Historical Dilemma 2. Challenge by New approach Spin-Hall, VoCSM 3. How far can we go? 4. Proposal of new architectures 5. Future work

20 Experimental results of I sw I csw (VoCSM) = 4eα * eff / ħθ SH E sw (0V) t n / w f I sw at 20nsec. with V=0 (μa) θ SH =0.09 t DL =0.12 t p =20ns. Self-Aligned structure θ SH =0.14 t DL =0 θ SH =0.18 t DL = Esw (k B T)

21 Prospect of I csw I csw (VoCSM) = 4eα * eff / ħθ SH E sw (0V) t n / w 3μA I sw at 20nsec. (μa) Esw (k B T) θ SH =0.14 t DL =0 t p =20ns. Self-Aligned structure Good possibility to have θ SH =0.55 t DL =0 I csw (VoCSM) = 4eα * eff / ħθ SH E sw (-0.5V) t n / w = 1.5μA Q csw =30fC

22 Reduction Trend of Switching Energy per bit Field writing STT writing SOT & VoCSM Switching energy per bit (fj/bit) 1E+7 1E+6 1E+5 1E+4 1E+3 1E+2 1E+1 1E+0 SRAM & DRAM Year VoCSM 1 H.Yoda,et al., IEDM2016 S.A.VoCSM S.Shirotori,et al., MMM/Intermag2016

23 Outline 1. Motivation of this study, to solve Historical Dilemma 2. Challenge by New approach Spin-Hall, VoCSM 3. How far can we go? 4. Proposal of new architectures 5. Future work

24 Proposed Architectures of Spintronics Memory ALU L1 Cache L2 Cache L3 Cache Working Memory (1) ~12F 2 Lower the I w Speed up the writing Spin-Hall orvocsm (2) (3) Select the bit to write ~20F 2 Spin-Hall ( or VoCSM) 4F 2-8F 2 VoCSM

25 Demonstrated Fundamental Features Lower the I w Speed up the writing H.Yoda, et. al. IMW 2017 H.Yoda, et. al. IEDM 2016 Select the bit to write

26 Outline 1. Motivation of this study, to solve Historical Dilemma 2. Challenge by New approach Spin-Hall, VoCSM 3. How far can we go? 4. Proposal of new architectures 5. Future work

27 J Csw (MA/cm 2 ) Fundamental Property of VoCSM elements 0J Csw MgO(~ 1.4nm)/CoFeB(1.1nm)/Ta(10nm) VCMA coefficient: 60fJ/(V/m)/m 2 J Csw Another possibility of VoCSM >2.0J Csw H.Yoda,et al., IEDM2016 Lower the I w Speed up the writing Select the bit to write Calculation (Logic) Voltage(V) Conventional Logic VoCSL (Voltage-Control Spintronics Logic) Memory array Memory array Data B Data B Store Data A Data B (OR, AND,,,) Data A OR Data A AND A B A' A B A'

28 VoCSM (Voltage-Control ) Spintronics Memory Non-volatile Memory with Ultra-low Power, High-speed, and Unlimited Endurance Ultra-low Power writing MRAM Dev. Day 2018 Unlimited endurance Patent Japanese patent P , USP 9,881,660: High-density VoCSM (writing 8data with 2 write-pulses) Japanese patent P : High-Speed VoCSM (Complementary writing) Other 21 patents registered and other 27 patents pending Publication Digests of 62nd IEDM, session 27.6, San Francisco, CA, 3 7, December, 2016 Proceedings of IMW 2017, p. 165, Monterey, CA, May, 2017 IEEE Transactions on Magnetics, vol. 53, p , 2017 More than 10 invited talks and other 20 conference talks.

29 New Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient (Voltage-Control) Spintronics Memory (VoCSM) H. Yoda Corporate Research & Development Center, Toshiba Corporation Supported by The ImPACT Program of the Council for Science, Technology and Innovation (Cabinet Office, Government of Japan).

30 Summary 1. VoCSM writing is very powful to reduce the writing current to the order of spintronics limitation. 2. High-speed writing and unlimited endurance seem to co-exist for VoCSM. 3. The historical dilemma might be solved. 4. High-speed & high-density architectures were proposed and demonstrated the unique writing schemes. 5. Logic application was introduced and for the long run, it may find applications

31 How to select the bit to write MRAM Dev. Day 2018 unselected bits Selected bits unselected bits V da V a V da 0 Esw VCMA Esw

32 The issues 20nm (i) Static interaction (ii) Resonance Interactions between neighbor bits are big problems Definitely needs to make stray-field small, Like using Ferrimagnets,,

33 V a Write Error Rate Curves I w + 1E+0 1E-1 Conventional spin-hall writing WER 1E-2 1E-3 1E-4 1E-5 VoCSM writing J W (MA/cm 2 ) Deterministic

34 In-plane MTJ ( aspect ratio of =1 ) ΔEr ~44k B T(80nm 80nm) ΔEr improved by thikker film (1.5nm 2.5nm) MTJ SHE-EL SIL Under layer