A Universal Memory Model for Design Exploration. Ketul Sutaria, Chi-Chao Wang, Yu (Kevin) Cao School of ECEE, ASU
|
|
|
- Christian Hodge
- 5 years ago
- Views:
Transcription
1 A Universal Memory Model for Design Exploration Ketul Sutaria, Chi-Chao Wang, Yu (Kevin) Cao School of ECEE, ASU
2 Universal Memory Modeling because there is no universal memory device! Modeling needs in light of scaling A top-down view: Finite-State Machine (FSM) Type I and Type II memories Modeling examples: Flash, PCM, and MRAM Summary -2-
3 Scaling Trend: Logic Device Bulk/SOI MOSFET Strained MOSFET HKMG MOSFET MG MOSFET Dominated by silicon based CMOS Dedicated compact model, such as BSIM and PSP, to describe the physics underneath Bottom-up modules: electro-static and transport Future abstraction, using I on and I off, for fast design evaluation Common behavior to cover post-si FET devices -3-
4 Scaling Trend: Memory Device SRAM Flash PCM STT DRAM FRAM RRAM Tremendous variety in memory physics, materials, structures, and devices! SRAM and DRAM used to be the mainstream 3D technology, such as TSV, offers future opportunity of heterogeneous integration -4-
5 Design Perspective Speed Power Density, Date-Retention, Speed (R/W), Power, Voltage, Compatibility, Reliability Diverse design needs drive the development and selection of different types of memory -5-
6 Headline News Much more technological choices for memory design Still, there is no universal solution -6-
7 Modeling of Memory Devices From discrete, bottom-up approaches to a universal model Essential to efficiently bridge technology evaluation and design choice -7-
8 A Top-Down View General Behavior: A Finite-State Machine (FSM) The diagram of finite states is the formal and general method to describe a sequential unit The state may be defined as the output data (0 and 1), which can be a electrical signal or other physical values The transition/retention mechanisms distinguish one type of memory from another type -8-
9 Equivalent Circuit Diagram Input Control Output Control Static, Monotonic A common modeling structure for SPICE simulation Cell: performs the state transition and data retention Input control: translates the input signals for Write Output control: translates the output signals for Read Physical modules to cover various types of memories -9-
10 Two Types of Memory Type I Type II Two types based on the forces of cell operation Forces for 1 0 or 0 1 can be different Type I: external force only to stabilize/distinguish states Type II: both internal and external forces to control the states self-feedback mechanisms for meta-stability -10-
11 Modeling Examples DRAM SRAM DRAM: Type I Read and Write through the same resistor, but different capacitances SRAM: Type II Feedback between the cross-coupled inverters for data retention -11-
12 More Classifications Category Program (t) Erase (t) States Retention DRAM Charging Discharging Q in Cap (VM) Refresh Q Type I Type II Flash Charging (Hot carrier/ Tunneling) Discharging (Hot carrier/ Tunneling) Q in/out FG (NVM) PCM High voltage/current Reverse reaction Resistance (Amorphous/crystal states) (NVM) RRAM Conducting path (low R) Removal of the path Resistance change (NVM) SRAM Charging Discharging Q + positive feedback (VM) MRAM- MTJ FeRAM Spin alignment (currentinduced magnetic field) E-Field to change the polarization Reverse magnetic field Reverse E-Field * Magneto resistance (NVM) Polarizations (NVM) Device structure/material material material positive feedback material material Different operation modes may involve different physical forces -12-
13 Flash (Type I) V CG V FG C CG C FG V CG V FG C FG I G =f(v FG -V CH ) V FG is changed by carrier injection and regarded as the state value The program/erase is through the tunneling current, I G When V CG is applied, I G is activated Voltage difference between V FG and V CH determines I G -13-
14 SPICE Simulation vs. TCAD 4.0 DC simulation Transient V FG (V) V FG (V) Symbol: TCAD Line: Model Symbol: TCAD Line: Model V CG (V) Time (s) The model is implemented through sub-circuit and/or Verilog-A SPICE simulation converges well and matches TCAD data, with appropriate tuning of model parameters Read and Write in Flash may have different speeds, depending on the specific tunneling mechanism -14-
15 PCM (Type I) Top electrode R thermal Chalcogenide Resistor (heater) C thermal Bottom electrode R thermal Chalcogenide exhibits reversible transition between the amorphous and crystalline state, controlled by the temperature profile -15-
16 Phase Change Behavior 1.2 Resistance (a.u.) Symbol: measurement (A. L. Lacaita, et al., IEDM 04) Line: simulation Programming current (µa) The success of phase change (state transition) depends on the magnitude and the width of the input current pulse If not successful, the original phase (state) remains -16-
17 STT MRAM (Type II) θ dm dt dm 0Ms H M K1 uea M M dt s 2 Zeeman (external) Demagnetization (internal) Anisotropic (internal) Write in STT MRAM requires the magnetization change of one ferromagnetic layer, involves three energies d M dt d H cos M dt 0 s K s θ V sin cos -17-
18 Dynamic Simulation Magnetization Angle (degree) I < I c I (top left to bottom right) Pulse width: 10ns x x10-7 Time (s) The dynamic change is well captured by the model The balance between external/internal (feedthrough/feedback) forces are calculated by SPICE, reducing computation risk and cost -18-
19 Further Abstraction Out DRAM SRAM STT The transfer characteristic is essential to determine noise margin (stability) and drive strength (speed) Finite points to extract key static/dynamic properties Statistical variability and reliability embedded into finite points In -19-
20 Summary A universal SPICE model for various memory devices The generic interface between circuit and device research Easy customization to different physical mechanisms Fully compatible with the SPICE engine -20-
SPICE Modeling of STT-RAM for Resilient Design. Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu (Kevin) Cao School of ECEE, ASU
SPICE odeling of STT-RA for Resilient Design Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu (Kevin) Cao School of ECEE, ASU OUTLINE - 2 - Heterogeneous emory Design A Promising Candidate:
Author : Fabrice BERNARD-GRANGER September 18 th, 2014
Author : September 18 th, 2014 Spintronic Introduction Spintronic Design Flow and Compact Modelling Process Variation and Design Impact Semiconductor Devices Characterisation Seminar 2 Spintronic Introduction
Lecture 6 NEW TYPES OF MEMORY
Lecture 6 NEW TYPES OF MEMORY Memory Logic needs memory to function (efficiently) Current memories Volatile memory SRAM DRAM Non-volatile memory (Flash) Emerging memories Phase-change memory STT-MRAM (Ferroelectric
Flash Memory Cell Compact Modeling Using PSP Model
Flash Memory Cell Compact Modeling Using PSP Model Anthony Maure IM2NP Institute UMR CNRS 6137 (Marseille-France) STMicroelectronics (Rousset-France) Outline Motivation Background PSP-Based Flash cell
Digital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
Advanced Flash and Nano-Floating Gate Memories
Advanced Flash and Nano-Floating Gate Memories Mater. Res. Soc. Symp. Proc. Vol. 1337 2011 Materials Research Society DOI: 10.1557/opl.2011.1028 Scaling Challenges for NAND and Replacement Memory Technology
Perpendicular MTJ stack development for STT MRAM on Endura PVD platform
Perpendicular MTJ stack development for STT MRAM on Endura PVD platform Mahendra Pakala, Silicon Systems Group, AMAT Dec 16 th, 2014 AVS 2014 *All data in presentation is internal Applied generated data
Moores Law for DRAM. 2x increase in capacity every 18 months 2006: 4GB
MEMORY Moores Law for DRAM 2x increase in capacity every 18 months 2006: 4GB Corollary to Moores Law Cost / chip ~ constant (packaging) Cost / bit = 2X reduction / 18 months Current (2008) ~ 1 micro-cent
Sequential Logic. Handouts: Lecture Slides Spring /27/01. L06 Sequential Logic 1
Sequential Logic Handouts: Lecture Slides 6.4 - Spring 2 2/27/ L6 Sequential Logic Roadmap so far Fets & voltages Logic gates Combinational logic circuits Sequential Logic Voltage-based encoding V OL,
12. Memories / Bipolar transistors
Technische Universität Graz Institute of Solid State Physics 12. Memories / Bipolar transistors Jan. 9, 2019 Technische Universität Graz Institute of Solid State Physics Exams January 31 March 8 May 17
From Spin Torque Random Access Memory to Spintronic Memristor. Xiaobin Wang Seagate Technology
From Spin Torque Random Access Memory to Spintronic Memristor Xiaobin Wang Seagate Technology Contents Spin Torque Random Access Memory: dynamics characterization, device scale down challenges and opportunities
Page 1. A portion of this study was supported by NEDO.
MRAM : Materials and Devices Current-induced Domain Wall Motion High-speed MRAM N. Ishiwata NEC Corporation Page 1 A portion of this study was supported by NEDO. Outline Introduction Positioning and direction
Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies
A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies Model download website: mtj.umn.edu Jongyeon Kim 1, An Chen 2, Behtash Behin-Aein 2, Saurabh Kumar 1,
Memory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
Mechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices
Mechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices Rashmi Jha and Branden Long Dept. of Electrical Engineering and Computer Science University of Toledo Toledo,
New Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient writing (Voltage-Control) Spintronics Memory (VoCSM)
New Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient writing (Voltage-Control) Spintronics Memory (VoCSM) Hiroaki Yoda Corporate Research & Development Center, Toshiba
Semiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
ECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
CMOS Inverter. Performance Scaling
Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS
MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application
2011 11th Non-Volatile Memory Technology Symposium @ Shanghai, China, Nov. 9, 20112 MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application Takahiro Hanyu 1,3, S. Matsunaga 1, D. Suzuki
Magnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines
Non Volatile Memories Compact Models for Variability Evaluation
Non Volatile Memories Compact Models for Variability Evaluation Andrea Marmiroli MOS-AK/GSA Workshop April 2010 Sapienza Università di Roma Outline Reasons to address variability aspects Physics based
Spintronics. Seminar report SUBMITTED TO: SUBMITTED BY:
A Seminar report On Spintronics Submitted in partial fulfillment of the requirement for the award of degree of Electronics SUBMITTED TO: SUBMITTED BY: www.studymafia.org www.studymafia.org Preface I have
Floating Gate Devices: Operation and Compact Modeling
Floating Gate Devices: Operation and Compact Modeling Paolo Pavan (1), Luca Larcher (1) and Andrea MarmirolI (2) (1) Università di Modena e Reggio Emilia, Via Fogliani, 1 42100 Reggio Emilia (Italy) -
CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
Single Event Effects: SRAM
Scuola Nazionale di Legnaro 29/3/2007 Single Event Effects: SRAM Alessandro Paccagnella Dipartimento di Ingegneria dell Informazione Università di Padova alessandro.paccagnella@unipd.it OUTLINE Introduction
SEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
GMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
Lecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
Advanced Topics In Solid State Devices EE290B. Will a New Milli-Volt Switch Replace the Transistor for Digital Applications?
Advanced Topics In Solid State Devices EE290B Will a New Milli-Volt Switch Replace the Transistor for Digital Applications? August 28, 2007 Prof. Eli Yablonovitch Electrical Engineering & Computer Sciences
Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today
EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS141 2 1 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 Frequency
Supplementary Information for. Non-volatile memory based on ferroelectric photovoltaic effect
Supplementary Information for Non-volatile memory based on ferroelectric photovoltaic effect Rui Guo 1, Lu You 1, Yang Zhou 1, Zhi Shiuh Lim 1, Xi Zou 1, Lang Chen 1, R. Ramesh 2, Junling Wang 1* 1 School
Nomenclature, Advantages, Applications. Logic States, Read Ops, Write Ops
Critical Factors in Testing MRAM Devices W. Stevenson Cypress Semiconductor, Inc Inc. Southwest Test Workshop June G. Asmerom C. Taylor Electroglas AGENDA / OBJECTIVE MRAM Device? Nomenclature, Advantages,
EE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor
Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
An Overview of Spin-based Integrated Circuits
ASP-DAC 2014 An Overview of Spin-based Integrated Circuits Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafiné Ravelosona, and Claude Chappert
Thin Film Transistors (TFT)
Thin Film Transistors (TFT) a-si TFT - α-si:h (Hydrogenated amorphous Si) deposited with a PECVD system (low temp. process) replaces the single crystal Si substrate. - Inverted staggered structure with
A Review of Spintronics based Data Storage. M.Tech Student Professor
A Review of Spintronics based Data Storage By: Mohit P. Tahiliani S. Vadakkan M.Tech Student Professor NMAMIT, Nitte NMAMIT, Nitte CONTENTS Introduction Giant Magneto Resistance (GMR) Tunnel Magneto Resistance
A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology
A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology M. Kim 1, J. Kim 1, G. Park 1, L. Everson 1, H. Kim 1, S. Song 1,2,
NONVOLATILE SPINTRONICS: PERSPECTIVES ON INSTANT-ON NONVOLATILE NANOELECTRONIC SYSTEMS
SPIN Vol. 2, No. 2 (2012) 1250009 (22 pages) World Scienti c Publishing Company DOI: 10.1142/S2010324712500099 NONVOLATILE SPINTRONICS: PERSPECTIVES ON INSTANT-ON NONVOLATILE NANOELECTRONIC SYSTEMS K.
NEM Relay Design for Compact, Ultra-Low-Power Digital Logic Circuits
NEM Relay Design for Compact, Ultra-Low-Power Digital Logic Circuits T.-J. K. Liu 1, N. Xu 1, I.-R. Chen 1, C. Qian 1, J. Fujiki 2 1 Dept. of Electrical Engineering and Computer Sciences University of
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL Compatible Inputs The is a single gate CMOS Schmitt trigger inverter fabricated with silicon gate CMOS technology. It achieves high speed operation
Access from the University of Nottingham repository:
ElHassan, Nemat Hassan Ahmed (2017) Development of phase change memory cell electrical circuit model for non-volatile multistate memory device. PhD thesis, University of Nottingham. Access from the University
Multiple Gate CMOS and Beyond
Multiple CMOS and Beyond Dept. of EECS, KAIST Yang-Kyu Choi Outline 1. Ultimate Scaling of MOSFETs - 3nm Nanowire FET - 8nm Non-Volatile Memory Device 2. Multiple Functions of MOSFETs 3. Summary 2 CMOS
A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).
A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). The Final Exam will take place from 12:30PM to 3:30PM on Saturday May 12 in 60 Evans.» All of
ECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
Semiconductor Memory Classification
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
VLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) True-value Simulator
Design Verification Simulation used for ) design verification: verify the correctness of the design and 2) test verification. Design verification: Response analysis Specification Design(netlist) Critical
University of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
CHAPTER I. Introduction. 1.1 State of the art for non-volatile memory
CHAPTER I Introduction 1.1 State of the art for non-volatile memory 1.1.1 Basics of non-volatile memory devices In the last twenty years, microelectronics has been strongly developed, concerning higher
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS s and Circuits Palkesh Jain Texas Instruments, Banglore, India palkesh@ti.com D. V. Kumar, J. M. Vasi, and M. B. Patil Department
The Pennsylvania State University. The Graduate School. College of Engineering NON-VOLATILE FERROELECTRIC TRANSISTOR BASED MEMORY DESIGN:
The Pennsylvania State University The Graduate School College of Engineering NON-VOLATILE FERROELECTRIC TRANSISTOR BASED MEMORY DESIGN: DEVICE-CIRCUIT ANALYSIS CONSIDERING GATE LEAKAGE A Thesis in Electrical
CSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Instructor: Mohsen Imani. Slides from Tajana Simunic Rosing
CSE140L: Components and Design Techniques for Digital Systems Lab FSMs Instructor: Mohsen Imani Slides from Tajana Simunic Rosing Source: Vahid, Katz 1 FSM design example Moore vs. Mealy Remove one 1 from
N ano scale l S il ii lco i n B ased N o nvo lat l i atl ie l M em ory r Chungwoo Kim, Ph.D.
cw_kim@samsung.com Acknowledgements Collaboration Funding Outline Introduction Current research status Nano fabrication Process Nanoscale patterning SiN thin film Si Nanoparticle Nano devices Nanoscale
Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D
6.012 - Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter asics - Outline Announcements Handout - Lecture Outline and Summary The MOSFET alpha factor - use definition in lecture,
74HC86. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input Exclusive OR Gate MARKING DIAGRAMS High Performance Silicon Gate CMOS The is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MM74C906 Hex Open Drain N-Channel Buffers
Hex Open Drain N-Channel Buffers General Description The MM74C906 buffer employs monolithic CMOS technology in achieving open drain outputs. The MM74C906 consists of six inverters driving six N-channel
Wouldn t it be great if
IDEMA DISKCON Asia-Pacific 2009 Spin Torque MRAM with Perpendicular Magnetisation: A Scalable Path for Ultra-high Density Non-volatile Memory Dr. Randall Law Data Storage Institute Agency for Science Technology
ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
Digital Electronics Part II - Circuits
Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The
Memory Trend. Memory Architectures The Memory Core Periphery
Semiconductor Memories: an Introduction ti Talk Overview Memory Trend Memory Classification Memory Architectures The Memory Core Periphery Reliability Semiconductor Memory Trends (up to the 90 s) Memory
EE241 - Spring 2000 Advanced Digital Integrated Circuits. References
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution
Section 4. Nonlinear Circuits
Section 4 Nonlinear Circuits 1 ) Voltage Comparators V P < V N : V o = V ol V P > V N : V o = V oh One bit A/D converter, Practical gain : 10 3 10 6 V OH and V OL should be far apart enough Response Time:
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS0026 Dual High-Speed MOS Driver General Description DS0026 is a low cost
Nanoelectronics 12. Atsufumi Hirohata Department of Electronics. Quick Review over the Last Lecture
Nanoelectronics 12 Atsufumi Hirohata Department of Electronics 09:00 Tuesday, 20/February/2018 (P/T 005) Quick Review over the Last Lecture Origin of magnetism : ( Circular current ) is equivalent to a
Chapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two
5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were
Lecture 16: Circuit Pitfalls
Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution
Administrative Stuff
EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN
Overview ECE 553: TESTING AND TESTABLE DESIGN OF. Memory Density. Test Time in Seconds (Memory Size n Bits) 10/28/2014
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Memory testing Overview Motivation and introduction Functional model of a memory A simple minded test and its limitations Fault models March tests
Solid-State Electronics
Solid-State Electronics 84 (2013) 147 154 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse Progress in Z 2 -FET 1T-DRAM: Retention
2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
EE155/255 Green Electronics
EE155/255 Green Electronics Power Circuits 10/4/17 Prof. William Dally Computer Systems Laboratory Stanford University HW2 due Monday 10/9 Lab groups have been formed Lab1 signed off this week Lab2 out
LH5P8128. CMOS 1M (128K 8) Pseudo-Static RAM PIN CONNECTIONS
LH5P8128 FEATURES 131,072 8 bit organization Access times (MAX.): 60/80/100 ns Cycle times (MIN.): 100/130/160 ns Single +5 V power supply Power consumption: Operating: 572/385/275 mw (MAX.) Standby (CMOS
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
74VHCT138ATTR 3 TO 8 LINE DECODER (INVERTING)
3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t PD = 7.6 ns (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 4 µa (MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS: V IH = 2V (MIN.), V IL = 0.8V (MAX) POWER
P-channel enhancement mode MOS transistor
FEATURES SYMBOL QUICK REFERENCE DATA Very low threshold voltage s V DS = 2 V Fast switching Logic level compatible I D =.2 A Subminiature surface mount g package R DS(ON). Ω (V GS =. V) GENERAL DESCRIPTION
Analysis and design of a new SRAM memory cell based on vertical lambda bipolar transistor
Microelectronics Journal 34 (003) 855 863 www.elsevier.com/locate/mejo Analysis and design of a new SRAM memory cell based on vertical lambda bipolar transistor Shang-Ming Wang*, Ching-Yuan Wu Institute
DS0026 Dual High-Speed MOS Driver
Dual High-Speed MOS Driver General Description DS0026 is a low cost monolithic high speed two phase MOS clock driver and interface circuit. Unique circuit design provides both very high speed operation
A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node
A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node U.K. Klostermann 1, M. Angerbauer 1, U. Grüning 1, F. Kreupl 1, M. Rührig 2, F. Dahmani 3, M. Kund 1, G. Müller 1 1 Qimonda
MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter
4-Bit Decade Counter 4-Bit Binary Counter General Description The MM74C90 decade counter and the MM74C93 binary counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel
SRAM & FLASH Mixed Module
128K x 16 SRAM & 512K x 16 FLASH SRAM / FLASH MEMORY ARRAY SRAM & FLASH PIN ASSIGNMENT (Top View) 68 Lead CQFP (QT) FEATURES Operation with single 5V supply High speed: 35ns SRAM, 90ns FLASH Built in decoupling
Reliability Testing. Process-Related Reliability Tests. Quality and Reliability Report. Non-Volatile Memory Cycling Endurance
Reliability Testing The purpose of reliability testing is to ensure that products are properly designed and assembled by subjecting them to stress conditions that accelerate potential failure mechanisms.
INCREASING power density and static leakage currents
IEEE TRANSACTIONS ON MAGNETICS, VOL. 51, NO. 5, MAY 2015 3400408 Straintronics-Based Random Access Memory as Universal Data Storage Devices Mahmood Barangi and Pinaki Mazumder, Fellow, IEEE Department
ECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
MRAM: Device Basics and Emerging Technologies
MRAM: Device Basics and Emerging Technologies Matthew R. Pufall National Institute of Standards and Technology 325 Broadway, Boulder CO 80305-3337 Phone: +1-303-497-5206 FAX: +1-303-497-7364 E-mail: pufall@boulder.nist.gov
! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
5 V 64K X 16 CMOS SRAM
September 2006 A 5 V 64K X 16 CMOS SRAM AS7C1026C Features Industrial (-40 o to 85 o C) temperature Organization: 65,536 words 16 bits Center power and ground pins for low noise High speed - 15 ns address
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
Magnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY
Magnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY Magnetic Tunnel Junctions (MTJs) Structure High density memory
Lecture 11: MOSFET Modeling
Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power
This document is an author-formatted work. The definitive version for citation appears as:
This document is an author-formatted work. The definitive version for citation appears as: A. Roohi, R. Zand, D. Fan and R. F. DeMara, "Voltage-based Concatenatable Full Adder using Spin Hall Effect Switching,"
Embedded MRAM Technology For logic VLSI Application
2011 11th Non-Volatile Memory Technology Symposium Embedded MRAM Technology For logic VLSI Application November 7, 2011 Naoki Kasai 1, Shoji Ikeda 1,2, Takahiro Hanyu 1,3, Tetsuo Endoh 1,4, and Hideo Ohno