P-channel enhancement mode MOS transistor
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- Trevor Warner
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1 FEATURES SYMBOL QUICK REFERENCE DATA Very low threshold voltage s V DS = 2 V Fast switching Logic level compatible I D =.2 A Subminiature surface mount g package R DS(ON). Ω (V GS =. V) GENERAL DESCRIPTION PINNING SOT7 d V GS(TO). V P-channel, enhancement mode, PIN DESCRIPTION logic level, field-effect power transistor. This device has low,2,,6 drain threshold voltage and extremely fast switching making it ideal for 3 gate battery powered applications and high speed digital interfacing. source 6 Top view The is supplied in the SOT7 subminiature surface mounting package. 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 3) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage - 2 V V DGR Drain-gate voltage R GS = 2 kω - 2 V V GS Gate-source voltage - ± 8 V I D Drain current (DC) T a = 2 C -.2 A T a = C A I DM Drain current (pulse peak value) T a = 2 C A P tot Total power dissipation T a = 2 C -.7 W T a = C -.7 W T stg, T j Storage & operating temperature - C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-a Thermal resistance junction to FR board, minimum 3 - K/W ambient footprint August 998 Rev.
2 ELECTRICAL CHARACTERISTICS T j = 2 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = V; I D = µa V voltage V GS(TO) Gate threshold voltage V DS = V GS ; I D = ma V T j = C V R DS(ON) Drain-source on-state V GS =. V; I D = A mω resistance V GS =. V; I D = A - 7 mω V GS =.8 V; I D = -. A - 8 mω V GS =. V; I D = A; T j = C mω g fs Forward transconductance V DS = -9.6 V; I D = A.. - S I GSS Gate source leakage current V GS = ±8 V; V DS = V - ± ± na I DSS Zero gate voltage drain V DS = -9.6 V; V GS = V; - - na current T j = C - 3 µa Q g(tot) Total gate charge I D = A; V DD = V; V GS =. V nc Q gs Gate-source charge nc Q gd Gate-drain (Miller) charge nc t d on Turn-on delay time V DD = V; I D = A; ns t r Turn-on rise time V GS = -8 V; R G = 6 Ω -. - ns t d off Turn-off delay time Resistive load - - ns t f Turn-off fall time ns C iss Input capacitance V GS = V; V DS = -9.6 V; f = MHz - - pf C oss Output capacitance pf C rss Feedback capacitance pf REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T j = 2 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I DR Continuous reverse drain T a = 2 C A current I DRM Pulsed reverse drain current A V SD Diode forward voltage I F = -.62 A; V GS = V V t rr Reverse recovery time I F = -. A; -di F /dt = A/µs; ns Q rr Reverse recovery charge V GS = V; V R = -9.6 V nc August Rev.
3 2 Normalised Power Dissipation, PD (%) Peak Pulsed Drain Current, IDM (A) 8 6 D = single pulse P D tp D = tp/t 2. T Ambient Temperature, Ta (C) Fig.. Normalised power dissipation. PD% = P D /P D 2 C = f(t a ). E-6 E- E E-3 E E E+ E+ Pulse width, tp (s) Fig.. Transient thermal impedance. Z th j-a = f(t); parameter D = t p /T Normalised Drain Current, ID (%) Ambient Temperature, Ta (C) Fig.2. Normalised continuous drain current. ID% = I D /I D 2 C = f(t a ); conditions: V GS V Drain current, ID (A) -. V.8 V.. V Drain-Source Voltage, VDS (V).3 V.2 V. V V -.9 V VGS = -.8 V Fig.. Typical output characteristics, T j = 2 C. I D = f(v DS ); parameter V GS Peak Pulsed Drain Current, IDM (A).7.6 Drain-Source On Resistance, RDS(on) (Ohms) -.8 V V. V.2 V.3 V -.9 V.. RDS(on) = VDS/ ID d.c. tp = ms ms ms. Drain-Source Voltage, VDS (V) Fig.3. Safe operating area. T a = 2 C I D & I DM = f(v DS ); I DM single pulse; parameter t p V VGS =.V. Fig.6. Typical on-state resistance, T j = 2 C. R DS(ON) = f(i D ); parameter V GS.8 V - August Rev.
4 -. VDS > ID X RDS(on) C -.. Gate-Source Voltage, VGS (V) Fig.7. Typical transfer characteristics. I D = f(v GS ) Threshold Voltage, VGS(to), (V) typical minimum Junction Temperature, Tj (C) Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = ma; V DS = V GS Transconductance, gfs (S) VDS > ID X RDS(on) C.2..6 Fig.8. Typical transconductance, T j = 2 C. g fs = f(i D ) E E E-3 E E- E-6 E-7 VDS = - V Gate-Source Voltage, VGS (V) Fig.. Sub-threshold drain current. I D = f(v GS) ; conditions: T j = 2 C Normalised Drain-Source On Resistance Tj 2C VGS =. V. V.8 V Junction Temperature, Tj (C) Fig.9. Normalised drain-source on-state resistance. R DS(ON) /R DS(ON)2 C = f(t j ) Capacitances, Ciss, Coss, Crss (pf) Ciss Coss Crss Drain-Source Voltage, VDS (V) Fig.2. Typical capacitances, C iss, C oss, C rss. C = f(v DS ); conditions: V GS = V; f = MHz August 998 Rev.
5 - -3 Gate-source voltage, VGS (V) VDD = V RD = Ohms Gate charge, (nc) Fig.3. Typical turn-on gate-charge characteristics. V GS = f(q G ) Source-Drain Diode Current, IF (A) C Drain-Source Voltage, VSDS (V) Fig.. Typical reverse diode current. I F = f(v SDS ); conditions: V GS = V; parameter T j August 998 Rev.
6 MECHANICAL DATA Plastic surface mounted package; 6 leads SOT7 D B E A X y H E v M A 6 Q pin index A 2 3 A c e bp w M B Lp detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A bp c D E e H E Lp Q v w y mm OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT7 SC Fig.. SOT7 surface mounting package. Notes. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC8. 3. Epoxy meets UL9 V at /8". August Rev.
7 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 3). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August Rev.
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Rev. 2 27 November 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
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Rev. 2 12 March 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
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Rev. 1 16 June 29 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in TO22 package qualified to 175 C. This product is designed and qualified for use in a wide
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Rev. 3 29 February 28 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package using Nexperia High-Performance
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Rev. 1 22 April 29 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This
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Important notice Dear Customer, On 7 February 217 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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