PSMN004-60P/60B. PSMN004-60P in SOT78 (TO-220AB) PSMN004-60B in SOT404 (D 2 -PAK).
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1 Rev April 22 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS technology. Product availability: PSMN4-6P in SOT78 (TO-22AB) PSMN4-6B in SOT44 (D 2 -PAK). 2. Features Low on-state resistance Fast switching. 3. Applications 4. Pinning information High frequency computer motherboard DC to DC converters OR-ing applications. Table 1: Pinning - SOT78 and SOT44, simplified outline and symbol Pin Description Simplified outline Symbol 1 gate (g) 2 drain (d) [1] 3 source (s) mb drain (d) mb mb d g MBK116 MBB76 s MBK16 SOT78 (TO-22AB) SOT44 (D 2- PAK) [1] It is not possible to make connection to pin 2 of the SOT44 package.
2 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit V DS drain-source voltage (DC) 25 C T j 175 C - 6 V I D drain current (DC) T mb =25 C; V GS =1V - 75 A P tot total power dissipation T mb =25 C - 23 W T j junction temperature C R DSon drain-source on-state resistance V GS = 1 V; I D = 25 A; T j =25 C mω 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 6134). Symbol Parameter Conditions Min Max Unit V DS drain-source voltage (DC) 25 C T j 175 C - 6 V V DGR drain-gate voltage (DC) 25 C T j 175 C; R GS =2kΩ - 6 V V GS gate-source voltage (DC) - ±2 V V GSM gate-source voltage t p 5 µs; pulsed; - ±3 V duty cycle 25%; T j 15 C I D drain current (DC) T mb =25 C; V GS =1V;Figure 2 and 3-75 A T mb = 1 C; V GS =1V;Figure 2-75 A I DM peak drain current T mb =25 C; pulsed; t p 1 µs; Figure 3-4 A P tot total power dissipation T mb =25 C; Figure 1-23 W T stg storage temperature C T j junction temperature C Source-drain diode I S source (diode forward) current (DC) T mb =25 C - 75 A I SM peak source (diode forward) current T mb =25 C; pulsed; t p 1 µs - 4 A Avalanche ruggedness E DS(AL)S non-repetitive avalanche energy unclamped inductive load; I D =75A;t p =.1 ms; V DD =15V; R GS =5Ω; V GS = 1 V; starting T j =25 C - 5 mj I DS(AL)S non-repetitive avalanche current unclamped inductive load; V DD =15V;R GS =5Ω; V GS =1V; starting T j =25 C - 75 A Product data Rev April 22 2 of 13
3 12 P der (%) 3aa16 12 I der (%) 1 3ah Tmb (C) T mb (ºC) P der P tot I D = % I P der = % I tot ( 25 C ) D25C ( ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature ah81 I D (A) Limit R DSon = V DS /I D t p = 1 µs µs 1 DC 1 ms 1 ms 1 ms V DS (V) Fig 3. T mb =25 C; I DM is single pulse. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. Product data Rev April 22 3 of 13
4 7. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-mb) thermal resistance from junction to mounting base Figure K/W R th(j-a) thermal resistance from junction to ambient SOT78 vertical in still air K/W SOT44 mounted on a printed circuit board; minimum footprint K/W 7.1 Transient thermal impedance 1 3af48 Z th(j-mb) (K/W) δ = P t p δ = T single pulse t p T t t p (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. Product data Rev April 22 4 of 13
5 8. Characteristics Table 5: Characteristics T j =25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage I D =.25 ma; V GS =V T j =25 C V T j = 55 C V V GS(th) gate-source threshold voltage I D = 1 ma; V DS =V GS ; Figure 9 T j =25 C V T j = 175 C V T j = 55 C V I DSS drain-source leakage current V DS = 3 V; V GS =V T j =25 C µa T j = 175 C µa I GSS gate-source leakage current V GS = ±2 V; V DS = V na R DSon drain-source on-state resistance V GS = 1V; I D =25A;Figure 7 and 8 T j =25 C mω T j = 175 C mω Dynamic characteristics Q g(tot) total gate charge I D = 75 A; V DD =48V; V GS =1V; nc Q gs gate-source charge Figure nc Q gd gate-drain (Miller) charge nc C iss input capacitance V GS =V; V DS = 25 V; f = 1 MHz; pf C oss output capacitance Figure pf C rss reverse transfer capacitance pf t d(on) turn-on delay time V DD = 15 V; I D = 12 A; V GS =1V; ns t r rise time R G =6Ω; resistive load ns t d(off) turn-off delay time ns t f all time ns Source-drain diode V SD source-drain (diode forward) voltage I S = 25 A; V GS =V;Figure V Product data Rev April 22 5 of 13
6 3 I D (A) 2 T j = 25 ºC 7.5 V 8 V 1 V 2V 7 V 3ah V 6 V 1 I D (A) 8 6 V DS > I D x R DSon 3ah84 T j = 175 ºC V 4 5 V 2 25 ºC V GS = 4.5 V V DS (V) V GS (V) Fig 5. T j =25 C Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. T j =25 C and 175 C; V DS >I D x R DSon Transfer characteristics: drain current as a function of gate-source voltage; typical values..15 R DSon (Ω).1 5 V 5.5 V 6 V T j = 25 C o3ah83 a aa V V GS = 2 V 1 V 8 V 7 V I D (A) T j ( C) T j =25 C R a = DSon R DSon ( 25 C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. Product data Rev April 22 6 of 13
7 5 V GS(th) (V) 4 max 3aa I D (A) 1-2 3aa35 3 typ 1-3 min typ max 2 min T j ( o C) V GS (V) Fig 9. I D = 1 ma; V DS =V GS T j =25 C; V DS =5V Gate-source threshold voltage as a function of junction temperature. Fig 1. Sub-threshold drain current as a function of gate-source voltage ah87 C (pf) 1 4 C iss 1 3 C oss C rss V DS (V) V GS =V;f=1MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. Product data Rev April 22 7 of 13
8 1 I S (A) 8 V GS = V 3ah86 12 V GS (V) 1 I D = 75 A V DD = 48 V 3ah ºC T j = 25 ºC T j = 25 ºC V SD (V) Q G (nc) T j =25 C and 175 C; V GS =V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. I D = 75 A; V DD = 48 V Fig 13. Gate-source voltage as a function of gate charge; typical values. Product data Rev April 22 8 of 13
9 9. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-22AB SOT78 E p A A 1 D 1 q mounting base D L 1 (1) L 2 Q L b b c e e 5 1 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D D1 E e L L2 L1 (1) p max. mm q Q Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC EIAJ 3-lead TO-22AB SC-46 EUROPEAN PROJECTION ISSUE DATE Fig 14. SOT78 (TO-22AB). Product data Rev April 22 9 of 13
10 Plastic single-ended surface mounted package (Philips version of D 2 -PAK); 3 leads (one lead cropped) SOT44 A E A 1 D 1 mounting base D H D L p b c e e Q mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A D A 1 b c max. D E e L p H D Q OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT Fig 15. SOT44 (D 2- PAK) Product data Rev April 22 1 of 13
11 1. Revision history Table 6: Revision history Rev Date CPCN Description Product data; initial version Product data Rev April of 13
12 11. Data sheet status Data sheet status [1] Product status [2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-65A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL Definitions 13. Disclaimers Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 6134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 14. Trademarks TrenchMOS is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information, please visit For sales office addresses, send to: sales.addresses@ Fax: Koninklijke Philips Electronics N.V. 22. All rights reserved. Product data Rev April of 13
13 Contents 1 Description Features Applications Pinning information Quick reference data Limiting values Thermal characteristics Transient thermal impedance Characteristics Package outline Revision history Data sheet status Definitions Disclaimers Trademarks Koninklijke Philips Electronics N.V. 22. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 26 April 22 Document order number:
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