SRAM & FLASH Mixed Module
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1 128K x 16 SRAM & 512K x 16 FLASH SRAM / FLASH MEMORY ARRAY SRAM & FLASH PIN ASSIGNMENT (Top View) 68 Lead CQFP (QT) FEATURES Operation with single 5V supply High speed: 35ns SRAM, 90ns FLASH Built in decoupling caps and multiple ground pins for low noise Organized as 128K x 16 SRAM and 512K x 16 FLASH Low power CMOS TTL Compatible Inputs and Outputs Both blocks of memory are user configurable as 256K x 8 FLASH MEMORY FEATURES Operation with single 5V (±10%) Eight equal sectors of 64K bytes Any combination of sectors can be concurrently erased Supports full chip erase Embedded erase and program algorithms 20,000 program/erase cycles Hardware write protection SI/O 0 SI/O 1 SI/O 2 SI/O 3 SI/O 4 SI/O 5 SI/O 6 SI/O 7 GND SI/O 8 SI/O 9 SI/O 10 SI/O 11 SI/O 12 SI/O 13 SI/O 14 SI/O 15 NC A0 A1 A2 A3 A4 A5 FCS\1 GND FCS\2 SWE\1 A6 A7 A8 A9 A10 VCC NC NC A18 FWE\2 FWE\1 SWE\2 A17 SCS\2 OE\ SCS\1 A16 A15 A14 A13 A12 A11 VCC FI/O 0 FI/O 1 FI/O 2 FI/O 3 FI/O 4 FI/O 5 FI/O 6 FI/O 7 GND FI/O 8 FI/O 9 FI/O 10 FI/O 11 FI/O 12 FI/O 13 FI/O 14 FI/O 15 OPTIONS Operating Temperature Ranges Military (-55 o C to +125 o C) Industrial (-40 o C to +85 o C) MARKINGS XT IT Timing SRAM FLASH 35ns 90ns -35 Package Ceramic Quad Flatpack QT PIN FUNCTION Address Inputs A 0-18 SI/O 0-15 FI/O 0-15 OE\ SWE\ 1-2 FWE\ 1-2 SCS\ 1-2 FCS\ 1-2 V CC GND NC PIN DESCRIPTION SRAM Data Input / Outputs FLASH Data Input / Outputs Output Enable SRAM Write Enables FLASH Write Enables SRAM Chip Selects FLASH Chip Selects Power Supply Ground No Connect GENERAL DESCRIPTION The is a 2 MEG CMOS SRAM and 8 MEG CMOS FLASH Module organized as 128K x 16 (SRAM) and 512K x 16 (FLASH). These devices achieve high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. For more detailed information regarding the FLASH internal operations, programming, command definitions and functional descriptions, please see the AS8F512K32 data sheet located on our website at 1
2 FCS\2 FEW\2 FCS\1 FWE\1 SCS\2 SWE\2 SCS\1 SWE\1 OE\ A0 - A18 / A0-A16 / A0-A16 M0 M1 SRAM 128K x 8 SRAM 128K x 8 M2 M3 FLASH 512K x 8 FLASH 512K x 8 FI/O 8 - FI/O 15 FI/O 0 -FI/O 7 SI/O 8 - SI/O 15 SI/O 0 - SI/O 7 BLOCK DIAGRAM SRAM TRUTH TABLE MODE OE\ SCS\ SWE\ I\0 POWER Read L L H D OUT Active Write X L L D IN Active Standby X H X High Z Standby FLASH TRUTH TABLE USER BUS OPERATIONS OPERATION FCS\1-4 OE\ FWE\1-4 A0 A1 A6 A9 I/O Read L L H X X X X Data Out Output Disable L H H X X X X High Z Standby and Write Inhibit H X X X X X X High Z Write L H L A0 A1 A6 A9 Data In Sector Protect L VID L X X X VID X Verify Sector Protect L L H H H L VID Data Out Sector Unprotect see note 2 see note 2 L H H H see note 2 Data Out Verify Sector Unprotect L L H H H H VID Data Out Erase Operations L H see note 1 see note 1 see note 1 see note 1 see note 1 see note 1 LEGEND: L = V IL, H = V IH, X = Don't Care, V ID = 12V, See DC Charateristics for voltage levels NOTE: 1. See Chip/Sector Erase Operation Timings and Alternate CE\ Controlled Write Operation Timings of AS8F512K32 data sheet. 2. See Chart 1 (pg. 6) of AS8F512K32 data sheet. 2
3 ABSOLUTE MAXIMUM RATINGS* Voltage of Vcc Supply Relative to Vss...-.5V to +7V Storage Temperature C to +150 C Short Circuit Output Current(per I/O)...20mA Voltage on Any Pin Relative to Vss...-.5V to Vcc+1V Maximum Junction Temperature** C *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. SRAM & FLASH This is a stress rating only and functional operation on the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See the Application Information section at the end of this datasheet for more information. PARAMETER Flash Data Retention 10 years Flash Endurance (write / erase cycles) 20,000 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55 o C < T A < 125 o C and -40 o C to +85 o C; Vcc = 5V +10%) SRAM 1. All voltages referenced to V SS (GND) V for pulse width <20ns. 3. ICC is dependent on output loading and cycle rates. The specified value applies with the outputs FLASH NOTES: 1. Icc active while Embedded Program or Embedded Erase Algorithm is in progress. 2. Not 100% tested. 3
4 CAPACITANCE (V IN = 0V, f = 1MHz, T A = 25 o C )1 NOTE: 1. This parameter is sampled. AC TEST CONDITIONS Test Specifications Input pulse levels...vss to 3V Input rise and fall times...5ns Input timing reference levels...1.5v Output reference levels...1.5v Output load...see Figure 1 NOTES: Vz is programmable from -2V to + 7V. I OL and I OH programmable from 0 to 16 ma. Vz is typically the midpoint of V OH and V OL. I OL and I OH are adjusted to simulate a typical resistive load circuit. Figure 1 4
5 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTE 5) (-55 o C<T A < 125 o C and -40 o C to +85 o C; V CC = 5V +10%) SRAM AC DESCRIPTION SYMBOL -35 UNITS MIN MAX READ CYCLE READ cycle time t RC 35 ns Address access time t AA 35 ns Chip select access time t ACS 35 ns Output hold from address change t OH 2 ns Output enable to output valid t AOE 20 ns Chip select to output in low Z 1 t LZCS 3 ns Output enable to output in low Z 1 t LZOE 0 ns Chip disable to output in high Z 1 t HZCS 20 ns Output disable to output in high Z 1 t HZOE 20 ns SRAM AC (SWE\ & SCS\ controlled) DESCRIPTION SYMBOL -35 UNITS MIN MAX WRITE CYCLE WRITE cycle time t WC 35 ns Chip select to end of write t CW 25 ns Address valid to end of write t AW 25 ns Address setup time t AS 0 ns Address hold from end of write t AH 0 ns Data valid to end of write t DS 20 ns Data hold time t DH 0 ns WRITE pulse width t WP1 25 ns Output active from end of write 1 t LZWE 2 ns Write enable to output in High-Z 1 t HZWE 20 ns 1. This parameter is guaranteed but not tested. 5
6 SRAM READ CYCLE NO. 1 t RC A0-A16 t OH t AA SI/O 0-15 PREVIOUS DATA VALID DATA VALID SRAM READ CYCLE NO. 2 ADt RC SCS\ SOE\ SI/O 0-15 HIGH IMPED- t AA t ACS tlzcs t AOE t LZOE t HZCS DATA VALID 6
7 SRAM WRITE CYCLE NO. 1 (Chip Select Controlled) t WC A0-A16 SCS\ t AW tcw t AH t AS t WP1 1 SWE\ t LZ- t HZWE t DS t DH SI/O 0-15 DATA VALID WRITE CYCLE NO. 2 (Write Enable Controlled) t WC A0-A16 t AW SCS\ t AS t CW t AH SWE\ t WP2 1 t DS t DH SI/O 0-15 DATA VALID 7
8 FLASH ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (READ ONLY) (-55 C < TA < 125 C; V CC = 5V -5%/+10%) NOTES: 1. See Test Specification for test conditions. 2. Output driver disable time. 3. Guaranteed but not Tested. SRAM & FLASH Parameter Speed Options Symbol JEDEC Std. Parameter Description Test Setup -35 Units CE\=V t AVAV t IL, RC Read Cycle Time (Note 3) Min 90 ns OE\=V IL CE\=V t AVQV t IL, ACC Address to Output Delay Max 90 ns OE\=V IL t ELQV t CE Chip Enable Low to Output Valid Max 90 ns t GLQV t OE Output Enable to Output Delay Max 35 ns t OEH Output Enable Hold Time (Note 3) Read Min 0 ns Toggle and Data\Polling Min 10 ns t EHQZ t HZ Chip Enable High to Output High Z (Note 2, 3) Max 20 ns t GHQZ t DF Output Enable to Output High Z (Note 2,3) 20 ns t AXQX t OH Output Hold Time from Addresses, CE\ or OE\, Whichever Occurs First Min 0 ns Read Operation Timings Addresses Addresses Stable FCS\ t CE t DF FWE\ t CE t OH Outputs High-Z Output Valid High-Z OV 8
9 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55 C < TA < 125 C; V CC = 5V +/- 10%) WRITE / ERASE / PROGRAM Erase and Program FWE\ Controlled Parameter Symbol Speed Options Units JEDEC Std. Parameter Description -90 t AVAV t WC Write Cycle Time Min 90 ns t AVWL t AS Address Setup Time Min 0 ns t WLAX t AH Address Hold Time Min 45 ns t DVWH t DS Data Setup Time Min 45 ns t WHDX t DH Write Enable High to Input Transition Min 0 ns t OES Output Enable Setup Time Min 0 ns Read Recover time Before Write t GHWL t GHWL Min (OE\ high to FWE\ low) 0 ns t ELWL t CS FSC\ Setup Time Min 0 ns t WHEH t CH FSC\ Hold Time Min 0 ns t WLWH t WP Write Pulse Width Min 45 ns t WHWL t WPH Write Pulse Width High Min 20 ns t WHWH1 t WHWH1 Programming Operation Min 300 us t WHWH2 t WHWH2 Sector Erase Operation Max 15 sec t WHWH3 t WHWH3 Chip Erase Operation Max 120 sec t VCHEL V CC Setup Time Min 50 us Chip Program Time Max 11 sec 9
10 Program Operation Timings t WC t AS Addresses 555h PA PA PA t AH FCS\ OE\ t CH FWE\ t GHt WP t CS t DS tdh t WPH t WHWH1 FI/O 0 - FI/O 15 AOh PD Status D OUT Vcc NOTE: PA= Program Address, PD= Program data, D OUT is the true data at the program address. 10
11 Chip/Sector Erase Operation Timings t WC t AS Addresses 2AAh SA VA VA 555h for Chip Erase t AH FCS\ OE\ t CH t GHt WP t WHWH2 FWE\ t CS t DS t DH t WPH FI/O 0 - FI/O 7 or FI/O 8 - FI/ 55h 30th 10 for Chip Erase In Progress Complete Vcc NOTE: SA= Sector Address. VA = Valid Address for reading status data. 11
12 Data Polling Timings (During Embedded Algorithms) t RC Addresses VA VA VA FCS\ OE\ t CH t CE t OE t OEH t DF FWE\ t OH FI/O 7 or FI/O 15 Complement Complement True Valid Data High-Z FI/O 0 - FI/O 6 or FI/O 8 - FI/O 14 Status Data Status Data True Valid Data High-Z NOTE: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Toggle Bit Timings ( During Embedded Algorithms) t RC Addresses VA VA VA VA t CE FCS\ t CH t OE OE\ t OEH t DF FWE\ t OH FI/O 6 / FI/O 2 or FI/O 14 / FI/O 10 Valid Status (first read) Valid Status Valid Status Valid Status NOTE: VA=Valid address; not required for FI/O 6 or FI/O 14. Illustration shows first two status cycles after command sequence, last status read cycle, and array data read cycle. 12
13 MECHANICAL DEFINATIONS* Package Designator QT SRAM & FLASH 13
14 ORDERING INFORMATION SRAM & FLASH EXAMPLE's: QT-35/XT or QT-35/MIL Device Number Package Type Speed ns Process QT -35 /* *AVAILABLE PROCESSES /IT = Industrial Temperature Range /XT = Extended Temperature Range /MIL = MIL-STD-883 para NC -40 o C to +85 o C -55 o C to +125 o C -55 o C to +125 o C 14
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