An Overview of Spin-based Integrated Circuits

Transcription

1 ASP-DAC 2014 An Overview of Spin-based Integrated Circuits Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafiné Ravelosona, and Claude Chappert IEF, Univ. Paris-Sud, CNRS, Orsay, 91405, France Electronics Engineering, Univ. Beihang, Beijing, , China 1/12/2014

2 Outline Introduction Spintronics fundamental Spin-based memory devices and circuits Spin-based logic devices and circuits Emerging computing paradigms Conclusion and perspectives 2014/1/12 ASP-DAC

3 Moore s Law Ends? MOS Scaling Ends??? Leakage current (static) Long traffic (dynamic) Reliability issues Volatile Weisheng Zhao et al, IEEE VLSI-SOC, 2013 S. E. Thompson, S. Parthasarathy,Mater. Today, Vol. 9 No. 6, pp , /1/12 ASP-DAC

4 Spintronics is Emerging! Non-volatility 3D integration fast access speed ultra-low power Completely or partially replace CMOS technology Weisheng Zhao et al, IEEE VLSI-SOC, /1/12

5 Outline Introduction Spintronics fundamental Spin-based memory devices and circuits Spin-based logic devices and circuits Emerging computing paradigms Conclusion and perspectives 2014/1/12 ASP-DAC

6 Spintronics Histrory The origins of Spintronics can be traced back to the 1970s [Julliere 1975] The discovery of spin valve or GMR in 1988 (Nobel Prize Physics 2007 for A. Fert and P. A. Grunberg) The discovery of MTJ and STT in 1995 [Moodera et al.,miyazaki et al., and Berger and Slonczewski] The spin-valve sensor was firstly commercialized by IBM in /1/12 ASP-DAC

7 STT-MTJ Stochastic switching TMR = ( R R ) / R AP P P C. Chappert, A. Fert and F. Dau, Nature Mater., vol. 6, pp , W. S. Zhao, et al, Microelectron. Reliab., vol. 52, pp ,

8 STT-MTJ modeling Critical current C0 0 S K 2 Bg Precessional switching region, Thermal activation region, γe γe I = α ( µ M ) HV= α E µ µ g t pulse 1 2 µ BP Pr ( tpulse ) = 1 exp, = ( I 2 2 write IC 0) τ1 τ1 C + ln ( π ) em ( 1+ P ) d Pr ( t pulse ) 1 E I =, τ = τ exp ( (1 )) dt τ kt ( 1? Pr ( t pulse )) write B I C0 Dynamic reversal region, no explicit formulas B 2014/1/12 ASP-DAC

9 STT-MTJ modeling (Cont.) Verilog-A language STMicroelectronics 40 nm design-kit DC and transient simulation Y. Zhang et al., IEEE Trans. Electron Devices, vol. 59, no. 3, pp , /1/12 ASP-DAC

10 Reliability issues STT stochastic switching write errors TMR reduction read errors Read disturbance read errors TMR real TMR(0) = 1 +V / V 2 2 bias h tread Iread Prdis ( tread ) = 1 exp( N exp( (1 ))) τ I 0 C 0 S.Yuasa et al, Nat. Mat. (2004) W. S. Zhao, et al, Microelectron. Reliab., vol. 52, pp , /1/12 ASP-DAC

11 Outline Introduction Spintronics fundamental Spin-based memory devices and circuits Spin-based logic devices and circuits Emerging computing paradigms Conclusion and perspectives 2014/1/12 ASP-DAC

12 Magneto RAM (MRAM) Mainly based on the hybrid structure, i.e. MTJ+MOS Field driven FIMS-MRAM Thermal Assisted TA-FIMS-MRAM STT driven STT-MRAM Thermal Assisted TA-STT-MRAM 2014/1/12 ASP-DAC

13 MRAM (Cont.) MRAM uses MTJ as non-volatile storage element Read based on the TMR ratio of MTJ ITRS reported that STT-MRAM is one of the most promising candidates for the next generation non-volatile memory. Many prototypes or small-scale chips have been proposed or commercialized in markets currently Intrinsic anti-radiation, promising for aerospace applications 2014/1/12 ASP-DAC

14 Racetrack Memory Based on domain wall (DW) motion With MTJ as write and read heads Ultra-high storage density and low power operation One of the key challenges to build RM is to avoid any pinning defects in the magnetic strips Yue Zhang et al., JAP, vol.111, , /1/12 ASP-DAC

15 Advanced Spin-based Memories Voltage-Controlled (DC) MRAM or DW motion Spin-Orbit Coupling memory devices Further reduce programming power VS STT Far away for practical applications Na Lei et al., Nature Communications, vol.4, 1378, M.Miron et al, Nature 476,189 (2011) Y.Kim et al, arxiv:

16 Outline Introduction Spintronics fundamental Spin-based memory devices and circuits Spin-based logic devices and circuits Emerging computing paradigms Conclusion and perspectives 2014/1/12 ASP-DAC

17 Hybrid MTJ/CMOS Logic Circuits Mainly based on the logic-in-memory structure Inputs partly volatile,partly non-volatile 3D integration shortens traffic delay and power Low power and high speed Erya Deng et al., IEEE Trans. Magnetics,vol.49, pp ,

18 Domain Wall based Logics All the data inputs are stored in non-volatile states Area, power, delay overheads Same challenges as racetrack memory Defects in magnetic nanowires H-P Trinh, et al., IEEE. Circuits and Systems I, vol.60, pp , /1/12 ASP-DAC

19 Spin-Transistors Concept has been predicted early in the 1990s, but it was experimentally developed recently Most critical challenge for spin transistors is the magic material for the spin transport channel Graphene has been proved generally the potentiality and capability for the channel material Spin-MOSFET and Spin-FET Sugahara S, Nitta J.Proceedings of the IEEE, 2010, 98(12): /1/12 ASP-DAC

20 All-Spin Logic and Nano-Magnetic Logic Uses nano-magnets as digital spin capacitors to store data and spin to communicate, realizing logic gates based on the spin majority evaluation Ultra-low power and full spin system Challenges for material, fabrication and controllability Majority gate All spin full adder B. Behin-Aein et al, Nature nanotech, Vol. 5, pp , S. Breitkreutz, et al., IEEE Trans. on Magnetics, vol.49, pp ,

21 Spin Wave Logic It uses magnetic films as spin conduit of wave propagation, information can be coded into a phase or amplitude of the propagating spin wave Challenges: Spin wave amplitude decay and low spin wave phase velocity T. Schneider et al, Appl. Phys. Letters, vol.92, pp ,

22 Outline Introduction Spintronics fundamental Spin-based memory devices and circuits Spin-based logic devices and circuits Emerging computing paradigms Conclusion and perspectives 2014/1/12 ASP-DAC

23 Normally-Off Computing Systems Non-volatile storage: no static power Instant on/off capability Normally-Off when the CPU is in standby state Normally-On after power is reset Ultra-low power computing system Full use Partly use Idle state Weisheng Zhao et al., IEEE VLSI-SOC, 2013 H. Yoda, et alprocs. of IEDM, pp , S.H. Kang, Non-volatile Memories Workshop, 2010.

24 Dynamic Reconfigurable Systems FPGA with SRAM to store the configuration Low power efficiency and logic density Challenge for dynamically reconfigurable or in run-time Spin-based memory as configuration STT-MRAM, TA-MRAM and racetrack memory etc W.S. Zhao, et al., IEEE Trans. on Magnetics, vol.47, pp , 2011 W.S. Zhao, et al., ACM Trans. Reconfigurable Technology and Systems, vol.2, 2009.

25 Neuromorphic Systems Circuits and systems that work analogously to the brain Spintronics devices and memristor are the most promising candidates as synapse in neuromorphic systems currently Ultra-low power consumption Artificial intelligence M. Sharad et al., IEEE Trans. Nano., Vol. 11, pp , K. Roy et al., IEEE ISLPED, pp , /1/12 ASP-DAC

26 Conclusion and perspectives Overview of spin-based devices and circuits, their challenges and merits in current applications Emerging novel computing paradigms and architectures beyongd Von-Neumann architecture In the short term (i.e., 5-10 years), STT-MTJ/CMOS hybrid memory and logic could be the major candidates to achieve the commercial steps. In the long term (i.e., years), there isn t any evidence for any other devices or structures (e.g., Graphene based devices) to become the mainstream solution. 2014/1/12 ASP-DAC

27 Acknowledgement Thanks for your attention! Questions?? 2014/1/12 ASP-DAC