Memory and computing beyond CMOS

Transcription

1 Memory and computing beyond CMOS Dipartimento di Elettronica, Informazione e Bioingegneria Politecnico di Milano daniele.ielmini@polimi.it

2 Outline 2 Introduction What is CMOS? What comes after CMOS? Example: the memristor Boolean Logic Neuromorphic Computing Virtual lab tour

3 Outline 3 Introduction: What is CMOS? What comes after CMOS? Example: the memristor Boolean Logic Neuromorphic Computing Virtual lab tour

4 Inside our smartphone 4 Computer, tablet, smartphone Central Processing Unit (CPU) Intel 22 nm Ivy Bridge MOS transistor 45 nm p-channel

5 MOSFET characteristics 5 V GS I D V DS MOSFET = digital switch 2 or more digital switches allow to syntesize logic gates (NOT, NAND, NOR, etc.) and circuits (adder, flip flop, etc.)

6 1947: the first transistor 6 December 1947: Shockley, Brattain and Bardeen develop a point-contact transistor using Ge transistor and demonstrating analog amplification

7 1958: the first integrated circuit (IC) : J. Kilby (Texas Instruments) invents a technique to integrate all devices (transistor, R, C) in a single Ge crystal Later R. Noyce (Fairchild) improves the idea by integrating interconnects too, thus paving the way to ultra-large-scale integration (ULSI) design and fabrication 2000: Premio Nobel a Kilby per la sua invenzione

8 1965: Moore s law 8 After only 4 years from the first commercial IC, Moore observes that the number of transistors in the IC doubles every 18 months

9 Scaling = cost : C1103 1kb DRAM (Intel) costava 20$ 2014: 4GB SDRAM costa 20$ (sarebbe costata 600 M$ nel 1971) CMOS also improves its performance with scaling

10 Moore s law along the decades 10 N doubles every 18 months N doubles every 24 months

11 Limits of Moore s law 11 a = 0.54 nm

12 Scaling vs. heat 12 Due to the increasing power density, hence heat, clock rate has come to a saturation Less benefits from Moore s law scaling

13 Outline 13 Introduction: What is CMOS? What comes after CMOS? Example: the memristor Boolean Logic Neuromorphic Computing Virtual lab tour

14 After Moore s law 14 III-V semiconductors Tunnel FET 2D semiconductors

15 More-Moore strategies 15 (1) New materials (2) New architectures

16 After Moore s law 16 MEMS RF CMOS Image sensors III-V semiconductors Tunnel FET 2D semiconductors Spintronics Quantum computing Memristor

17 Outline 17 Introduction: What is CMOS? What comes after CMOS? Example: the memristor Boolean Logic Neuromorphic Computing Virtual lab tour

18 Different flavours of memristive devices 18 Set 10 kw Set Threshold switching Parallel (P) Antiparallel (AP) Reset Reset 10 MW V T V A TiN HfO 2 TiN RRAM resistive switching memory PCM phase change memory STTRAM spin transfer torque magnetic memory

19 The memristor 19 V A TiN I C = 9 ma HfO 2 Ti TiN Set Reset V A Set V A > 0 Reset V A < 0

20 Drift-diffusion model for defect migration 20 (a) Diffusion (b) Drift j D = D n D +μfn D D = D 0 e E A(V) kt(v) μ = D kt q S. Larentis, et al., IEEE Trans. Electron Devices 59, 2468 (2012)

21 Model equations 21 Equations solved self-consistently: nd D nd mfn t V 0 D Drift/diffusion equation Poisson equation k T V th 2 Fourier equation Boundary conditions: - TE: V = V(t), T = T 0 - BE: V = 0, T = T 0

22 Set process 22 S. Larentis, et al., IEEE T-ED 59, 2468 (2012)

23 Set process 23 Analytical model: S. Larentis, et al., IEEE T-ED 59, 2468 (2012) d dt = Ae E A kt inj

24 Reset process 24

25 Reset process 25 Analytical model: d dt = Ae E A kt inj

26 Real-time studies of resistive switching 26 Filament formed in Ag/Al2O2/Pt memristor Y. Yang, et al., Nature Communications 3:732 (2012) In-situ TEM study of switching in a-si In-situ TEM study of reset transition in Ag/ZrO2/Pt Q. Liu, et al., Adv. Mater. 24, 1844 (2012)

27 Memristive/resistive memory 27 TE Ta 2 O 5 /TaO x BE Courtesy: Z. Wei, Panasonic

28 3D crosspoint memory 28 Intel/Micron announced 3D high-density, high-speed memory Memory and select elements were not disclosed

29 Outline 29 Introduction: What is CMOS? What comes after CMOS? Example: the memristor Boolean Logic Neuromorphic Computing Virtual lab tour

30 Conditional switching in memristors 30 New computer based on ionic switching 1. Small (2-terminal) 2. Scalable 3. 3D technology 4. Nonvolatile (off power = 0) 5. Memory + logic 6. Complete (AND, IMP, NOT) V in out Q=0 Q =0 P=1 P =0 P = Q = P AND Q CMOS logic requires: 2 transistors Difficult interconnect 2D technology S. Balatti, et al., IEEE T-ED 62, 1831 (2015)

31 AND gate 31 V > 0 Q = 0 P = 0 V Q = 1 P = 0 V Q = 0 P = 1 V Q = 1 P = 1 V Q V P I I V P P I I V P V Q P Q V V P V Q Q Q V V Q P Q P V V P V Q Q P V Q = 0 P = 0 V Q = 0 P = 0 V Q = 0 P = 0 V Q = 1 P = 1 Enable pulse P = 0 Q = 0 P = 0 Q = 1 P = 1 Q = 1 P = 0 Q = 0 P = 0 Q = 0 Q = 0 P = 0 P = 1 Q = 0 P = 1 Q = 1 P Q P'=P*Q Q'=P*Q P' = Q' = P*Q AND condition: V set < V < 2V set Q = 1: bit transfer V

32 Material implication (IMP) 32 V < 0 Q = 0* P = 0 V Q = 1 P = 0 V Q = 0* P = 1 V Q = 1 P = 1 I V Q V P I I I V P V Q P Q = 0* Q V V P V Q P Q V V P V Q P V V P V Q Q P V Q = 1 P = 0 V Q = 1 P = 0 V Q = 0* P = 1 V Q = 1 P = 1 Enable pulse P = 0 Q = 0* P = 0 Q = 1 Q = 0* P = 1 P = 1 Q = 1 P = 0 Q = 1 P = 0 Q = 1 Q = 0* P = 1 P = 1 Q = 1 P Q P'=P Q'=P Q 0 0* * 1 0* Q' = P Q IMP condition: V > V reset Q = 0*: NOT gate V

33 OR and XOR 33 A + B = A B A B = A B B A

34 Outline 34 Introduction: What is CMOS? What comes after CMOS? Example: the memristor Boolean Logic Neuromorphic Computing Virtual lab tour

35 IoT intelligence 35 Traffic monitoring/vehicle detection Robot navigation Drone navigation W. Yan, et al., Front. Neurorob Facial detection/recognition Epilectic seizure prediction

36 Functionality = connectivity 36 Neuromorphic architectures Density in the human cortex: Cells = 10 7 cm -2 Synapses = cm -2 (10 4 average connectivity) In vivo Neuron Axons/dendrites Synapses In silico CMOS Interconnect RRAM/memristors

37 Resistance control and multilevel operation 37 RRAM LTP LTD 3.2 V, 300 μs -2.8 V, 300 μs # pulses S. H. Jo, et al., Nano Lett. 10, 1297 (2010) I-controlled set V-controlled reset S. Yu, et al., IEEE T-ED 58 (2011)

38 Spike-timing dependent plasticity (STDP) 38 PRE synapse POST Pre-synaptic neuron G Post-synaptic neuron t = t POST - t PRE Depression t < 0 Potentiation t > 0 t

39 Evidence in biological systems 39 G.-Q. Bi and M.-M. Poo, J. Neuroscience 18 (1998) L. F. Abbott and S. B. Nelson, Nature Neurosci. 3, 1178 (2000)

40 Hybrid CMOS/memristive synapse 40 1T1R synapse V TE V TE 2T1R synapse V G BE V CG V FG BE S. Ambrogio, et al., Nanotechnology 24 (2013) Z.-Q. Wang, et al., Front. Neurosci. 8:438 (2015)

41 1T1R synapse 41 Synapse V TE PRE POST V G BE - + V int V G Integrate Fire

42 Communication (integrate) 42 V TE = const. PRE spike Synapse V TE PRE POST V G BE V G - + V int Integrate Fire

43 Plasticity (fire) 43 POST spike V TE+ PRE spike Synapse V TE V TE- PRE POST V G BE V G - + V int Integrate Fire

44 Depression ( t < 0) 44 PRE spike POST spike t<0 Reset PRE spike Synapse V TE PRE POST V G BE - + V int V G Integrate Fire

45 Potentiation ( t > 0) 45 PRE spike POST spike t>0 Set PRE spike Synapse V TE PRE POST V G BE V G - + V int Integrate Fire S. Ambrogio, et al., IEEE Trans. Electron Devices 63, 1508 (2016)

46 STDP characteristics kw 30 kw 50 kw 75 kw R 0 R 0 Data Calculated 125 kw 200 kw 300 kw 500 kw State-dependent STDP by experiments and simulations using an analytical RRAM model S. Ambrogio, et al., IEEE Trans. Electron Devices 63, 1508 (2016)

47 2T1R synapse by IBM 47 Similar design but integrated 2T1R structure PCM instead of a RRAM, advantage = unipolar operation, no need for negative voltages S. Kim, et al., IEDM Tech. Dig. 443 (2015)

48 Learning networks: the perceptron 48 Introduced by Minsky in the late 1950 Modeled by convergence theorem by Rosenblatt, 1962 Perceptron can be trained to learn and classify patterns

49 Demonstrating on-line unsupervised learning 49 Pattern First layer 1 28x28 neurons PRE 2 28x28 synapses 3 Second layer 1 neuron 784 POST 1

50 Stochastic pattern learning 50 Input 50 ms Synapse Weights V th 100 ns

51 On-line learning and update 51

52 Multiple pattern learning 52 Input 1 st layer 784 neurons Inhibitory synapses Synapses PRE nd layer 10 neurons 784 POST

53 10-digit learning and classification 53 The network allows for pattern differentiation and classification

54 Hardware demonstration 54

55 Outline 55 Introduction: What is CMOS? What comes after CMOS? Example: the memristor Boolean Logic Neuromorphic Computing Virtual lab tour

56 Weight 1/R [S] Weight 1/R [S] From materials to systems: the full chain 56 (a) RRAM V TE (b) V G V G a a PRE Current Input from other synapses POST V TE Memristor fabrication/characterization Input Weights Input 10 Weights Input Weights Device simulation and circuit design Time [s] Circuit design/testing

57 Virtual lab tour a a

58 eight 1/R [S] Weight 1/R [S] Virtual lab tour Input Weights Input 15 Weights Input 15 Weights Time [s]

59 Virtual lab tour

60 Virtual lab tour MoS 2 CoFeB MgO CoFeB AP P P AP

61 Virtual lab tour