The N3XT Technology for. Brain-Inspired Computing
|
|
- Jodie Walters
- 6 years ago
- Views:
Transcription
1 The N3XT Technology for Brain-Inspired Computing SystemX Alliance Department of Electrical Engineering
2 Source: Google
3 Source: vrworld.com
4 Source: BDC Stanford Magazine University
5 988 5 Winter Olympic Games in Calgary, Canada
6
7 Source: Gogamguro.com
8 s of kw Source: Google
9 Small to moderate scale Large scale Scale Up Requires Energy Efficiency Application Emulating 4.5% of human brain: 3 synapses, 9 neurons Deep sparse autoencoder: 9 synapses, M images Hardware used Blue Gene/P: 36,864 nodes, 47,456 cores, CPUs (6, cores) Estimated power consumption 2.9 MW (LINPACK) ~ kw (cores only) Convolutional neural net with 6M synapses, 65K neurons 2 GPUs,2 W Restricted Boltzmann Machine: 28M synapses; 69,888 neurons Processing s of speech using deep neural network GPU CPU GPU CPU (4 cores) 55 W 65 W 238 W 8 W 9 S. B. Eryilmaz et al., IEDM
10 These nanotechnology innovations will have to be developed in close coordination with new computer architectures, and will likely be informed by our growing understanding of the brain a remarkable, faulttolerant system that consumes less power than an incandescent light bulb
11 Approaches of Neuromorphic Hardware
12 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware
13 Approaches of Neuromorphic Hardware Neuromorphic hardware Conventional hardware (CPU, GPU, supercomputers, etc)
14 Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc)
15 Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) Brain emulation on BlueGene [7] HTM [3]
16 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) Brain emulation on BlueGene [7] HTM [3] Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
17 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) TrueNorth [6] SpiNNaker [9] Human Brain Project [2] Brain emulation on BlueGene [7] HTM [3] Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
18 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) TrueNorth [6] SpiNNaker [9] Hebbian learning Spike-based ANN Brain emulation on BlueGene [7] Human Brain Project [2] PCM, RRAM, CBRAM HTM [3] Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
19 Conventional ML algorithms Biology-based models / algorithms Approaches of Neuromorphic Hardware Neuromorphic hardware with analog nonvolatile memory synapses Conventional hardware (CPU, GPU, supercomputers, etc) TrueNorth [6] SpiNNaker [9] Hebbian learning Spike-based ANN Brain emulation on BlueGene [7] Human Brain Project [2] PCM, RRAM, CBRAM HTM [3] ANN, RBM, sparse learning PCM, RRAM Cats on YouTube ANNs: ConvNets, DNNs, DBNs [-3]
20 Many of these breakthroughs will require new kinds of nanoscale devices and materials integrated into three-dimensional systems and may take a decade or more to achieve
21 N3XT Nanosystems Computation immersed in memory Memory Ultra-dense vertical connections Computing logic
22 N3XT Nanosystems Computation immersed in memory Memory Ultra-dense vertical connections Computing logic Impossible with today s technologies
23 N3XT: Computation Immersed in Memory 3D Resistive RAM Massive storage D CNFET, 2D FET Compute, RAM access MRAM Quick access D CNFET, 2D FET Compute, RAM access D CNFET, 2D FET Compute, Power, Clock thermal thermal thermal Not TSV Ultra-dense, fine-grained vias Silicon compatible
24 Aly et al., IEEE Computer,
25 Non-Volatile Memory (NVM) Top Electrode phase change material oxide isolation switching region Bottom Electrode metal oxide Top Electrode oxygen ion filament oxygen vacancy Bottom Electrode Active Top Electrode solid electrolyte filament metal atoms Bottom Electrode partially reset state fully reset state TiN TiN TiN 25nm poly c-gst T amorphous TiN SiO 2 poly c-gst amorphous 2 nm O 2 TiN SiO 2 TiN SiO 2 TiOx/ HfOx nm Cu ion Electrolyte Bottom electrode Phase change memory (PCM) Metal oxide resistive switching memory (RRAM) Conductive bridge memory (CBRAM) 26 D. Kuzum et al., Nano Lett. 23, Y. Wu et al., IEDM 23; A. Calderoni et al., IMW
26 Non-Volatile Memory (NVM) Synapse Analog programmable Scalable to a few nm Stack in 3D partially reset state fully reset state TiN TiN TiN 25nm poly c-gst T amorphous TiN SiO 2 poly c-gst amorphous 2 nm O 2 TiN SiO 2 TiN SiO 2 TiOx/ HfOx nm Cu ion Electrolyte Bottom electrode Phase change memory (PCM) Metal oxide resistive switching memory (RRAM) Conductive bridge memory (CBRAM) 27 D. Kuzum et al., Nano Lett. 23, Y. Wu et al., IEDM 23; A. Calderoni et al., IMW
27 Resistance (Ohm) Resistance (Ohm) Nanoscale Memory as Synaptic Weights Synaptic updates in the brain: basis for learning Requirement: analog resistance change -step grey scale (% resolution) Pulse Number 4 3 Partial RESET Pulse Number Partial SET Phase change synapse D. Kuzum et al., Nano Lett., p. 279 (22)
28 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
29 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
30 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
31 w (%) w (%) w (%) w (%) Synaptic weight change w (%) Synaptic Weight Change w (%) Nanoscale Memory Can Emulate Biological Synaptic Behavior STDP (spike-timing-dependent plasticity) t (ms) t (ms) t (ms) t (ms) =-8.6 =-29 LTP- LTP-2 LTP-3 LTD- LTD-2 LTD-3 =-.3 = =29.5 = Spike timing t (ms) 4 ms 25 ms 5 ms 35 ms 2 2 ms 45 ms Number of pre/post spike pairs Various STDP kernels Various time constants Weight update saturation D. Kuzum et al., Nano Lett., p. 279 (22)
32 Hyper Dimensional (HD) Computing Elements of Hyper dimensional Computing: Also known as vector symbolic architectures or holographic reduced representation (Kanerva, Cognitive Computation, (2):39-59,29) Information is represented by High-dimensional representation (e.g., D =,) Variables and values are combined into a holistic record using vector algebra: Multiplication for Binding Addition for Bundling Composed vector can in turn become a component in further composition Holistic record is decoded with (inverse) multiplication Approximate results of vector operations are identified with exact ones using content-addressable memory 33 ENIGMA
33 HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
34 Algorithms HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
35 System and Circuit Design Algorithms HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
36 Associative memory enabled by novel device technologies System and Circuit Design Algorithms HD Computing layers Letters/Image features/ Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA Letters/Image features/ sequences... Phonemes/DNA sequences... Application Projected into hyper-dimensional space Random vectors: k ~ k bits Representation MAP Kernels (Multiplication-Addition-Permutation) v v2, sum(v, v2, ), sum(v), perm(v) Computation unknown closest? Measure distance : learned & unseen vectors (recognition/classification/reasoning/etc.) Inference
37 Hyperdimensional (HD) Computing Monolithic 3D enables Energy-efficient classification Area efficient HD projection use RRAM variability & stochastic switching 3D RRAM + low power access transistors + address decoders High-density Inter-layer vias Low power computation
38 3D Enables In-Memory Computing 3D RRAM with FinFET BL select TiN/Ti (5 nm) TiN/Ti Layer 4 (L4) Layer 3 (L3) Layer 2 (L2) Layer (L) (TE) TiN TiN TiN TiN (BE) TiN (2 nm) 5 nm H. Li et al., Symp. VLSI Tech.,
39 Current ( A) Resistance ( ) Resistance ( ) B B B B MAP Kernels: 3D RRAM Approach Key HD operations: multiplication, addition, permutation k D C k B 4 XOR {, } system M k k M A equiv. Multiplication {-, } system C = Multiplication Input AB = pillar addr. = D C B A D = D = Input AB = pillar addr. = C = k M G T Logic Evaluation Cycle (#) Addition Symbol: -pillar exp. 2 Input AB = pillar addr. = D = Logic Evaluation Cycle (#) D C B A D = Input AB = pillar addr. = D C B A C = C = k M G T k k M G G Measured data on 4-layer 3D vertical RRAM Line: 2-pillar emulated Addition Cycle (#) L44 L33 L22 L L4 L3 L2 L Permutation gnd V DD V DD gnd B E+5 (a) gnd V B DD 2 ns (b) 2 ns V DD gnd Measured LRS (~kω) 5.3E E E+5.E+6 gnd V DD V DD gnd Measured HRS (4kΩ-MΩ).E+6.E E E E E+ 5.3E+5.3E+ 4.E+5 4.E+.E+6.E E E E E+5 5.3E+5 5.3E+5 4.E+5 4.E+5
40 3D Integration of Memory and Logic Circuits within the Same Layer & Across Layers Synapses/Weights (3D RRAM) Logic (Si CMOS) Neuron circuits Communication Synapses/Weights (CNFET/2D FET) + RRAM
41 Nano-Engineered Computing Systems Technology Aly et al., IEEE Computer,
42 Students and Post-Docs
43 Collaborators Gert Cauwenberghs Siddharth Joshi Emre Neftci (UC San Diego) Jinfeng Kang (Peking U) Chung Lam SangBum Kim Matt Brightsky K.S. Lee, J.M. Shieh, W.K. Yen (NDL, Taiwan)
44 Sponsors E2CDA Engima Non-Volatile Memory Technology Research Initiative
45 Stanford SystemX Alliance
46 Non-Volatile Memory Technology Research Initiative
47 End of Talk Questions? fully set state partially reset state fully reset state TiN TiN TiN poly c-gst poly c-gst poly c-gst amorphous amorphous SiO 2 SiO 2 SiO 2 TiN TiN TiN
48 Open Research Questions. Functionality performance/watt, performance/m 2 variability reliability 2. Scale up (system size), scale down (device size) 3. Role of variability (functionality, performance) 4. Fan-in / fan-out, hierarchical connections, power delivery 5. Low voltage (wire energy device energy) 6. Stochastic learning behavior statistical learning rules 7. Meta-plasticity (internal state variables) 8. Timing as an internal variable 9. Learning rules: biological? AI?. Algorithm-device co-design. Materials/fabrication: monolithic 3D integration a must, MUST be low temperature
Addressing Challenges in Neuromorphic Computing with Memristive Synapses
Addressing Challenges in Neuromorphic Computing with Memristive Synapses Vishal Saxena 1, Xinyu Wu 1 and Maria Mitkova 2 1 Analog Mixed-Signal and Photonic IC (AMPIC) Lab 2 Nanoionic Materials and Devices
More informationNeuromorphic computing with Memristive devices. NCM group
Neuromorphic computing with Memristive devices NCM group Why neuromorphic? New needs for computing Recognition, Mining, Synthesis (Intel) Increase of Fault (nanoscale engineering) SEMICONDUCTOR TECHNOLOGY
More informationSynaptic Devices and Neuron Circuits for Neuron-Inspired NanoElectronics
Synaptic Devices and Neuron Circuits for Neuron-Inspired NanoElectronics Byung-Gook Park Inter-university Semiconductor Research Center & Department of Electrical and Computer Engineering Seoul National
More informationMemory and computing beyond CMOS
Memory and computing beyond CMOS Dipartimento di Elettronica, Informazione e Bioingegneria Politecnico di Milano daniele.ielmini@polimi.it Outline 2 Introduction What is CMOS? What comes after CMOS? Example:
More informationNEUROMORPHIC COMPUTING WITH MAGNETO-METALLIC NEURONS & SYNAPSES: PROSPECTS AND PERSPECTIVES
NEUROMORPHIC COMPUTING WITH MAGNETO-METALLIC NEURONS & SYNAPSES: PROSPECTS AND PERSPECTIVES KAUSHIK ROY ABHRONIL SENGUPTA, KARTHIK YOGENDRA, DELIANG FAN, SYED SARWAR, PRIYA PANDA, GOPAL SRINIVASAN, JASON
More informationNeuromorphic Network Based on Carbon Nanotube/Polymer Composites
Neuromorphic Network Based on Carbon Nanotube/Polymer Composites Andrew Tudor, Kyunghyun Kim, Alex Ming Shen, Chris Shaffer, Dongwon Lee, Cameron D. Danesh, and Yong Chen Department of Mechanical & Aerospace
More informationA 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology
A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology M. Kim 1, J. Kim 1, G. Park 1, L. Everson 1, H. Kim 1, S. Song 1,2,
More informationMechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices
Mechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices Rashmi Jha and Branden Long Dept. of Electrical Engineering and Computer Science University of Toledo Toledo,
More informationNeuromorphic computing using non-volatile memory
Advances in Physics: X ISSN: (Print) 2374-6149 (Online) Journal homepage: http://www.tandfonline.com/loi/tapx20 Neuromorphic computing using non-volatile memory Geoffrey W. Burr, Robert M. Shelby, Abu
More informationDemonstration of Logic Operations in High-Performance RRAM Crossbar Array Fabricated by Atomic Layer Deposition Technique
Han et al. Nanoscale Research Letters (2017) 12:37 DOI 10.1186/s11671-016-1807-9 NANO EXPRESS Demonstration of Logic Operations in High-Performance RRAM Crossbar Array Fabricated by Atomic Layer Deposition
More informationDevice and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays Haitong Li, Student Member, IEEE, Peng Huang, Bin Gao, Member, IEEE, Xiaoyan Liu, Member, IEEE, Jinfeng Kang,
More informationMagnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY
Magnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY Magnetic Tunnel Junctions (MTJs) Structure High density memory
More informationMachine Learning. Neural Networks. (slides from Domingos, Pardo, others)
Machine Learning Neural Networks (slides from Domingos, Pardo, others) For this week, Reading Chapter 4: Neural Networks (Mitchell, 1997) See Canvas For subsequent weeks: Scaling Learning Algorithms toward
More informationRE-ENGINEERING COMPUTING WITH NEURO- MIMETIC DEVICES, CIRCUITS, AND ALGORITHMS
RE-ENGINEERING COMPUTING WITH NEURO- MIMETIC DEVICES, CIRCUITS, AND ALGORITHMS Kaushik Roy Abhronil Sengupta, Gopal Srinivasan, Aayush Ankit, Priya Panda, Xuanyao Fong, Deliang Fan, Jason Allred School
More informationMachine Learning. Neural Networks. (slides from Domingos, Pardo, others)
Machine Learning Neural Networks (slides from Domingos, Pardo, others) For this week, Reading Chapter 4: Neural Networks (Mitchell, 1997) See Canvas For subsequent weeks: Scaling Learning Algorithms toward
More informationMTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application
2011 11th Non-Volatile Memory Technology Symposium @ Shanghai, China, Nov. 9, 20112 MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application Takahiro Hanyu 1,3, S. Matsunaga 1, D. Suzuki
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationEmerging Memories: Are They
Emerging Memories: Are They Stanford University Energy Efficient Enough? H. -S. Philip Wong Stanford University 2007.11.08 Center for Integrated Systems Memory Key Enabler for New Applications 256GB 8GB
More informationA Universal Memory Model for Design Exploration. Ketul Sutaria, Chi-Chao Wang, Yu (Kevin) Cao School of ECEE, ASU
A Universal Memory Model for Design Exploration Ketul Sutaria, Chi-Chao Wang, Yu (Kevin) Cao School of ECEE, ASU Universal Memory Modeling because there is no universal memory device! Modeling needs in
More informationApplications of Memristors in ANNs
Applications of Memristors in ANNs Outline Brief intro to ANNs Firing rate networks Single layer perceptron experiment Other (simulation) examples Spiking networks and STDP ANNs ANN is bio inpsired inpsired
More informationA Hybrid CMOS/Memristive Nanoelectronic Circuit for Programming Synaptic Weights
A Hybrid CMOS/Memristive Nanoelectronic Circuit for Programming Synaptic Weights Arne Heittmann and Tobias G. Noll Chair of Electrical Engineering and Computer Systems RWTH Aachen University -52062 Aachen,
More informationEvent-Driven Random Backpropagation: Enabling Neuromorphic Deep Learning Machines
Event-Driven Random Backpropagation: Enabling Neuromorphic Deep Learning Machines Emre Neftci Department of Cognitive Sciences, UC Irvine, Department of Computer Science, UC Irvine, March 7, 2017 Scalable
More informationPost Von Neumann Computing
Post Von Neumann Computing Matthias Kaiserswerth Hasler Stiftung (formerly IBM Research) 1 2014 IBM Corporation Foundation Purpose Support information and communication technologies (ICT) to advance Switzerland
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationConvolutional Neural Networks for Image Recognition and Online Learning Tasks Based on RRAM Devices
1 Convolutional Neural Networks for Image Recognition and Online Learning Tasks Based on RRAM Devices Zhen Dong, Student Member, IEEE, Zheng Zhou, Zefan Li, Chen Liu, Peng Huang, Member, IEEE, Lifeng Liu,
More informationAdministrative Stuff
EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationRRAM technology: From material physics to devices. Fabien ALIBART IEMN-CNRS, Lille
RRAM technology: From material physics to devices Fabien ALIBART IEMN-CNRS, Lille Outline Introduction: RRAM technology and applications Few examples: Ferroelectric tunnel junction memory Mott Insulator
More informationElectrical and Reliability Characteristics of RRAM for Cross-point Memory Applications. Hyunsang Hwang
Electrical and Reliability Characteristics of RRAM for Cross-point Memory Applications Hyunsang Hwang Dept. of Materials Science and Engineering Gwangju Institute of Science and Technology (GIST), KOREA
More informationCenter for Spintronic Materials, Interfaces, and Novel Architectures. Spintronics Enabled Efficient Neuromorphic Computing: Prospects and Perspectives
Center for Spintronic Materials, Interfaces, and Novel Architectures Spintronics Enabled Efficient Neuromorphic Computing: Prospects and Perspectives KAUSHIK ROY ABHRONIL SENGUPTA, KARTHIK YOGENDRA, DELIANG
More informationMachine Learning. Neural Networks. (slides from Domingos, Pardo, others)
Machine Learning Neural Networks (slides from Domingos, Pardo, others) Human Brain Neurons Input-Output Transformation Input Spikes Output Spike Spike (= a brief pulse) (Excitatory Post-Synaptic Potential)
More information3/10/2013. Lecture #1. How small is Nano? (A movie) What is Nanotechnology? What is Nanoelectronics? What are Emerging Devices?
EECS 498/598: Nanocircuits and Nanoarchitectures Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5) Lectures 2: ITRS Nanoelectronics Road Map (Sept 7) Lecture 3: Nanodevices; Guest Lecture by
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationImplementation of a Restricted Boltzmann Machine in a Spiking Neural Network
Implementation of a Restricted Boltzmann Machine in a Spiking Neural Network Srinjoy Das Department of Electrical and Computer Engineering University of California, San Diego srinjoyd@gmail.com Bruno Umbria
More informationNeuromorphic architectures: challenges and opportunites in the years to come
Neuromorphic architectures: challenges and opportunites in the years to come Andreas G. Andreou andreou@jhu.edu Electrical and Computer Engineering Center for Language and Speech Processing Johns Hopkins
More informationA nanoparticle-organic memory field-effect transistor behaving as a programmable spiking synapse
A nanoparticle-organic memory field-effect transistor behaving as a programmable spiking synapse F. Alibart,. Pleutin, D. Guerin, K. Lmimouni, D. Vuillaume Molecular Nanostructures & Devices group, Institute
More informationECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview
407 Computer Aided Design for Electronic Systems Simulation Instructor: Maria K. Michael Overview What is simulation? Design verification Modeling Levels Modeling circuits for simulation True-value simulation
More informationInfluence of electrode materials on CeO x based resistive switching
Influence of electrode materials on CeO x based resistive switching S. Kano a, C. Dou a, M. Hadi a, K. Kakushima b, P. Ahmet a, A. Nishiyama b, N. Sugii b, K. Tsutsui b, Y. Kataoka b, K. Natori a, E. Miranda
More informationMagnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
More informationA brain-inspired neuromorphic architecture for robust neural computation
A brain-inspired neuromorphic architecture for robust neural computation Fabio Stefanini and Giacomo Indiveri Institute of Neuroinformatics University of Zurich and ETH Zurich BIC Workshop @ ISCA40 June
More informationIntroduction. Previous work has shown that AER can also be used to construct largescale networks with arbitrary, configurable synaptic connectivity.
Introduction The goal of neuromorphic engineering is to design and implement microelectronic systems that emulate the structure and function of the brain. Address-event representation (AER) is a communication
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationLast update: October 26, Neural networks. CMSC 421: Section Dana Nau
Last update: October 26, 207 Neural networks CMSC 42: Section 8.7 Dana Nau Outline Applications of neural networks Brains Neural network units Perceptrons Multilayer perceptrons 2 Example Applications
More informationResistive Memories Based on Amorphous Films
Resistive Memories Based on Amorphous Films Wei Lu University of Michigan Electrical Engineering and Computer Science Crossbar Inc 1 Introduction Hysteretic resistive switches and crossbar structures Simple
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. References
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution
More informationNEM Relay Design for Compact, Ultra-Low-Power Digital Logic Circuits
NEM Relay Design for Compact, Ultra-Low-Power Digital Logic Circuits T.-J. K. Liu 1, N. Xu 1, I.-R. Chen 1, C. Qian 1, J. Fujiki 2 1 Dept. of Electrical Engineering and Computer Sciences University of
More informationDecoding. How well can we learn what the stimulus is by looking at the neural responses?
Decoding How well can we learn what the stimulus is by looking at the neural responses? Two approaches: devise explicit algorithms for extracting a stimulus estimate directly quantify the relationship
More informationDigital Object Identifier /JEDS
Received 30 August 2017; revised 21 November 2017; accepted 7 December 2017. Date of publication 11 December 2017; date of current version 15 January 2018. The review of this paper was arranged by Editor
More informationNiobium oxide and Vanadium oxide as unconventional Materials for Applications in neuromorphic Devices and Circuits
Niobium oxide and Vanadium oxide as unconventional Materials for Applications in neuromorphic Devices and Circuits Martin Ziegler, Mirko Hansen, Marina Ignatov, Adrian Petraru, and Hermann Kohlstedt Nanoelektronik,
More informationNovel VLSI Implementation for Triplet-based Spike-Timing Dependent Plasticity
Novel LSI Implementation for Triplet-based Spike-Timing Dependent Plasticity Mostafa Rahimi Azghadi, Omid Kavehei, Said Al-Sarawi, Nicolangelo Iannella, and Derek Abbott Centre for Biomedical Engineering,
More information1. HP's memristor and applications 2. Models of resistance switching. 4. 3D circuit architectures 5. Proposal for evaluation framework
OUTL LINE 1. HP's memristor and applications 2. Models of resistance switching 3. Volatility speed tradeo ffs 4. 3D circuit architectures 5. Proposal for evaluation framework HP S MEMRISTOR memristor =
More informationExperimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization
Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization J. Guy, G. Molas, P. Blaise, C. Carabasse, M. Bernard, A.
More informationDeep Learning with Coherent Nanophotonic Circuits
Yichen Shen, Nicholas Harris, Dirk Englund, Marin Soljacic Massachusetts Institute of Technology @ Berkeley, Oct. 2017 1 Neuromorphic Computing Biological Neural Networks Artificial Neural Networks 2 Artificial
More informationMetal Oxide Resistive Memory using Graphene Edge. Electrode
1 Metal Oxide Resistive Memory using Graphene Edge Electrode Seunghyun Lee 1*, Joon Sohn 1*, Zizhen Jiang 1, Hong-Yu Chen 1,2, H. -S. Philip Wong 1 1 Department of Electrical Engineering and Stanford SystemX
More informationSupporting Information
Copyright WILEY-VCH Verlag GmbH & Co. KGaA, 69469 Weinheim, Germany, 2017. Supporting Information for Adv. Mater., DOI: 10.1002/adma.201602976 Direct Observations of Nanofilament Evolution in Switching
More informationNRAM: High Performance, Highly Reliable Emerging Memory
NRAM: High Performance, Highly Reliable Emerging Memory Sheyang Ning,2, Tomoko Ogura Iwasaki, Darlene Viviani 2, Henry Huang 2, Monte Manning 2, Thomas Rueckes 2, Ken Takeuchi Chuo University 2 Nantero
More informationHw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today
EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS141 2 1 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 Frequency
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
More informationLarge-scale neural modeling
Large-scale neural modeling We re acquiring brain data at an unprecedented rate Dendritic recording Serial Scanning EM Ca ++ imaging Kwabena Boahen Stanford Bioengineering boahen@stanford.edu Goal: Link
More informationBidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part I: Al/Mo/Pr 0.7 Ca 0.3 MnO 3 Material Improvements and Device Measurements
Received 29 August 217; revised 3 October 217; accepted 1 November 217. Date of publication 6 December 217; date of current version 8 January 218. The review of this paper was arranged by Editor S. Moshkalev.
More informationLEADING THE EVOLUTION OF COMPUTE MARK KACHMAREK HPC STRATEGIC PLANNING MANAGER APRIL 17, 2018
LEADING THE EVOLUTION OF COMPUTE MARK KACHMAREK HPC STRATEGIC PLANNING MANAGER APRIL 17, 2018 INTEL S RESEARCH EFFORTS COMPONENTS RESEARCH INTEL LABS ENABLING MOORE S LAW DEVELOPING NOVEL INTEGRATION ENABLING
More informationAdvanced Flash and Nano-Floating Gate Memories
Advanced Flash and Nano-Floating Gate Memories Mater. Res. Soc. Symp. Proc. Vol. 1337 2011 Materials Research Society DOI: 10.1557/opl.2011.1028 Scaling Challenges for NAND and Replacement Memory Technology
More informationMemory Trend. Memory Architectures The Memory Core Periphery
Semiconductor Memories: an Introduction ti Talk Overview Memory Trend Memory Classification Memory Architectures The Memory Core Periphery Reliability Semiconductor Memory Trends (up to the 90 s) Memory
More informationAn Overview of Spin-based Integrated Circuits
ASP-DAC 2014 An Overview of Spin-based Integrated Circuits Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafiné Ravelosona, and Claude Chappert
More informationA final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).
A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). The Final Exam will take place from 12:30PM to 3:30PM on Saturday May 12 in 60 Evans.» All of
More informationTechnological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication
Xia L,Gu P,Li B et al. Technological exploration of RRAM crossbar array for matrix-vector multiplication. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 31(1): 3 19 Jan. 2016. DOI 10.1007/s11390-016-1608-8
More informationLRADNN: High-Throughput and Energy- Efficient Deep Neural Network Accelerator using Low Rank Approximation
LRADNN: High-Throughput and Energy- Efficient Deep Neural Network Accelerator using Low Rank Approximation Jingyang Zhu 1, Zhiliang Qian 2, and Chi-Ying Tsui 1 1 The Hong Kong University of Science and
More informationO 3. /Ni RRAM for synaptic applications
Semiconductor Science and Technology PAPER Understanding the gradual reset in Pt/Al O /Ni RRAM for synaptic applications To cite this article: Biplab Sarkar et al Semicond. Sci. Technol. Manuscript version:
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationEE410 vs. Advanced CMOS Structures
EE410 vs. Advanced CMOS Structures Prof. Krishna S Department of Electrical Engineering S 1 EE410 CMOS Structure P + poly-si N + poly-si Al/Si alloy LPCVD PSG P + P + N + N + PMOS N-substrate NMOS P-well
More informationOutline. Neural dynamics with log-domain integrator circuits. Where it began Biophysics of membrane channels
Outline Neural dynamics with log-domain integrator circuits Giacomo Indiveri Neuromorphic Cognitive Systems group Institute of Neuroinformatics niversity of Zurich and ETH Zurich Dynamics of Multi-function
More informationFinding the Missing Memristor
February 11, 29 Finding the Missing Memristor 3 nm Stan Williams HP 26 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice Acknowledgments People
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationSize-dependent Metal-insulator Transition Random Materials Crystalline & Amorphous Purely Electronic Switching
Nanometallic RRAM I-Wei Chen Department of Materials Science and Engineering University of Pennsylvania Philadelphia, PA 19104 Nature Nano, 6, 237 (2011) Adv Mater,, 23, 3847 (2011) Adv Func Mater,, 22,
More informationHow to do backpropagation in a brain
How to do backpropagation in a brain Geoffrey Hinton Canadian Institute for Advanced Research & University of Toronto & Google Inc. Prelude I will start with three slides explaining a popular type of deep
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationNeural Networks. Mark van Rossum. January 15, School of Informatics, University of Edinburgh 1 / 28
1 / 28 Neural Networks Mark van Rossum School of Informatics, University of Edinburgh January 15, 2018 2 / 28 Goals: Understand how (recurrent) networks behave Find a way to teach networks to do a certain
More informationCMSC 421: Neural Computation. Applications of Neural Networks
CMSC 42: Neural Computation definition synonyms neural networks artificial neural networks neural modeling connectionist models parallel distributed processing AI perspective Applications of Neural Networks
More informationQuasi Analog Formal Neuron and Its Learning Algorithm Hardware
Quasi Analog Formal Neuron and Its Learning Algorithm Hardware Karen Nazaryan Division of Microelectronics and Biomedical Devices, State Engineering University of Armenia, 375009, Terian Str. 105, Yerevan,
More informationSemiconductor memories
Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor
More informationGPU-accelerated Computing at Scale. Dirk Pleiter I GTC Europe 10 October 2018
GPU-accelerated Computing at Scale irk Pleiter I GTC Europe 10 October 2018 Outline Supercomputers at JSC Future science challenges Outlook and conclusions 2 3 Supercomputers at JSC JUQUEEN (until 2018)
More informationNTE74176 Integrated Circuit TTL 35Mhz Presettable Decade Counter/Latch
NTE74176 Integrated Circuit TTL 35Mhz Presettable Decade Counter/Latch Description: The NTE74176 is a high speed monolithic counter in a 14 Lead plastic DIP type package consisting of four DC coupled master
More informationSTDP Learning of Image Patches with Convolutional Spiking Neural Networks
STDP Learning of Image Patches with Convolutional Spiking Neural Networks Daniel J. Saunders, Hava T. Siegelmann, Robert Kozma College of Information and Computer Sciences University of Massachusetts Amherst
More informationDRAMATIC advances in technology scaling have given us
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004 919 Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI Hiromitsu Kimura, Member, IEEE, Takahiro Hanyu, Member,
More informationKnowledge Extraction from DBNs for Images
Knowledge Extraction from DBNs for Images Son N. Tran and Artur d Avila Garcez Department of Computer Science City University London Contents 1 Introduction 2 Knowledge Extraction from DBNs 3 Experimental
More informationEffective Capacitance Enhancement Methods for 90-nm DRAM Capacitors
Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 112 116 Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors Y. K. Park, Y. S. Ahn, S. B. Kim, K. H. Lee, C. H.
More informationUltralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches Presenter: Tulika Mitra Swarup Bhunia, Massood Tabib-Azar, and Daniel Saab Electrical Eng. And
More informationMoores Law for DRAM. 2x increase in capacity every 18 months 2006: 4GB
MEMORY Moores Law for DRAM 2x increase in capacity every 18 months 2006: 4GB Corollary to Moores Law Cost / chip ~ constant (packaging) Cost / bit = 2X reduction / 18 months Current (2008) ~ 1 micro-cent
More informationHow to outperform a supercomputer with neuromorphic chips
How to outperform a supercomputer with neuromorphic chips Kwabena Boahen Stanford Bioengineering boahen@stanford.edu Telluride Acknowledgements Paul Merolla John Arthur Joseph Kai Lin Hynna BrainsInSilicon.stanford.edu
More informationAccess from the University of Nottingham repository:
ElHassan, Nemat Hassan Ahmed (2017) Development of phase change memory cell electrical circuit model for non-volatile multistate memory device. PhD thesis, University of Nottingham. Access from the University
More informationmaterials, devices and systems through manipulation of matter at nanometer scale and exploitation of novel phenomena which arise because of the
Nanotechnology is the creation of USEFUL/FUNCTIONAL materials, devices and systems through manipulation of matter at nanometer scale and exploitation of novel phenomena which arise because of the nanometer
More informationSemiconductor Memory Classification
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationArtificial Neural Network and Fuzzy Logic
Artificial Neural Network and Fuzzy Logic 1 Syllabus 2 Syllabus 3 Books 1. Artificial Neural Networks by B. Yagnanarayan, PHI - (Cover Topologies part of unit 1 and All part of Unit 2) 2. Neural Networks
More informationVLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationBiological Modeling of Neural Networks:
Week 14 Dynamics and Plasticity 14.1 Reservoir computing - Review:Random Networks - Computing with rich dynamics Biological Modeling of Neural Networks: 14.2 Random Networks - stationary state - chaos
More informationLow Power Phase Change Memory via Block Copolymer Self-assembly Technology
Low Power Phase Change Memory via Block Copolymer Self-assembly Technology Beom Ho Mun 1, Woon Ik Park 1, You Yin 2, Byoung Kuk You 1, Jae Jin Yun 1, Kung Ho Kim 1, Yeon Sik Jung 1*, and Keon Jae Lee 1*
More informationUNSUPERVISED LEARNING
UNSUPERVISED LEARNING Topics Layer-wise (unsupervised) pre-training Restricted Boltzmann Machines Auto-encoders LAYER-WISE (UNSUPERVISED) PRE-TRAINING Breakthrough in 2006 Layer-wise (unsupervised) pre-training
More informationDeep Learning Srihari. Deep Belief Nets. Sargur N. Srihari
Deep Belief Nets Sargur N. Srihari srihari@cedar.buffalo.edu Topics 1. Boltzmann machines 2. Restricted Boltzmann machines 3. Deep Belief Networks 4. Deep Boltzmann machines 5. Boltzmann machines for continuous
More information